DETAILED ACTION
The instant application having Application No. 19/260,132 has a total of 24 claims pending in the application, there are 3 independent claims and 21 dependent claims, all of which are ready for examination by the examiner.
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant's drawings submitted 7/3/2025 are acceptable for examination purposes.
REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-24 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al (US 2023/0026323).
Regarding Claim 1, Kim teaches a memory system, comprising:
one or more memory devices (memory device 100 of Fig. 1); and
processing circuitry coupled with the one or more memory devices (host 400 of Fig. 1) and configured to cause the memory system to:
receive a read command indicating a first set of one or more logical addresses and a second set of one or more logical addresses that is non-contiguous with the first set of one or more logical addresses (a host may submit a multi-read command to the memory device, Paragraph 0126, which is “a read command for at least two or more logical addresses,” Paragraph 0151, also see the sets of one or more logical addresses shown on Fig. 10A, and further the multi-read is “an operation of simultaneously reading a plurality of logical addresses that are not successive [non-contiguous] to each other,” Paragraph 0107), the first set of one or more logical addresses and the second set of one or more logical addresses associated with a set of sequential data (see Fig. 15, where it is shown the first and second set of logical addresses are associated with a set of sequential data shown on the right-hand side of the figure as Data #1, Data #2, etc.);
access at least one of the one or more memory devices at a plurality of physical addresses corresponding to the first set of one or more logical addresses and the second set of one or more logical addresses to retrieve the set of sequential data in response to the read command (“When … the multi-read operation is performed, data of a plurality of areas of which logical addresses are not successive may be simultaneously read and obtained,” Paragraph 0151, also note that physical addresses are used to access the memory device, Paragraph 0131-0133); and
output the set of sequential data in accordance with accessing the at least one of the one or more memory devices (“the data obtained by the multi-read operation may be provided [output] to the host,” Paragraph 0152).
Regarding Claim 2, the cited prior art teaches the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
receive, prior to receiving the read command, one or more write commands indicating to store the set of sequential data in accordance with the first set of one or more logical addresses and the second set of one or more logical addresses that is non-contiguous with the first set of one or more logical addresses (“a memory controller configured to receive a write command from an external host and control the memory device according to the write command,” and it is “a write command for at least two or more logical addresses,” Paragraph 0182, therefore this command may be used to store the set of sequential data); and
store the set of sequential data to the plurality of physical addresses of the one or more memory devices, wherein the plurality of physical addresses comprise a first set of one or more physical addresses mapped to the first set of one or more logical addresses and a second set of one or more physical addresses mapped to the second set of one or more logical addresses (“a memory controller configured to receive a write command from an external host and control the memory device according to the write command,” and it is “a write command for at least two or more logical addresses,” Paragraph 0182, therefore this command may be used to store the set of sequential data at different physical addresses corresponding to the logical addresses).
Regarding Claim 3, the cited prior art teaches the memory system of claim 1, wherein the plurality of physical addresses are located within a single memory device of the one or more memory devices (see single memory device 100 of Fig. 1).
Regarding Claim 4, the cited prior art teaches the memory system of claim 1, wherein the plurality of physical addresses are located within a first memory device of the one or more memory devices and within a second memory device of the one or more memory devices (though only one device is shown on Fig. 1, there may be multiple devices 100 and therefore the plurality of physical addresses may be located within a first and second memory device, Paragraph 0050).
Regarding Claim 5, the cited prior art teaches the memory system of claim 1, wherein the first set of one or more logical addresses and the second set of one or more logical addresses are included, within the read command, in an extra header segment (EHS) data field (see logical addresses in the EHS data field of a read command in the bottom-right corner of Fig. 10B).
Regarding Claim 6, the cited prior art teaches the memory system of claim 5, wherein one or more second fields of the read command indicate that the EHS data field includes the first set of one or more logical addresses and the second set of one or more logical addresses, and wherein accessing the at least one of the one or more memory devices in accordance with the first set and the second set is in response to the one or more second fields indicating that the EHS data field includes the first set and the second set (the second field corresponding to “the read command descriptor block (CDB),” which is “information indicating whether the read request is the read request for the at least two or more logical addresses,” Paragraph 0129).
Regarding Claim 7, the cited prior art teaches the memory system of claim 6, wherein the one or more second fields comprise a length field, an EHS type field, an EHS sub-type field, or any combination thereof (the read command descriptor block signifies the length of the read and is therefore a length field, Paragraph 0129).
Regarding Claim 8, the cited prior art teaches the memory system of claim 1, wherein the first set of one or more logical addresses corresponds to a first set of logical block addresses and the second set of one or more logical addresses corresponds to a second set of logical block addresses (see logical block addresses in the bottom-right section of the read command of Fig. 10B).
Claim 9 is the non-transitory computer-readable medium corresponding to the memory system of claim 1, and is rejected under similar rationale.
Claim 10 is the non-transitory computer-readable medium corresponding to the memory system of claim 2, and is rejected under similar rationale.
Claim 11 is the non-transitory computer-readable medium corresponding to the memory system of claim 3, and is rejected under similar rationale.
Claim 12 is the non-transitory computer-readable medium corresponding to the memory system of claim 4, and is rejected under similar rationale.
Claim 13 is the non-transitory computer-readable medium corresponding to the memory system of claim 5, and is rejected under similar rationale.
Claim 14 is the non-transitory computer-readable medium corresponding to the memory system of claim 6, and is rejected under similar rationale.
Claim 15 is the non-transitory computer-readable medium corresponding to the memory system of claim 7, and is rejected under similar rationale.
Claim 16 is the non-transitory computer-readable medium corresponding to the memory system of claim 8, and is rejected under similar rationale.
Claim 17 is the method corresponding to the memory system of claim 1, and is rejected under similar rationale.
Claim 18 is the method corresponding to the memory system of claim 2, and is rejected under similar rationale.
Claim 19 is the method corresponding to the memory system of claim 3, and is rejected under similar rationale.
Claim 20 is the method corresponding to the memory system of claim 4, and is rejected under similar rationale.
Claim 21 is the method corresponding to the memory system of claim 5, and is rejected under similar rationale.
Claim 22 is the method corresponding to the memory system of claim 6, and is rejected under similar rationale.
Claim 23 is the method corresponding to the memory system of claim 7, and is rejected under similar rationale.
Claim 24 is the method corresponding to the memory system of claim 8, and is rejected under similar rationale.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
Jang et al (US 2026/0016988) teaches COMPUTING SYSTEM FOR STORING DATA AND METHOD OF OPERATING THE SAME.
Xu et al (US 2025/0244901) teaches STORAGE CONTROLLER, DATA READING METHOD AND STORAGE DEVICE.
CLOSING COMMENTS
Conclusion
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. ' 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-24 have been rejected.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mark Giardino whose telephone number is (571) 270-3565 and can normally be reached on M-F 9:00-5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Jared Rutz can be reached at 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
/MARK A GIARDINO JR/Primary Examiner, Art Unit 2135
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