DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1 – 4, 10 -13, 17, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Joshi et al (US Patent Number 10,963,615, hereinafter “Joshi”) in view of Mathuna et al. (US Publication Number 2002/0116562, hereinafter “Mathuna”).
4. As per claims 1, 13, and 20 Joshi teaches a method, system, and non-transitory computer-readable storage medium (application design system 500 with CPU 506 and memory 508, figure 5) comprising: a routing cost estimation tool (compiler routing module 706 of DPE array compiler module 608, figure 7) for routing a logical edge (net pf the netlist, figure 7, column 19, lines 40 – 67) between a logical producer unit (source block of the net, columns 19 and 20) and a logical consumer unit (destination block of the net, columns 19 and 20) onto a reconfigurable processor (DPE array 102 with configurable stream switches 214 where routing module 706 generates global and detailed routes per net through stream switches of DPE array and routed netlist compiled into binaries 714 loaded to configure array, figures 1, 2, 5, and 7 – 9), wherein the cost estimation tool is configured to: receive a tentative assignment of the logical edge, the logical producer unit, and the logical consumer unit to a physical link (edge of modeled stream switch 912, figure 9), a physical producer unit (core 202/memory bank 302 mapping source kernel/buffer, figures 2 and 3), and a physical consumer unit (core 202/memory bank 302 to which destination is mapped) of the reconfigurable processor, respectively (mapping module 704 maps kernels to cores and buffers memory banks, routing module 706 routes each net through switch edges and mapping and routing may be iteratively performed, so each mapping and route, figures 7 – 9).
Joshi does not appear to explicitly disclose determine a number of active cycles of the logical edge; determine a number of stage cycles; determine a scaling factor of a realized bandwidth based on a division of the number of active cycles by the number of stage cycles; and determine a realized bandwidth consumption of the tentative assignment based on the scaling factor of the realized bandwidth.
However, Mathuna discloses determine a number of active cycles of the logical edge (master counter registers 100a…z count cycles of bus ownership by each bus master, a master acting as data producer/consumer, figure 5, paragraphs 2 and 5); determine a number of stage cycles (real-time counter 96, register 104, figure 5, counts all bs cycles that occur during a time period ending with a profile event, paragraphs 5 and 25); determine a scaling factor of a realized bandwidth based on a division of the number of active cycles by the number of stage cycles (cycles owned during a given time period are proportional to bus bandwidth consumption of master and calculated from owned cycle counts against real time count, the proportionality ration, paragraphs 2 – 6); and determine a realized bandwidth consumption (estimate bandwidth consumption before implementation, paragraph 20) of the tentative assignment based on the scaling factor of the realized bandwidth (paragraphs 3 and 20).
Joshi and Mathuna are analogous art because they are from the same field of endeavor of data routing.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Joshi and Mathuna before him or her, to modify the mechanism of Joshi to include the cycle handling of Mathuna because it would enhance data delivery on a bus.
One of ordinary skill would be motivated to make such modification in order to enhance bus utilization (paragraphs 5 and 6). Therefore, it would have been obvious to combine Mathuna with Joshi to obtain the invention as specified in the instant claims.
5. Joshi modified by the teachings of Mathuna as seen in claim 1 above, as per claim 2, Joshi teaches a method, wherein the reconfigurable processor comprises arrays of coarse-grained reconfigurable (CGR) units (DPE array 102 of 104 with core 202 and memory 204 and stream switch 214, figures 1 and 2 each set through configuration registers 210/212/216 and array configured by binaries 714, figures 2 and 7).
6. Joshi modified by the teachings of Mathuna as seen in claim 1 above, as per claim 3, Joshi teaches a method, wherein the logical consumer unit comprises a compute unit (core 202, figure 2) or a memory unit (memory 302 of 204, figure 3, kernel mapped to core/buffer mapped to memory, figures 2, 3, and 7).
7. Joshi modified by the teachings of Mathuna as seen in claim 1 above, as per claim 4, Joshi teaches a method, further comprising: providing the realized bandwidth consumption of the tentative assignment as a cost estimation (each net’s edge utilization summed against capacity and weighted route slack is minimized, figure 9) to a placement and routing tool (compiler mapping module 704 and compiler routing module 706, figure 7, iteratively performed optimization).
8. Joshi modified by the teachings of Mathuna as seen in claim 1 above, as per claims 10, 11, and 17, Joshi teaches a method and system, wherein, for determining the number of active cycles of the logical edge (cycles per master, paragraph 5), the cost estimation tool is further configured to: determine all paths that pass through the logical edge; determine an accumulated active cycle for each one of all the paths that pass through the logical edge; and determine the number of active cycles as a maximum accumulated active cycle of the accumulated active cycle for each one of all the paths that pass through the logical edge (path determination and Manhattan distance between source and destination columns 19 and 20).
9. Joshi modified by the teachings of Mathuna as seen in claim 1 above, as per claims 10, 12, and 18, Joshi teaches a method and system, further comprising: determining a sum of realized average bandwidths of all the logical edges that are assigned to use the physical link (edge of modeled stream switch 912, figure 9) to determine a congestion estimation of the physical link (sum over all nets routed through edge remain below capacity of totals every nets use, figure 9); and determining the realized bandwidth consumption of the tentative assignment based on the scaling factor of the realized bandwidth (Mathuna: paragraphs 3, 20) and the congestion estimation of the physical link (route cumulative utilization remains within capacity, figure 9).
10. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Joshi in view of Mathuna further in view of Guo et al. (US Publication Number 2014/0314076, hereinafter “Guo”).
11. Joshi modified by the teachings of Mathuna as seen in claim 1 above, as per claim 5, Mathuna teaches a method, further comprising: and determining the realized bandwidth consumption of the tentative assignment based on the scaling factor of the realized bandwidth (paragraphs 3 and 20)
12. Joshi/Mathuna does not appear to explicitly disclose determining an end-to-end bandwidth between the physical producer unit and the physical consumer unit; and the end-to-end bandwidth.
However, Guo discloses determining an end-to-end bandwidth (credit loop 905 – 920, figure 9) between the physical producer unit (upstream router, figure 4b) and the physical consumer unit (downstream router, figure 4b, paragraph 48, credit round trip delay Tcrt is parameter that determines max throughput a credit based flow control mechanism can support, paragraph 75, buffer space sized against Tcrt to decide channel bandwidth limit, figure 9, paragraph 77); and the end-to-end bandwidth (Tcrt limited ceiling cap bandwidth for channel, paragraphs 75 and 77).
Joshi/Mathuna and Guo are analogous art because they are from the same field of endeavor of latency handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Joshi/Mathuna and Guo before him or her, to modify the mechanism of Joshi/Mathuna to include the bandwidth handling of Guo because it would enhance data routing techniques.
One of ordinary skill would be motivated to make such modification in order to enhance storage efficiency (paragraph 26). Therefore, it would have been obvious to combine Guo with Joshi/Mathuna to obtain the invention as specified in the instant claims.
13. Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Joshi in view of Mathuna further in view of Kumar et al. (US Publication Number 2014/0098683, hereinafter “Kumar”).
14. Joshi modified by the teachings of Mathuna as seen in claim 1 above, as per claims 9 and 19, Mathuna teaches a method and system comprising a scaling factor of the realized bandwidth (paragraphs 3 and 20).
Joshi/Mathuna does not appear to explicitly disclose a method and system further comprising: determining an upper output bandwidth limit of the logical producer unit, an upper input bandwidth limit of the logical consumer unit, and an upper bandwidth limit of the logical edge based on the upper output bandwidth limit and the upper input bandwidth limit; and determining the realized bandwidth consumption of the tentative assignment based on the upper bandwidth limit of the logical edge.
However, Kumar discloses a method and system further comprising: determining an upper output bandwidth limit (peak transmit rate, paragraph 42) of the logical producer unit (source component, paragraph 42), an upper input bandwidth limit (peak receive rate, paragraph 42) of the logical consumer unit (destination, paragraph 42), and an upper bandwidth limit (capacity of an edge of flow graph, figure 6) of the logical edge based on the upper output bandwidth limit and the upper input bandwidth limit (capacity of an edge is max rate of source components can send data long route without exceeding peak transmit rate of source and peak receive rate of destination, figure 6); and determining the realized bandwidth consumption of the tentative assignment based on the upper bandwidth limit of the logical edge (edge capacity caps rate route can carry, figure 6).
Joshi/Mathuna and Kumar are analogous art because they are from same field of endeavor latency management.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Joshi/Mathuna and Kumar before him or her, to modify the mechanism of Joshi/Mathuna to include the bandwidth handling of Kumar because it would enhance the bandwidth range integrity of data transmissions.
One of ordinary skill would be motivated to make such modification in order to enhance traffic management efficiency (paragraphs 13 – 15). Therefore, it would have been obvious to combine Kumar with Joshi/Mathuna to obtain the invention as specified in the instant claims.
Allowable Subject Matter
15. Claims 6 – 8 and 14 – 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
16. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Abts/Brownell/Fleming/Gupta/Ravi/Wilkinson/Zhao has teachings of latency bandwidth handling.
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AH
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
