DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of elect Invention I in the reply filed on 6/23/2026 is acknowledged.
Claims 1 – 14 are pending for consideration.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 – 5, 10, 11, 13, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Bong et al. (U.S. Patent Publication 20230044555 A1 Filed: 8/3/2021) in view Kim et al. (U.S. Patent Publication 20240005846 A1, Assignee: Samsung, Filed: 6/30/2022).
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Regarding claim 1, Bong discloses A display device, comprising:
a display panel where a plurality of gate lines (Fig. 1, GL), a plurality of data lines (Fig. 1, DL), and a plurality of subpixels (Fig. 1, PX) are disposed;
a gate driving circuit (Fig. 1, GD) configured to supply a plurality of gate signals to the plurality of gate lines; ([0043] [0045]) and
a controller (Fig. 1, controller 130) configured to control the gate driving circuit, ([0048] – [0053])
wherein the gate driving circuit (Fig. 1, GD) is configured to adjust a voltage level of a first gate high voltage to generate a gate low voltage and to output an emission control gate signal based on the second gate high voltage among the plurality of gate signals in at least one interval in a single frame period. (Figs, 3, 8, 10, [0092] he scan signal Scan(n) may have the gate high voltage VGH having the first voltage level in the first and third to fifth intervals ①, ③, ④, and ⑤ and may have the gate low voltage VGL having the second voltage level in the second interval ②. A pulse of the scan signal Scan(n) having the gate low voltage VGL may have a period of one horizontal period 1H in one frame in an interval where a phase of the first emission control signal EM1(n) overlaps a phase of the second emission control signal EM2(n). A pulse period of the scan signal Scan(n) may be variously changed according to embodiments. [0088] – [0091] )
Bong does not disclose “adjust a voltage level of a first gate high voltage to generate a second gate high voltage”.
Kim discloses “adjust a voltage level of a first gate high voltage to generate a second gate high voltage”. ([0173] [0192] the first voltage VGH is changed from the first high voltage level VH1 to the second high voltage level VH2 [0189] [0193] – [0197])
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate different voltage high level by Kim into device of Bong. The suggestion/motivation would have been to improve efficiency. (Kim: [0192])
Regarding claim 2, Bong and Kim disclose wherein a voltage level of the second gate high voltage is lower than the voltage level of the first gate high voltage. (Kim [0189] [0193] – [0197] [0192])
Regarding claim 3, Bong and Kim disclose wherein the gate driving circuit is configured to output the emission control gate signal based on the second gate high voltage during at least one vertical blank interval in the single frame period. (Kim [0189] [0193] – [0197] [0192])
Regarding claim 4, Bong and Kim disclose wherein the gate driving circuit is configured to output the emission control gate signal based on the second gate high voltage during at least one interval when a number of subpixels emitting light among the plurality of subpixels in the single frame period is less than a threshold number. (Kim [0189] [0193] – [0197] [0192])
Regarding claim 5, Bong and Kim disclose wherein the gate driving circuit includes: a first multiplexer configured to output one of the first gate high voltage or the second gate high voltage; and an emission control driver configured to output the emission control gate signal based on the one of the first gate high voltage or the second gate high voltage. (Kim [0189] [0193] – [0197] [0192])
Regarding claim 10, Bong and Kim disclose wherein the gate driving circuit is configured to adjust a first gate low voltage to generate a second gate low voltage and to output an emission control gate signal based on the second gate high voltage and the second gate low voltage through the at least one gate line in at least one interval in the single frame period. (Bong [0088] – [0092])
Regarding claim 11, Bong and Kim disclose wherein a voltage level of the second gate low voltage is higher than a voltage level of the first gate low voltage. (Bong [0088] – [0094])
Regarding claim 13, Bong and Kim disclose wherein the gate driving circuit includes at least one scan driver configured to output at least one scan gate signal among the plurality of gate signals based on the first gate high voltage and a gate low voltage. (Bong [0088] – [0094])
Regarding claim 14, Bong and Kim disclose wherein the second gate high voltage and the second gate low voltage are set such as to minimize a difference in voltage levels of the emission control gate signal between the at least one interval and an interval adjacent to the at least one interval. (Bong [0088] – [0094])
Alternately, claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. Patent Publication 20250209980 A1, Filed: 12/20/2023) in view of Bong et al. (U.S. Patent Publication 20230044555 A1).
Regarding claim 1, Lee discloses A display device, comprising:
a display panel where a plurality of gate lines (Fig. 1, GL_1, GL_2 [0048] [0049]) , a plurality of data lines (Fig. 1, DL [0048] [0049]), and a plurality of subpixels (Fig. 1, PX) are disposed;
a gate driving circuit (Fig. 1, gate driver 20) configured to supply a plurality of gate signals to the plurality of gate lines; and
a controller (Fig. 1, timing controller 10 [0046]) configured to control the gate driving circuit,
wherein the gate driving circuit is configured to adjust a voltage level of a first gate high voltage to generate a second gate high voltage and to output an emission control gate signal based on the second gate high voltage among the plurality of gate signals in at least one interval in a single frame period. ([0010] The emission signal may be a square wave signal including a gate high voltage period and a gate low voltage period, and the emission signal voltage controller may change the gate high voltage based on a luminance difference of the image data between adjacent frames. [0011] The emission signal voltage controller may set the gate high voltage to a first gate high voltage when the luminance difference between the adjacent frames is smaller than a critical value, and set the gate high voltage to a second gate high voltage smaller than the first gate high voltage when the luminance difference between the adjacent frames is greater than the critical value.)
Lee does not disclose “among the plurality of gate signals in at least one interval in a single frame period”.
Bong discloses “among the plurality of gate signals in at least one interval in a single frame period”. ([0092])
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate single frame by Bong into device of Lee. The suggestion/motivation would have been to improve efficiency. (Bong: [0092])
Allowable Subject Matter
Claims 6 – 9, 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20200082768 A1 discloses emission control signal on abstract.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN-NAN LIN whose telephone number is (571)272-5646. The examiner can normally be reached Monday - Thursday 7:30am - 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin C Lee can be reached at 571-2722963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN-NAN LIN/Primary Examiner, Art Unit 2629
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