DETAILED ACTION
The instant application having Application No. 19/261,526 has a total of 20 claims pending in the application, all of which are ready for examination by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The instant application 19/261,526 filed 7/7/2025 is a Continuation of 17/973,950 filed 10/26/2022, now U.S. Patent #12353325.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 13, and 20 recite region of L2P map corresponding to a respective logical address range. Where the claims and claims dependent thereon further recite L2P regions, it is unclear as to whether the region and L2P region are intended to correspond to the same or different subject matter. The examiner suggests amending the limitation, “wherein each region of the L2P map corresponds to a respective logical address range” in claims 1, 13, and 20 as “wherein each L2P region of the L2P map corresponds to a respective logical address range”.
Claim 1 recites a response message comprising information about a changed L2P region, a to-be-loaded L2P region, and an invalid L2P region. Each of the L2P regions as listed are respectively recited as identifying regions (i.e. a plurality of regions) having respective attributes. The intended subject matter of the limitations is unclear, as the limitations appear to provide that the response message comprises information about, for example, a single invalid L2P region, and that the single invalid L2P region identifies a plurality of regions that are no longer valid. The examiner suggests amending claim 1 to provide that said response message comprises changed L2P region information, to-be-loaded L2P information, and invalid L2P region information, in a manner similar to the recitations of independent claims 13 and 20.
Claims 2-12 and 14-19 are rejected for being dependent on a rejected claim.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-5, 7-11, 13-16, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 7-10, and 15 of U.S. Patent No. 12353325, Widder et al. (US 20190004944 A1) and King et al. (US 20030093721 A1). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the co-pending applications disclose/obviate the claims on the instant application.
Note that (MPEP 804.0 (I.B.1)) states: A complete response to a nonstatutory double patenting (NDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional.
As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. Therefore, an application must not be allowed unless the required compliant terminal disclaimer(s) is/are filed and/or the withdrawal of the nonstatutory double patenting rejection(s) is made of record by the examiner. See MPEP § 804.02, subsection VI, for filing terminal disclaimers required to overcome nonstatutory double patenting rejections in applications filed on or after June 8, 1995.
Instant application 19/261,526
U.S. Patent #12353325 (corresponding to Application # 17/973,950)
1. A system comprising:
a storage system comprising a memory controller and a memory array, the storage system configured to maintain a relationship between a logical block address (LBA) and a physical address (PA) of data stored by the memory array in a logical-to-physical (L2P) map, and to provide L2P information to a host device, wherein each region of the L2P map corresponds to a respective logical address range;
wherein the memory controller is configured to receive a memory request from the host device and, in response, provide a response message comprising information about:
a changed L2P region identifying regions previously provided to the host device that are no longer valid but remain available to the storage system without loading from the memory array;
a to-be-loaded L2P region identifying regions ready for loading by the host device but not yet transferred to the host device; and
an invalid L2P region identifying regions that are no longer valid and require loading from the memory array.
5. The system of claim 1, wherein the memory controller is configured to determine L2P state changes in different L2P regions and subregions of the memory array based on changes in the L2P map at the storage system, wherein the L2P states of L2P regions and subregions include valid, changed, to-be-loaded, and invalid states.
7. The system of claim 1, wherein the response message comprises sequential fields, each field allocated a predetermined number of bytes and comprising (1) a first single-byte portion storing a region index and (2) a second single-byte portion storing a most significant bit and (3) a third single-byte portion storing a least significant bit.
8. The system of claim 7, wherein the sequential fields include:
(1) a first field comprising changed L2P region and subregion information identifying regions previously provided to the host device that are no longer valid but remain available to the storage system without loading from the memory array;
(2) a second field comprising to-be-loaded L2P region and subregion information identifying regions ready for host device loading but not yet transferred to the host device; and
(3) a third field comprising invalid L2P region and subregion information identifying regions that are no longer valid and require loading from the memory array.
1. A system comprising:
a storage system comprising a memory controller and a memory array, the storage system configured to maintain a relationship between a logical block address (LBA) and a physical address (PA) of data stored on the memory array in a logical-to-physical (L2P) map, and to provide L2P information to a host device,
wherein the memory controller is configured to:
determine L2P state changes in different L2P regions and subregions of the memory array based on changes in the L2P map at the storage system, wherein the L2P states of L2P regions and subregions include valid, changed, to-be-loaded, and invalid states; and
provide, as a response to a host memory request from the host device including an invalid L2P region or subregion, a response information unit based on the determined L2P state changes, wherein the response information unit comprises sequential fields, each allocated a predetermined number of bytes limited in size and comprising a region portion consuming one byte for storing a region index and a subregion portion consuming one byte for a most significant bit and one byte for a least significant bit,
wherein the sequential fields include:
(1) a first field comprising changed L2P region and subregion information identifying regions previously provided to the host device that are no longer valid but remain available to the storage system without loading from the memory array;
(2) a second field comprising to-be-loaded L2P region and subregion information identifying regions ready for host device loading but not yet transferred to the host device; and
(3) a third field comprising invalid L2P region and subregion information identifying regions that are no longer valid and require loading from the memory array.
2. The system of claim 1, wherein a size of subregions within the logical address ranges is 4K bytes, and wherein each logical address range comprises multiple subregions.
2. The system of claim 1, wherein a size of one or more of the changed L2P subregion, the to-be-loaded L2P subregion, or the invalid L2P subregion on the memory array is 4K bytes, and
wherein one or more of the changed L2P region, the to-be-loaded L2P region, or the invalid L2P region comprises multiple subregions.
3. The system of claim 1, wherein the host device is configured to request L2P information from the storage system using an L2P read buffer command.
7. The system of claim 1, comprising the host device,
wherein the host device is configured to request L2P information from the storage system using an L2P read buffer command, and to receive and store the requested L2P information at the host device.
9. The system of claim 8, wherein a size of one or more of the changed L2P subregion, the to-be-loaded L2P subregion, or the invalid L2P subregion on the memory array is 4K bytes, and wherein one or more of the changed L2P region, the to-be-loaded L2P region, or the invalid L2P region comprises multiple subregions.
2. The system of claim 1, wherein a size of one or more of the changed L2P subregion, the to-be-loaded L2P subregion, or the invalid L2P subregion on the memory array is 4K bytes, and
wherein one or more of the changed L2P region, the to-be-loaded L2P region, or the invalid L2P region comprises multiple subregions.
10. The system of claim 8, wherein the changed L2P region information, the to-be-loaded L2P region information, and the invalid L2P region information in the response message are each 1 byte in size, and wherein the changed L2P subregion information, the to-be-loaded L2P subregion information, or the invalid L2P subregion information in the response message are each 2 bytes in size, including one byte for a most significant bit (MSB) and one byte for a least significant bit (LSB).
3. The system of claim 2, wherein the changed L2P region information, the to-be-loaded L2P region information, and the invalid L2P region information in the response information unit are each 1 byte in size, and
wherein the changed L2P subregion information, the to-be-loaded L2P subregion information, or the invalid L2P subregion information in the response information unit are each 2 bytes in size, including one byte for a most significant bit (MSB) and one byte for a least significant bit (LSB).
13. A system comprising:
a storage system comprising a memory controller and a memory array, the storage system configured to maintain a relationship between a logical block address (LBA) and a physical address (PA) of data stored on the memory array in a logical-to-physical (L2P) map, and to provide L2P information to a host device, wherein each region of the L2P map corresponds to a respective logical address range;
wherein the memory controller is configured to:
determine L2P state changes in different L2P regions and subregions of the memory array based on changes in the L2P map at the storage system, wherein the L2P states of L2P regions and subregions include valid, changed, to-be-loaded, and invalid states;
notify the host device that L2P information should be updated using an L2P update needed flag; and
provide, as a response to a host memory request, a response message having a limited size and comprising:
changed L2P region and associated subregion information identifying regions previously provided to the host device that are no longer valid but remain available to the storage system without loading from the memory array;
to-be-loaded L2P region and associated subregion information identifying regions ready for host device loading but not yet transferred to the host device; and
invalid L2P region and associated subregion information identifying regions that are no longer valid and require loading from the memory array.
8. A method comprising:
maintaining, using a storage system comprising a memory controller and a memory array, a relationship between a logical block address (LBA) and a physical address (PA) of data stored on the memory array in a logical-to-physical (L2P) map, and providing L2P information to a host device;
determining, using the memory controller, L2P state changes in different L2P regions and subregions of the memory array based on changes in the L2P map at the storage system, wherein the L2P states of L2P regions and subregions include valid, changed, to-be-loaded, and invalid states; and
providing, as a response to a host memory request from the host device including an invalid L2P region or subregion, a response information unit based on the determined L2P state changes, wherein the response information unit comprises sequential fields, each allocated a predetermined number of bytes limited in size and comprising a region portion consuming one byte for storing a region index and a subregion portion consuming one byte for a most significant bit and one byte for a least significant bit,
wherein the sequential fields include:
(1) a first field comprising changed L2P region and subregion information identifying regions previously provided to the host device that are no longer valid but remain available to the storage system without loading from the memory array;
(2) a second field comprising to-be-loaded L2P region and subregion information identifying regions ready for host device loading but not yet transferred to the host device; and
(3) a third field comprising invalid L2P region and subregion information identifying regions that are no longer valid and require loading from the memory array.
14. The system of claim 13, wherein a size of subregions within the logical address ranges is 4K bytes, and wherein the changed L2P region information, the to-be-loaded L2P region information, and the invalid L2P region information are each 1 byte in size.
9. The method of claim 8, wherein a size of one or more of the changed L2P subregion, the to-be-loaded L2P subregion, or the invalid L2P subregion on the memory array is 4K bytes, and
wherein one or more of the changed L2P region, the to-be-loaded L2P region, or the invalid L2P region comprises multiple subregions.
15. The system of claim 14, wherein the changed L2P subregion information, the to-be-loaded L2P subregion information, and the invalid L2P subregion information are each 2 bytes in size.
16. The system of claim 13, wherein the changed L2P region information, the to-be-loaded L2P region information, and the invalid L2P region information are each 1 byte in size, and wherein associated subregion information comprises 2 bytes including one byte for a most significant bit and one byte for a least significant bit.
10. The method of claim 9, wherein the changed L2P region information, the to-be-loaded L2P region information, and the invalid L2P region information in the response information unit are each 1 byte in size, and
wherein the changed L2P subregion information, the to-be-loaded L2P subregion information, or the invalid L2P subregion information in the response information unit are each 2 bytes in size, including one byte for a most significant bit (MSB) and one byte for a least significant bit (LSB).
20. At least one non-transitory device-readable storage medium comprising instructions that, when executed by a memory controller of a memory system, cause the memory controller to perform operations comprising:
maintaining a relationship between a logical block address (LBA) and a physical address (PA) of data stored on a memory array of the storage system in a logical-to-physical (L2P) map, and providing L2P information to a host device, wherein each region of the L2P map corresponds to a respective logical address range;
determining L2P state changes in different L2P regions and subregions of the memory array based on changes in the L2P map at the storage system, wherein the L2P states of L2P regions and subregions include valid, changed, to-be-loaded, and invalid states;
notifying the host device that L2P information should be updated using an L2P update needed flag; and
providing, as a response to a host memory request, a response message comprising:
first L2P region and associated subregion information identifying regions previously provided to the host device that are no longer valid but remain available to the storage system without loading from the memory array;
second L2P region and associated subregion information identifying regions ready for host device loading but not yet transferred to the host device; and
third L2P region and associated subregion information identifying regions that are no longer valid and require loading from the memory array.
15. At least one non-transitory device-readable storage medium comprising instructions that, when executed by a memory controller of a storage system, cause the memory controller to perform operations comprising:
maintaining a relationship between a logical block address (LBA) and a physical address (PA) of data stored on a memory array of the storage system in a logical-to-physical (L2P) map and providing L2P information to a host device;
determining L2P state changes in different L2P regions and subregions of the memory array based on changes in the L2P map at the storage system, wherein the L2P states of L2P regions and subregions include valid, changed, to-be-loaded, and invalid states; and
providing, as a response to a host memory request from the host device including an invalid L2P region or subregion, a response information unit based on the determined L2P state changes, wherein the response information unit comprises sequential fields, each allocated a predetermined number of bytes limited in size and comprising a region portion consuming one byte for storing a region index and a subregion portion consuming one byte for a most significant bit and one byte for a least significant bit,
wherein the sequential fields include:
(1) a first field comprising changed L2P region and subregion information identifying regions previously provided to the host device that are no longer valid but remain available to the storage system without loading from the memory array;
(2) a second field comprising to-be-loaded L2P region and subregion information identifying regions ready for host device loading but not yet transferred to the host device; and
(3) a third field comprising invalid L2P region and subregion information identifying regions that are no longer valid and require loading from the memory array.
Regarding claim 4, U.S. Patent #12353325 discloses all limitations except for read buffer command comprising an operation code, a buffer ID, an L2P region, an L2P subregion, and an allocation length. Where U.S. Patent #12353325 discloses a read buffer command for requesting L2P information and the host receiving information including L2P region and subregion information (claims 1 and 7), King et al. (US 20030093721 A1) teaches a read buffer command comprising operation code, buffer ID, transfer lengths, and target logical unit number (para. 76-80, 38; table 6).
U.S. Patent #12353325 and King are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of U.S. Patent #12353325 and King, to modify the disclosures by U.S. Patent #12353325 to include disclosures by King since they both teach data storage memory access, wherein King is directed towards commands used for querying device status (para. 17-18). Therefore, it would be applying a known technique (read buffer command comprising operation code, buffer ID, transfer length, and target logical unit) to a known device (system configured to utilize read buffer command for receiving information concerning L2P region and subregion) ready for improvement to yield predictable results (system configured to utilize read buffer command comprising operation code, buffer ID, transfer length, and target L2P region and subregion, as doing so would provide for improved command processing by providing for the operation type, buffer, transfer length, and targets associated with the command). MPEP 2143
Regarding claims 11, 13, and 20, U.S. Patent #12353325 discloses all limitations except for where a controller is to notify host that L2P information should be updated using a flag. U.S. Patent #12353325 teaches a storage system providing L2P information to a host device, and also teaches, responsive to a host request, sending a response information including changed or invalid regions. Widder (US 20190004944 A1) teaches a memory system sending updates to part or all of address table on a host having invalid parts (alerting update is needed), where the memory system may utilize a data construct such as a bitmap indicating which parts of address table on a host is invalid in association with synchronizing the address table on host with the address table on the memory system (para. 16, 20-21, 49-52), where a bit of a bitmap may correspond to a flag.
U.S. Patent #12353325 and Widder are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of U.S. Patent #12353325 and Widder, to modify the disclosures by U.S. Patent #12353325 to include disclosures by Widder since they both teach data storage and memory access, wherein Widder is directed towards memory translation and addressing (para. 1-2, 14-16). Therefore, it would be applying a known technique (memory system configured to send updates to parts of host address table having invalid portions and a bitmap used for indicating invalid portions of host address table) to a known device (storage system providing mapping information to host device and, responsive to a host request, a response information comprising information including invalid or changed regions) ready for improvement to yield predictable results (storage system sending updates to parts of the host mapping information having invalid portions, and, responsive to a host request, sending response information including invalid or changed regions, where invalid portions of host mapping information may be tracked using a bitmap in order to provide for improved tracking of host mapping information status). MPEP 2143
The double patenting rejection above applies to claims 1-5, 7-11, 13-16, and 20.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Chen et al. (US 20100064095 A1) teaches ready data comprising data that has been received from host into a host interface and cached into cache memory.
Liao et al. (US 20190361803 A1) teaches determining whether state of a logical block is in a readiness state by determining whether the physical blocks mapped to the logical block is ready for data transfer.
Conclusion
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/E.Y.K./Examiner, Art Unit 2135
/YAIMA RIGOL/Primary Examiner, Art Unit 2135
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