NON-FINAL REJECTION
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 5, 6, 8, 9, 11, 12, 14, 15, and 18 of U.S. Patent No. 12,367,154 in view of Bolbenes et al. (US 2017/0344492).
Regarding claim 1, U.S. Patent No. 12,367,154 discloses:
An integrated circuit comprising:
a processor core comprising a processor pipeline (claim 1: a processor pipeline; claim 3: a processor core that includes the processor pipeline) and a register (claim 2: a control status register);
a translation lookaside buffer (TLB) configured to translate a guest virtual address (GVA) to a physical address (claim 1: a translation lookaside buffer configured to perform two-stage address translation to translate guest virtual addresses to physical addresses); and
a data store (claim 1: a data store)…
wherein the integrated circuit is configured to, responsive to a first address translation request for a first GVA resulting in a fault condition in the TLB (claim 1: responsive to the fault condition on a hit in the translation lookaside buffer for a first address translation request from the processor pipeline for a first guest virtual address):
initiate a hardware-based, single-stage page table walk using the first GVA to determine a corresponding first guest physical address (GPA) (claim 1: invoke a single-stage page table walk with the first guest virtual address to obtain the first guest physical address);
cause the TLB to signal a miss to the processor pipeline for the first address translation request (claim 5: cause the translation lookaside buffer to return a miss to the processor pipeline in response the first address translation request), thereby prompting a subsequent retry of the request (claim 6: in response to the miss, add the first address translation request to a queue of address translation requests to be retried in program order);
store the first GPA in the data store (claim 1: store the first guest physical address with the first guest virtual address in the data store); and…
U.S. Patent No. 12,367,154 does not appear to explicitly teach a data store “separate from entries of the TLB” and “upon a subsequent retried address translation request for the first GVA, communicate the first GPA from the data store to the register.” However, Bolbenes et al. disclose:
[a data store] separate from entries of the TLB (FIG. 4 minicache 36 separate from TLB 42);…upon a subsequent retried address translation request for the first GVA, communicate the first GPA from the data store to the register ([0032] When this translation is subsequently actioned, if it results in a permission fault, then fault handling by a hypervisor program will be triggered and this can result in the hypervisor program issuing an intermediate physical address lookup instruction (ATS1E1) in order to return the last intermediate physical address (such as writing this into an appropriate response register, e.g. PAR_EL2). As a consequence of the check permission circuitry 40 having stored the virtual address to last intermediate physical address mapping within the cache 36, this intermediate address lookup instruction (ATS1E1) will hit within the cache 36 using its virtual address and the cache 36 can rapidly write the correct intermediate physical address value into the response register PAR_EL2; [0033] Accordingly, if the response returned from a response interface 46 initiates a permission fault resulting in the hypervisor generating an intermediate address lookup instruction ATS1E1, then this may again be serviced from the cache 36 without waiting for a further page table walk to be performed).
U.S. Patent No. 12,367,154 and Bolbenes et al. are analogous art because U.S. Patent No. 12,367,154 and Bolbenes et al. disclose address translation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of U.S. Patent No. 12,367,154 and Bolbenes et al. before him/her, to modify the teachings of U.S. Patent No. 12,367,154 with the teachings of Bolbenes et al. because implementing a data store separate from the TLB would enable a response to an address translation instruction to be provided more rapidly (Bolbenes et al. [0024]).
Regarding claim 2, U.S. Patent No. 12,367,154 further discloses:
The integrated circuit of claim 1, wherein the processor pipeline is configured to, in response to the miss, add the first address translation request to a queue of address translation requests to be retried in program order (claim 6: in response to the miss, add the first address translation request to a queue of address translation requests to be retried in program order).
Regarding claim 3, U.S. Patent No. 12,367,154 further discloses:
The integrated circuit of claim 1, wherein the register is a control status register (claim 2: a control status register), and the integrated circuit further comprises memory storing hypervisor software configured to read the control status register in response to receiving an exception from the processor core (claim 4: a memory storing hypervisor software that is configured to read the control status register in response to receiving an exception from a processor core including the processor pipeline).
Regarding claim 4, U.S. Patent No. 12,367,154 further discloses:
The integrated circuit of claim 1, wherein the data store is further configured to store a valid flag, and wherein the integrated circuit is further configured to update the valid flag to indicate the first GPA is ready when it is stored in the data store, and update the valid flag to indicate the first GPA is not ready responsive to it being transferred to the register (claim 7: in which the data store is configured to store a valid flag, and in which the fault handling circuitry is configured to: update the valid flag to indicate the first guest physical address is ready when storing the first guest physical address in the data store; and update the valid flag to indicate the first guest physical address is not ready responsive to transferring the first guest physical address to a control status register).
Regarding claim 5, U.S. Patent No. 12,367,154 further discloses:
The integrated circuit of claim 1, wherein the data store is further configured to store a guest fault flag indicating whether the fault condition corresponding to the first GPA occurred during a first stage or a second stage of a two-stage address translation (claim 1: store a guest fault flag indicating whether a fault condition corresponding to a first guest physical address occurred during a first stage or a second stage of the two-stage address translation).
Regarding claim 6, U.S. Patent No. 12,367,154 further discloses:
The integrated circuit of claim 1, further comprising exception handling circuitry configured to update the register, wherein the first GPA is communicated to the register via a signal path through the translation lookaside buffer and the exception handling circuitry (claim 3: an exception handling circuitry configured to update a processor core that includes the processor pipeline in response to exceptions occurring in the processor core, in which the first guest physical address is transferred to the control status register via a signal path through the translation lookaside buffer and the exception handling circuitry).
Regarding claim 7, U.S. Patent No. 12,367,154 further discloses:
The integrated circuit of claim 1, wherein the integrated circuit is further configured to store the first GVA in the data store as a tag associated with the first GPA (claim 1: a tag that includes a guest virtual address and data that includes a physical address; a data store configured to: hold a guest physical address and the guest virtual address).
Claims 8-20 recite limitations substantially similar to the limitations of claims 1-7. Therefore, claims 8-20 are rejected under the same reasoning as claim 1-7.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7-9, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Bolbenes et al. and Bryant (US 2021/0406194).
Regarding claim 1, Bolbenes et al. disclose:
An integrated circuit comprising:
…and a register ([0032] response register PAR_EL2;
a translation lookaside buffer (TLB) (FIG. 4 a translation lookaside buffer 42) configured to translate a guest virtual address (GVA) to a physical address ([0032] a normal translation lookup received at a translation lookaside buffer 42; [0021] translation of a virtual address VA of a memory access generated by a guest operating system to a physical address PA of a memory system); and
a data store separate from entries of the TLB (FIG. 4 minicache 36 separate from TLB 42);
wherein the integrated circuit is configured to, responsive to a first address translation request for a first GVA (FIG. 4 normal translation; [0032] a normal translation lookup received at a translation lookaside buffer 42 of the memory management unit 34) resulting in a fault condition in the TLB ([0033] In the case of a hit within the translation lookaside buffer 42 in response to a received normal translation request, then this results in the return of a translation response by the response interface 46 as before. The hit response is also checked by check permission circuitry 38. If the check performed by the check permission circuitry 38 indicates at the second stage of address translation permission data is more restrictive than the first stage of address translation and permission data (i.e. a fault)):
initiate a hardware-based, single-stage page table walk using the first GVA to determine a corresponding first guest physical address (GPA) ([0033] then a speculative page table walk operation is initiated and performed by the page table walking circuitry 44 in order to obtain the last intermediate physical address associated with that translation);
cause the TLB to signal a miss to the processor pipeline for the first address translation request, thereby prompting a subsequent retry of the request (FIG. 4 TLB returns a miss; [0032] In the case of a normal translation lookup received at a translation lookaside buffer 42 of the memory management unit 34, when a translation lookaside buffer miss occurs, a page table walk is performed by a page table walking circuit 44);
store the first GPA in the data store ([0033] This last intermediate physical address IPA is then stored together with the virtual address to which it corresponds into the cache 36); and
upon a subsequent retried address translation request for the first GVA, communicate the first GPA from the data store to the register ([0032] When this translation is subsequently actioned, if it results in a permission fault, then fault handling by a hypervisor program will be triggered and this can result in the hypervisor program issuing an intermediate physical address lookup instruction (ATS1E1) in order to return the last intermediate physical address (such as writing this into an appropriate response register, e.g. PAR_EL2). As a consequence of the check permission circuitry 40 having stored the virtual address to last intermediate physical address mapping within the cache 36, this intermediate address lookup instruction (ATS1E1) will hit within the cache 36 using its virtual address and the cache 36 can rapidly write the correct intermediate physical address value into the response register PAR_EL2; [0033] Accordingly, if the response returned from a response interface 46 initiates a permission fault resulting in the hypervisor generating an intermediate address lookup instruction ATS1E1, then this may again be serviced from the cache 36 without waiting for a further page table walk to be performed).
Bolbenes et al. do not appear to explicitly teach “a processor core comprising a pipe.” However, Bryant discloses:
a processor core ([0024] A (e.g., hardware) processor (e.g., having one or more cores) may execute instructions to operate on data, for example, to perform arithmetic, logic, or other functions) comprising a processor pipe ([0033] a page miss handler circuit having a plurality of pipeline walk stages (e.g., and corresponding states in a state machine) that allow for a plurality of contemporaneous page walk stages to be performed)
Bolbenes et al. and Bryant are analogous art because Bolbenes et al. and Bryant teach address translation.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Bolbenes et al. and Bryant before him/her, to modify the teachings of Bolbenes et al., which teaches handling fault conditions when performing address translations with Bryant’s teachings of a processor core because such modifications would have amounted to little more than combining “familiar elements according to known methods” and would have been obvious because it would have done “no more than yield predictable results.” (MPEP 2143 I.A.) Processor pipelines are well-known elements of virtual memory address translations. Implementing a processor pipeline would provide the means to fetch and execute instructions.
Regarding claim 2, Bryant further discloses:
The integrated circuit of claim 1, wherein the processor pipeline is configured to, in response to the miss, add the first address translation request to a queue of address translation requests to be retried in program order ([0033] Embodiments herein utilize a page miss handler circuit having a plurality of pipeline walk stages (e.g., and corresponding states in a state machine) that allow for a plurality of contemporaneous page walk stages to be performed. For example, page miss handler circuit 104 in FIG. 1 may include a page miss handler (PMH) queue 140 and/or page miss handler (PMH) pipeline 142. Page miss handler (PMH) queue 140 may include an entry for each miss…In certain embodiments, each stage of a plurality of page walks may be handled out of order, for example, with a stage of a first (based on program order or order of receipt by the queue 140) page walk being performed concurrently with a different stage of a (earlier or later) second (based on program order or order of receipt by the queue 140) page walk being performed).
Regarding claim 7, Bolbenes et al. further disclose:
The integrated circuit of claim 1, wherein the integrated circuit is further configured to store the first GVA in the data store as a tag associated with the first GPA ([0021] FIG. 1 schematically illustrates translation of a virtual address VA of a memory access generated by a guest operating system (i.e. guest virtual address) to a physical address PA of a memory system…In particular, when a memory access request requires translation via a page table walk, such as, as a result of a miss within a translation lookaside buffer; The teachings of paragraph [0021] imply that when a translation of a guest virtual address is needed, the TLB is searched to find the physical address. In other words, the guest virtual address is used to look up the physical address in the TLB. One of ordinary skill in the art would understand that the guest virtual address is the tag that corresponds to, and is used to find, the data that is the physical address when performing translation lookups in the TLB).
Claims 8-9 and 14-16 recite limitations substantially similar to the limitations of claims 1, 2, and 7. Therefore, claims 8-9 and 14-16 are rejected under the same rationale as claims 1, 2 and 7.
Allowable Subject Matter
Claims 3-6, 10-13, and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the examiner’s statement of reasons for allowance:
While one or more reasons are offered below citing reasons that the claims are allowable over the prior art, it is each claim taken as a whole, including interrelationships and interconnections between various claimed elements, which are allowable over the prior art of record and not any individual limitation of a claim. The prior art of Bolbenes et al. and Bryant, when taken alone or in combination with each other, fail to anticipate and/or make obvious to one of ordinary skill in the art the claimed invention prior to the effective filing date.
Regarding claim 3, the prior art, alone or in combination, does not disclose the following limitations, as claimed, in combination with the other claimed limitations:
“The integrated circuit of claim 1, wherein the register is a control status register, and the integrated circuit further comprises memory storing hypervisor software configured to read the control status register in response to receiving an exception from the processor core.”
Regarding claim 4, the prior art, alone or in combination, does not disclose the following limitations, as claimed, in combination with the other claimed limitations:
“The integrated circuit of claim 1, wherein the data store is further configured to store a valid flag, and wherein the integrated circuit is further configured to update the valid flag to indicate the first GPA is ready when it is stored in the data store, and update the valid flag to indicate the first GPA is not ready responsive to it being transferred to the register.”
Regarding claim 5, the prior art, alone or in combination, does not disclose the following limitations, as claimed, in combination with the other claimed limitations:
“The integrated circuit of claim 1, wherein the data store is further configured to store a guest fault flag indicating whether the fault condition corresponding to the first GPA occurred during a first stage or a second stage of a two-stage address translation.”
Regarding claim 6, the prior art, alone or in combination, does not disclose the following limitations, as claimed, in combination with the other claimed limitations:
“The integrated circuit of claim 1, further comprising exception handling circuitry configured to update the register, wherein the first GPA is communicated to the register via a signal path through the translation lookaside buffer and the exception handling circuitry.”
Claims 10-13 and 17-20 recite limitations substantially similar to the limitations of claim 3-6. Therefore, claims 10-13 and 17-20 would be allowable under the same rationale as claim 3-6.
Conclusion
The prior art made of record and not relied upon, Mukherjee et al. (US 11,176,055), is considered pertinent to applicant's disclosure because it discloses address translation.
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/TRACY A WARREN/Primary Examiner, Art Unit 2137
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