DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the application filed 07 July 2025.
Claims 1-20 are pending and have been presented for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4 and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over HUNG (U.S. Patent Application Publication #2023/0317122) in view of FUJIWARA (U.S. Patent Application Publication #2023/0068645).
1. HUNG discloses A memory device comprising: an array of memory cells (see [0032]: NAND flash array); and a peripheral circuit coupled to the array of memory cells (see [0047]: page buffer/CIM unit) and comprising: page buffers (see [0037]: page buffer) configured to store first data transmitted from a data interface of the memory device (see [0067]: M bits loaded into the page buffer from another source), sense second data from the array of memory cells (see [0067]: M bits loaded into the page buffer in a read operation from the memory array) and generate third data based on the first data and second data (see FUJIWARA below); at least one process unit coupled to the page buffers via a data-path bus of the peripheral circuit (see [0037]: CIM circuit; [0041]: CIM circuit can perform operations on data in the page buffer), and configured to perform calculation based on the third data (see FUJIWARA below); and a control logic (see [0043]-[0045]: command decoder and control logic) configured to program the second data into the array of memory cells (see [0048]: generate an output and store the result).
FUJIWARA discloses the following limitations that are not taught by HUNG: generate third data based on the first data and second data (see [0038]-[0039]: combine intermediate data into output data; [0060]: generate intermediate data from the data read from the memory and the weigh data in the buffer), and configured to perform calculation based on the third data (see [0039]: the output from one macro is supplied as input to another macro, the data being fed into each macro is intermediate data) Generating intermediate data from first and second data allows for implementation of a neural network using memory macros (see [0051]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify HUNG to generate third data, as disclosed by FUJIWARA. One of ordinary skill in the art would have been motivated to make such a modification to implement a neural network, as taught by FUJIWARA. HUNG and FUJIWARA are analogous/in the same field of endeavor as both references are directed to performing computations on data in memory.
2. The memory device of claim 1, wherein the first data comprises at least one row; and the control logic is further configured to control the page buffers to receive each row of the first data based on a first data pattern (see [0053]: page buffer includes multiple rows, which anticipates at least one row; [0061], [0069]: data is stored in the page buffer for an operation, the claims do not define the pattern, so any patterns of 1’s and 0’s would anticipate the limitation).
3. The memory device of claim 2, wherein the page buffer is further configured to store the first data based on a first data pattern, store the second data based on a second data pattern, and store the third data based on a third data pattern (see [0053]: page buffer includes multiple rows, which anticipates at least one row; [0061], [0069]: data is stored in the page buffer for an operation, the claims do not define the pattern, so any patterns of 1’s and 0’s would anticipate the limitation).
4. The memory device of claim 3, wherein the page buffer is further configured to perform an OR operation or and AND operation on the first data having the first data pattern and the second data having the second data pattern to generate the third data having the third data pattern (see FUJIWARA [0075]: logic operations are performed using an AND gate or a NOR gate).
16. The memory device of claim 1, wherein the memory device comprises a NAND flash memory (see [0032]: NAND flash array).
17. HUNG discloses A method for data calculation with a memory device comprising an array of memory cells (see [0032]: NAND flash array) and a peripheral circuit coupled to the memory cells (see [0047]: page buffer/CIM unit), comprising: obtaining, by page buffers (see [0037]: page buffer) of the peripheral circuit, first data from a data interface of the memory device (see [0067]: M bits loaded into the page buffer from another source); sensing, by the page buffers of the peripheral circuit, second data from the array of memory cells (see [0067]: M bits loaded into the page buffer in a read operation from the memory array); generating, by the page buffers of the peripheral circuit, third data based on the first data and the second data (see FUJIWARA below); and performing calculation, by at least one process unit of the peripheral circuit, based on third data (see FUJIWARA below).
FUJIWARA discloses the following limitations that are not taught by HUNG: generate third data based on the first data and second data (see [0038]-[0039]: combine intermediate data into output data; [0060]: generate intermediate data from the data read from the memory and the weigh data in the buffer), and configured to perform calculation based on the third data (see [0039]: the output from one macro is supplied as input to another macro, the data being fed into each macro is intermediate data) Generating intermediate data from first and second data allows for implementation of a neural network using memory macros (see [0051]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify HUNG to generate third data, as disclosed by FUJIWARA. One of ordinary skill in the art would have been motivated to make such a modification to implement a neural network, as taught by FUJIWARA. HUNG and FUJIWARA are analogous/in the same field of endeavor as both references are directed to performing computations on data in memory.
18. The method of claim 17, further comprising: storing the first data, by the page buffers of the peripheral circuit, based on a first data pattern; storing the second data, by the page buffers of the peripheral circuit, based on a second data pattern; and storing the third data, by the page buffers of the peripheral circuit, based on a third data pattern (see [0053]: page buffer includes multiple rows, which anticipates at least one row; [0061], [0069]: data is stored in the page buffer for an operation, the claims do not define the pattern, so any patterns of 1’s and 0’s would anticipate the limitation).
19. The method of claim 17, further comprising: programming the second data into the array of memory cells (see HUNG [0048]: generate an output and store the result).
20. HUNG discloses A system, comprising: a memory device comprising: an array of memory cells (see [0032]: NAND flash array); and a peripheral circuit coupled to the memory cells (see [0047]: page buffer/CIM unit) and comprising: page buffers (see [0037]: page buffer) configured to store first data transmitted from a data interface of the memory device (see [0067]: M bits loaded into the page buffer from another source), sense second data from the array of memory cells (see [0067]: M bits loaded into the page buffer in a read operation from the memory array) and generate third data based on the first data and the second data (see FUJIWARA below); and at least one process unit coupled to the page buffers via a data-path bus of the peripheral circuit (see [0037]: CIM circuit; [0041]: CIM circuit can perform operations on data in the page buffer), and configured to perform calculation based on the third data (see FUJIWARA below); and a controller coupled with the memory device (see [0043]-[0045]: command decoder and control logic) and configured to transmit the first data into the memory device and receive a result of the calculation from the memory device (see [0048]: generate an output and store the result).
FUJIWARA discloses the following limitations that are not taught by HUNG: generate third data based on the first data and second data (see [0038]-[0039]: combine intermediate data into output data; [0060]: generate intermediate data from the data read from the memory and the weigh data in the buffer), and configured to perform calculation based on the third data (see [0039]: the output from one macro is supplied as input to another macro, the data being fed into each macro is intermediate data) Generating intermediate data from first and second data allows for implementation of a neural network using memory macros (see [0051]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify HUNG to generate third data, as disclosed by FUJIWARA. One of ordinary skill in the art would have been motivated to make such a modification to implement a neural network, as taught by FUJIWARA. HUNG and FUJIWARA are analogous/in the same field of endeavor as both references are directed to performing computations on data in memory.
Allowable Subject Matter
Claims 5-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The state of the art discloses processing-in-memory architectures that include page buffers to process input data along with data stored in a memory array.
TANAKA (2024/0257842) discloses a CIM system that processes input data using weights stored in a memory array, see pages 8-9.
FOUDA (2024/0143541) discloses a CIM hardware module where the memory array stores a plurality of weights. The weights can be stored as a matrix. The CIM circuit performs a matrix multiplication operation on input data using the stored weight data, see pages 4-6.
MATHURIYA (11,836,102) discloses computing weight values and storing those weight values in the memory array, see column 8. SKADRON (2023/0343373) discloses a processing in memory system for performing matrix multiplication. Data is stored in a matrix in the memory for processing, see [0053]-[0066].
PLANTS (2018/0232273) discloses ECC for data stored in a page buffer, see claim 1.
The state of the art fails to anticipate or render obvious the specific data pattern where “… the first data pattern comprises N first data segments with equal data length, where N is a positive integer and N≥2; a sequence of the N first data segments of the first data pattern is the same as a sequence of the first data; and every two adjacent first data segments of the first data pattern are separated by M first blank segments, where M is a positive integer and M≥2.” Applicant provides further clarification on the data patterns used and the storage of data in the memory based on the data pattern in paragraphs [0108]-[0110]. While the state of the art generally discloses storing data in a memory and data in a page buffer to be used in a CIM system, the prior art fails to show a combination which would provide for the specific patterns of data stored claimed by applicant.
Claims 6-15 depend from claim 5 and by nature of their dependency include the allowable subject matter of claim 5.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD J DUDEK JR whose telephone number is (571)270-1030. The examiner can normally be reached Monday - Friday, 8:00A-4:00P.
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/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2132
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