DETAILED ACTION
Claims 1-15 are pending.
The office acknowledges the following papers:
Patent application filed on 7/8/2025.
Allowable Subject Matter
Claims 1-10 and 15 would be allowable if rewritten or amended to overcome the double patenting rejections, set forth in this Office action.
Claims 12-14 would be allowable if rewritten to overcome the double patenting rejections, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Venkatasubramanian disclosed new memory requests determining if a L1 cache hit or miss occurs. After detecting the hit or miss, the entry is added to the scoreboard to track outstanding requests. Upon detecting a miss, a request is sent to the L2 cache. The scoreboard allows for returning data to the CPU in a different order than requests were originally sent to the L1 cache. As noted below, the BRI of independent claims 1 and 15 has invoked 35 U.S.C. 112(f). Venkatasubramanian failed to additionally teach the added structure of the claimed terms invoking 35 U.S.C. 112(f).
Priority
The effective filing date for the subject matter defined in the pending claims in this application is 6/14/2016.
Drawings
The Examiner contends that the drawings submitted on 7/8/2025 are acceptable for examination proceedings.
Specification
The disclosure is objected to because of the following informalities:
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. The Applicant’s cooperation is requested in correcting any errors of which the Applicant may become aware.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“a cache management unit arranged, in response to determining that a memory request generated in the processor refers to data that is not stored in the on-chip cache, to generate a memory request on a further level of a memory hierarchy” in claims 1 and 15, which is construed as the structure detailed at published application paragraphs 47-49 and figure 4 element 202 of the drawings.
“a re-order buffer module arranged to control an order in which memory requests generated in the processor are executed within the on-chip cache such that request entries may be picked out for execution in any order, and comprising a data structure arranged to store pending memory requests, and wherein data is received from the further level of the memory hierarchy in an order that is different from an order in which the corresponding memory requests are generated in the processor” in claims 1 and 15, which is construed as the structure detailed at published application paragraphs 50-56 and figure 5 element 502 of the drawings.
“an execution selection module arranged to select a sequence of pending memory requests from the data structure for execution such that pending requests relating to an identical cache line are executed in age order and pending requests relating to different cache lines are executed in an order dependent upon when data relating to the different cache lines is received via the second input” in claim 2, which is construed as the structure detailed at published application paragraphs 56-62 and figure 5 element 514 of the drawings.
“a cache line status module arranged to track a status of each cache line in the cache and in response to a cache miss on a particular cache line, to block execution of any subsequent memory requests generated in another on-chip cache and relating to the particular cache line until the corresponding data is received from the external memory” in claim 6, which is construed as the structure detailed at published application paragraph 64 and figure 4 element 412 of the drawings.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Applicants can file an eTerminal Disclaimer (eTD) in utility applications filed under 35 U.S.C. 111(a) or in compliance with 35 U.S.C. 371, and design applications. Filing an eTD via EFS-Web is highly recommended due to an extensive backlog for processing paper TDs. However, applicants may still file a TD for manual review.
Claims 1-15 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-5 and 9-17 of U.S. Patent No. 12,353,883. Although the conflicting claims are not identical, they are not patentably distinct from each other because U.S. Patent No. 12,353,883 contains every element of claims 1-15 of the instant application and thus anticipates the claims of the instant application. Claims of the instant application therefore are not patently distinct from earlier patent claims and as such are unpatentable over obvious-type double patenting. A later application claim is not patently distinct from an earlier claim if the later claim is anticipated by the earlier claim.
Instant Application
U.S. Patent No. 12,353,883
1. An instruction scheduler for use in an on-chip cache of a processor formed on a chip with the on-chip cache, the instruction scheduler comprising:
1. An instruction scheduler for use in an on-chip cache of a processor formed on a chip with the on-chip cache, the instruction scheduler comprising:
a cache management unit arranged, in response to determining that a memory request generated in the processor refers to data that is not stored in the on-chip cache, to generate a memory request on a further level of a memory hierarchy; and
a cache management unit arranged, in response to determining that a memory request generated in the processor refers to data that is not stored in the on-chip cache, to generate a memory request on a further level of a memory hierarchy; and
a re-order buffer module arranged to control an order in which memory requests generated in the processor are executed within the on-chip cache such that request entries may be picked out for execution in any order.
a re-order buffer module arranged to control an order in which memory requests generated in the processor are executed within the on-chip cache such that request entries may be picked out for execution in any order, and comprising a data structure arranged to store pending memory requests, and wherein data is received from the further level of the memory hierarchy in an order that is different from an order in which the corresponding memory requests are generated in the processor.
Claims 11 and 15 are similar to claim 1 and is rejected for the same reasons. Dependent claims 2-10 and 12-14 are read upon by the dependent claims 2-5 and 9-17 of U.S. Patent No. 12,353,883.
Claims 1-15 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-5 and 9-18 of U.S. Patent No. 10,929,138. Although the conflicting claims are not identical, they are not patentably distinct from each other because U.S. Patent No. 10,929,138 contains every element of claims 1-15 of the instant application and thus anticipates the claims of the instant application. Claims of the instant application therefore are not patently distinct from earlier patent claims and as such are unpatentable over obvious-type double patenting. A later application claim is not patently distinct from an earlier claim if the later claim is anticipated by the earlier claim.
Instant Application
U.S. Patent No. 10,929,138
1. An instruction scheduler for use in an on-chip cache of a processor formed on a chip with the on-chip cache, the instruction scheduler comprising:
1. An on-chip cache which is part of a memory hierarchy of a processor formed on a chip with the on-chip cache, the on-chip cache comprising an instruction scheduler, wherein the instruction scheduler comprises:
a first input arranged to receive memory requests generated in the processor;
a cache management unit arranged, in response to determining that a memory request generated in the processor refers to data that is not stored in the on-chip cache, to generate a memory request on a further level of a memory hierarchy; and
a cache management unit arranged, in response to determining that a received memory request refers to data that is not stored in the on-chip cache, to generate a memory request on a further level of the memory hierarchy;
a second input arranged to receive data returned from the further level in the memory hierarchy in response to memory requests generated in the cache management unit; and
a re-order buffer module arranged to control an order in which memory requests generated in the processor are executed within the on-chip cache such that request entries may be picked out for execution in any order.
a re-order buffer module arranged to control an order in which received memory requests are executed within the on-chip cache such that received request entries may be picked out for execution in any order, and comprising a data structure arranged to store pending memory requests, and wherein data is received via the second input in an order that is different from an order in which the corresponding memory requests are received via the first input.
Claims 11 and 15 are similar to claim 1 and is rejected for the same reasons. Dependent claims 2-10 and 12-14 are read upon by the dependent claims 2-5 and 9-17 of U.S. Patent No. 10,929,138.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 11 is rejected under 35 U.S.C. 102(a)(1 & 2) as being anticipated by Venkatasubramanian et al. (U.S. 2016/0019151).
As per claim 11:
Venkatasubramanian disclosed a method of operating an instruction scheduler for use in an on-chip cache of a processor formed on a chip with the on-chip cache, the method comprising:
determining if a memory request generated in the processor refers to data that is not stored in the on-chip cache (Venkatasubramanian: Figure 15 element 1507, paragraph 68)(The tag compare 1507 determines whether the request is a cache hit or miss.);
in response to determining that the memory request refers to data that is not stored in the on-chip cache, generating a memory request on a further level of a memory hierarchy (Venkatasubramanian: Figure 15, paragraph 69)(Upon a miss to the L1 cache, a request is sent to the L2 cache.); and
picking out memory requests generated in the processor for execution within the on-chip cache in any one of a plurality of orders (Venkatasubramanian: Figure 15 element 1506, paragraphs 70, 72, and 76)(The Scoreboard controls the order of memory requests and allows for out-of-order transaction for returned L2 cache data.).
Conclusion
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Minkin et al. (U.S. 6,629,188), taught prefetching data for a texture cache.
Wang et al. (U.S. 2011/0145551), taught reordering memory accesses.
Pohlack et al. (U.S. 2012/0159084), taught reordering memory accesses.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183
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