DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 08, 2025 and May 21, 2026 is/are in compliance with the provisional of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 1 is objected to because of the following informalities: in the 11th line of the claim there appears to be a missing word. “low-level operating” should be “low-level operating system” Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-18 and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “wherein, in response to the first application being interrupted, the first application transitions from the active state to a standby state, the execution data of the main task of the first application is loaded into the first portion, and the low-level operating prevents unloading of the execution data of the main task of the first application” and claim 10 recites “loading the execution data of the main task of the first application into the first portion in response to the interruption; preventing the unloading of the execution data of the main task of the first application from the first portion in response to the interruption”.
The specification at paragraphs [0014-0018], [0058], [0066-0069], and [0114] discusses the interrupt of an application, but is mute in regards to loading data into the volatile memory and/or preventing data from unloading from the volatile memory. The specification instead talks about transferring data to the non-volatile memory.
Therefore the specification as originally filed does not provide support for “wherein, in response to the first application being interrupted, the first application transitions from the active state to a standby state, the execution data of the main task of the first application is loaded into the first portion, and the low-level operating prevents unloading of the execution data of the main task of the first application” or “loading the execution data of the main task of the first application into the first portion in response to the interruption; preventing the unloading of the execution data of the main task of the first application from the first portion in response to the interruption”.
Claims 2-9 and 11-18 depends on claims 1 and 10 and inherits this deficiency.
Claim 20 recites “detect whether an application is a resident application based on a request sent by the application at first loading, deny installation of an application as a resident application when a predetermined portion of the volatile memory is already reserved for resident applications”.
The specification is mute in the detection of an application to be a resident application based on a request by the application at first loading. The specification recites at paragraph [0095] “The management, by the low-level operating system, of the allocation of a dedicated portion of the volatile memory to a given application is configured based on a request sent by this given application at first loading (or in its mapping definition or its memory image)”, which only discloses the defining of the allocation and not if an application is a resident application. Furthermore the specification at least paragraph [0108] describes resident application as frequent-use application. How is the request knowing that the application is a frequent-use application on the first load? The specification is mute in regards to the indication that the application is frequently-used by a request on first load.
Therefore the specification as originally filed does not provide support for “detect whether an application is a resident application based on a request sent by the application at first loading, deny installation of an application as a resident application when a predetermined portion of the volatile memory is already reserved for resident applications”.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “low-level operating system” in claims 1, 10, and 19 is a relative term which renders the claim indefinite. The term “low-level operating system” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. What would be considered a low-level operating system? The kernel, device driver, firmware, bootloader, etc.?
The term “high-level operating system” in claims 1, 10, and 19 is a relative term which renders the claim indefinite. The term “low-level operating system” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. What would be considered a high-level operating system? The cloud OS, distributed OS, virtual machines, etc.?
Claims 2-9, 11-18, and 20 depends on claims 1, 11, and 19, and there for inherits these deficiencies.
Claim 20 recites “detect whether an application is a resident application based on a request sent by the application at first loading, deny installation of an application as a resident application when a predetermined portion of the volatile memory is already reserved for resident applications”. It is unclear how the application at first load is able to send a request to identify that the application is a resident application when it has not even been started? For examination purposes examiner is interpreting the limitation to be “detect whether an application is a resident application
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 3, 5-12, and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over He et al. (US 2018/0219777) (hereinafter He) (published August 02, 2018) in view of Mesropian et al. (US 2019/0303305) (hereinafter Mesropian) (published October 03, 2019), Couvee et al. (US 2013/0111152) (hereinafter Couvee) (published May 02, 2013), and Yu et al. (US 2013/0060985) (hereinafter Yu) (published March 07, 2013).
Regarding Claim 1, He discloses an embedded electronic system comprising: a volatile memory; and
“Network device 100 may include one or more processors 102. Processors 102 may include single or multicore processors. System memory 104 may provide memory resources for processors 102. System memory 104 is typically a form of random access memory (RAM) (e.g., dynamic random access memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM))” (He [0032])
a processor configured to execute a low-level operating system to manage allocation of areas of the volatile memory to a plurality of high-level operating systems, each high-level operating system executing one or more applications,
“As shown in the example depicted in FIG. 1, a host operating system 110 may be loaded in system memory 104 and executed by one or more processors 102. Host operating system 110 may be loaded, for example, when network device 100 is powered on. In certain implementations, host operating system 110 may also function as a hypervisor and facilitate management of virtual machines and other programs that are executed by network device 100. Managing virtual machines may include partitioning resources of network device 100, including processor and memory resources, between the various programs. A hypervisor is a program that enables the creation and management of virtual machine environments including the partitioning and management of processor, memory, and other hardware resources of network device 100 between the virtual machine environments” (He [0033] the low-level operating system is the hypervisor and the high level operating system is the virtual machine/host operating system)
“The operating system and applications executing within the guest virtual machine 320 generally use virtual addresses. A virtual machine is “virtual” in the sense that, from the perspective of the operating system and applications running within the virtual machine, the virtual machine appears indistinguishable from a physical machine” (He [0069])
But does not explicitly state wherein a first portion of the volatile memory is reserved for a storage of the execution data of a main task of the first application and a second portion of the volatile memory is reserved for a storage of execution data of a task of a second application, wherein, in response to the first application being interrupted, the first application transitions from the active state to a standby state, the execution data of the main task of the first application is loaded into the first portion, and the low-level operating prevents unloading of the execution data of the main task of the first application, and wherein, in response to the second application requiring storage space in the volatile memory greater than an available portion of the volatile memory, the low-level operating system denies execution of the second application, the available portion being equal to the total area of the volatile memory excluding the first portion.
Mesropian discloses wherein a first portion of the volatile memory is reserved for a storage of the execution data of a main task of the first application and a second portion of the volatile memory is reserved for a storage of execution data of a task of a second application,
“Hypervisor 104 may reserve the portion of secure memory for application 108 based on an availability of secure memory. For example, in FIG. 4B, a reserved portion 444 may have be previously reserved, for instance for another application, when hypervisor 104 receives the request from application 108. Hypervisor 104 may be limited by a global limit, such as the size of secure memory 442, from reserving any amount of secure memory. In addition, hypervisor 104 may not reserve portions of secure memory already reserved for another application. Thus, in FIG. 4C, hypervisor 104 may reserve a reserved portion 446 for application 108” (Mesropian [0060] one of the reserved portions 444 and 446 in secure memory 142 of volatile memory 140 would be for the first application and the other portion for the second application)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the reserving of memory in Mesropian with the system in He. The motivation for doing so would be improve the security of the memory so that there is no cross contamination between applications.
Couvee and Mesropian discloses wherein, in response to the first application being interrupted, the first application transitions from the active state to a standby state, the execution data of the main task of the first application is loaded into the first portion, and the low-level operating prevents unloading of the execution data of the main task of the first application, and
“A first step (step 700) is directed to detecting an interruption. If an interruption is detected, a following step (step 705) consists of a test to determine whether the interruption is directed to the suspension of the execution of a main application or not” (Couvee [0079])
“If the interruption is directed to the suspension of the execution of a main application, the context of the execution of that application is stored (step 710). As indicated previously, this step makes it possible in particular to store memory references in course of the main application” (Couvee [0080])
“The accessed data are then stored in an upper part of the memory according to predetermined parameters (step 810)” (Couvee [0089])
“In certain implementations, hypervisor 104 may verify every I/O request to reserved portion 446 to ensure that only authenticated code 110 accesses reserved portion 446, and to prevent any other application or portions of code of application 108 from accessing reserved portion 446” (Mesropian [0068] data loaded to the reserved portions are prevent access/unloading by other applications)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the interrupting, suspension, and loading of data described in Couvee with the system in the combination of He and Mesropian. The motivation for doing so would be improve the resuming of the first application as described by Couvee. “The invention is generally directed to a mechanism for anticipated loading of cache memory to load data linked to the execution of a first application, during the execution of a second application executed further to an interruption of execution of the first application, in order to enable optimum resumption of execution of the first application” (Couvee [0042])
Mesropian and Yu discloses wherein, in response to the second application requiring storage space in the volatile memory greater than an available portion of the volatile memory, the low-level operating system denies execution of the second application, the available portion being equal to the total area of the volatile memory excluding the first portion.
“Thus, in FIG. 4C, hypervisor 104 may reserve a reserved portion 446 for application 108. Reserved portion 446 may not exceed the global limit, and further does not overlap reserved portion 444” (Mesropian [0060] the required storage would be greater than the global limit/available portion)
“Accordingly, when a remaining capacity of the main memory is insufficient, the newly added task may be denied or the previous task may be finished compulsorily. It may be difficult to realize stable multi-tasking in mobile devices” (Yu [0113])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the denying of execution described in Yu with the system in the combination of He, Mesropian, and Couvee. The motivation for doing so would be to keep the system running as execution of the new task would over provision/allocation of memory which would cause problems to other parts of the system when their memory is taken away.
Regarding Claim 3, Mesropian further discloses wherein the non-volatile memory is external to the embedded electronic system, and
“communication interface 522 may also represent a host adapter configured to facilitate communication between computing system 510 and one or more additional network or storage devices via an external bus or communications channel. Examples of host adapters include, without limitation, Small Computer System Interface (SCSI) host adapters, Universal Serial Bus (USB) host adapters, Institute of Electrical and Electronics Engineers (IEEE) 1394 host adapters, Advanced Technology Attachment (ATA), Parallel ATA (PATA), Serial ATA (SATA), and External SATA (eSATA) host adapters, Fibre Channel interface adapters, Ethernet adapters, or the like. Communication interface 522 may also allow computing system 510 to engage in distributed or remote computing” (Mesropian [0091])
wherein the execution data of the main task of the first application remains in the first portion in response to the execution data of the task of the second application being transferred to the second portion of the volatile memory for execution.
“Hypervisor 104 may reserve the portion of secure memory for application 108 based on an availability of secure memory. For example, in FIG. 4B, a reserved portion 444 may have be previously reserved, for instance for another application, when hypervisor 104 receives the request from application 108. Hypervisor 104 may be limited by a global limit, such as the size of secure memory 442, from reserving any amount of secure memory. In addition, hypervisor 104 may not reserve portions of secure memory already reserved for another application. Thus, in FIG. 4C, hypervisor 104 may reserve a reserved portion 446 for application 108. Reserved portion 446 may not exceed the global limit, and further does not overlap reserved portion 444” (Mesropian [0060] portion 446 is reserved for execution data of second application and would not impact execution data stored in the portion 444 for first application)
Regarding Claim 5, Mesropian further discloses wherein the system is configured to allocate an area of the volatile memory for an execution of a main task of an application.
“Hypervisor 104 may reserve the portion of secure memory for application 108 based on an availability of secure memory. For example, in FIG. 4B, a reserved portion 444 may have be previously reserved, for instance for another application, when hypervisor 104 receives the request from application 108. Hypervisor 104 may be limited by a global limit, such as the size of secure memory 442, from reserving any amount of secure memory. In addition, hypervisor 104 may not reserve portions of secure memory already reserved for another application. Thus, in FIG. 4C, hypervisor 104 may reserve a reserved portion 446 for application 108. Reserved portion 446 may not exceed the global limit, and further does not overlap reserved portion 444” (Mesropian [0060] portion 446 is reserved for execution data of a main task of an application)
Regarding Claim 6, Mesropian further discloses wherein the system is configured to set a size of the first portion and a size of the second portion in the volatile memory based on requirements of the first application and second application, respectively.
“Hypervisor 104 may reserve the portion of secure memory for application 108 based on an availability of secure memory. For example, in FIG. 4B, a reserved portion 444 may have be previously reserved, for instance for another application, when hypervisor 104 receives the request from application 108. Hypervisor 104 may be limited by a global limit, such as the size of secure memory 442, from reserving any amount of secure memory. In addition, hypervisor 104 may not reserve portions of secure memory already reserved for another application. Thus, in FIG. 4C, hypervisor 104 may reserve a reserved portion 446 for application 108. Reserved portion 446 may not exceed the global limit, and further does not overlap reserved portion 444” (Mesropian [0060] The size of the portions reserved for the first and second application would be based on their requirements as long as it does not violate the reserving rules)
Regarding Claim 7, Mesropian further discloses wherein the system is configured such that execution data of the main task of the first application and the execution data of the task of the second application are simultaneously present in the volatile memory.
“For example, in FIG. 4B, a reserved portion 444 may have be previously reserved, for instance for another application, when hypervisor 104 receives the request from application 108. Hypervisor 104 may be limited by a global limit, such as the size of secure memory 442, from reserving any amount of secure memory. In addition, hypervisor 104 may not reserve portions of secure memory already reserved for another application. Thus, in FIG. 4C, hypervisor 104 may reserve a reserved portion 446 for application 108” (Mesropian [0060] see fig. 4C execution data for first application would be in portion 444 and execution data of second application would be in portion 446)
Regarding Claim 8, Mesropian further discloses wherein the system is configured so that the low-level operating system executes a memory management function that prevents access of execution data of one application to other applications.
“In certain implementations, hypervisor 104 may verify every I/O request to reserved portion 446 to ensure that only authenticated code 110 accesses reserved portion 446, and to prevent any other application or portions of code of application 108 from accessing reserved portion 446” (Mesropian [0048])
Regarding Claim 9, Mesropian further discloses wherein the embedded electronic system is part of an embedded secure element.
“Hypervisor 104 may reserve the portion of secure memory for application 108 based on an availability of secure memory” (Mesropian [0060])
Regarding Claim 10, He discloses a method implemented in an embedded electronic system that includes a volatile memory, the method comprising:
“Network device 100 may include one or more processors 102. Processors 102 may include single or multicore processors. System memory 104 may provide memory resources for processors 102. System memory 104 is typically a form of random access memory (RAM) (e.g., dynamic random access memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM))” (He [0032])
managing, by a low-level operating system, an allocation of areas of the volatile memory to a plurality of high-level operating systems, each high-level operating system executing one or more applications;
“As shown in the example depicted in FIG. 1, a host operating system 110 may be loaded in system memory 104 and executed by one or more processors 102. Host operating system 110 may be loaded, for example, when network device 100 is powered on. In certain implementations, host operating system 110 may also function as a hypervisor and facilitate management of virtual machines and other programs that are executed by network device 100. Managing virtual machines may include partitioning resources of network device 100, including processor and memory resources, between the various programs. A hypervisor is a program that enables the creation and management of virtual machine environments including the partitioning and management of processor, memory, and other hardware resources of network device 100 between the virtual machine environments” (He [0033] the low-level operating system is the hypervisor and the high level operating system is the virtual machine/host operating system)
“The operating system and applications executing within the guest virtual machine 320 generally use virtual addresses. A virtual machine is “virtual” in the sense that, from the perspective of the operating system and applications running within the virtual machine, the virtual machine appears indistinguishable from a physical machine” (He [0069])
But does not explicitly state reserving a first portion of the volatile memory for a storage of execution data of a main task of a first application; reserving a second portion of the volatile memory for a storage of execution data of a task of a second application; transitioning the first application from an active state to a standby state in response to the execution of the first application being interrupted;
loading the execution data of the main task of the first application into the first portion in response to the interruption; preventing the unloading of the execution data of the main task of the first application from the first portion in response to the interruption; and denying, by the low-level operating system, execution of the second application in response to the second application requiring storage space in the volatile memory greater than an available portion of the volatile memory, the available portion being equal to the total area of the volatile memory excluding the first portion.
Mesropian discloses reserving a first portion of the volatile memory for a storage of execution data of a main task of a first application; reserving a second portion of the volatile memory for a storage of execution data of a task of a second application;
“Hypervisor 104 may reserve the portion of secure memory for application 108 based on an availability of secure memory. For example, in FIG. 4B, a reserved portion 444 may have be previously reserved, for instance for another application, when hypervisor 104 receives the request from application 108. Hypervisor 104 may be limited by a global limit, such as the size of secure memory 442, from reserving any amount of secure memory. In addition, hypervisor 104 may not reserve portions of secure memory already reserved for another application. Thus, in FIG. 4C, hypervisor 104 may reserve a reserved portion 446 for application 108” (Mesropian [0060] one of the reserved portions 444 and 446 in secure memory 142 of volatile memory 140 would be for the first application and the other portion for the second application)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the reserving of memory in Mesropian with the system in He. The motivation for doing so would be improve the security of the memory so that there is no cross contamination between applications.
Couvee and Mesropian discloses transitioning the first application from an active state to a standby state in response to the execution of the first application being interrupted;
“A first step (step 700) is directed to detecting an interruption. If an interruption is detected, a following step (step 705) consists of a test to determine whether the interruption is directed to the suspension of the execution of a main application or not” (Couvee [0079])
“If the interruption is directed to the suspension of the execution of a main application, the context of the execution of that application is stored (step 710). As indicated previously, this step makes it possible in particular to store memory references in course of the main application” (Couvee [0080])
loading the execution data of the main task of the first application into the first portion in response to the interruption; preventing the unloading of the execution data of the main task of the first application from the first portion in response to the interruption; and
“The accessed data are then stored in an upper part of the memory according to predetermined parameters (step 810)” (Couvee [0089] see Fig. 7a, 7b, and 8)
“Hypervisor 104 may reserve the portion of secure memory for application 108 based on an availability of secure memory. For example, in FIG. 4B, a reserved portion 444 may have be previously reserved, for instance for another application, when hypervisor 104 receives the request from application 108. Hypervisor 104 may be limited by a global limit, such as the size of secure memory 442, from reserving any amount of secure memory. In addition, hypervisor 104 may not reserve portions of secure memory already reserved for another application. Thus, in FIG. 4C, hypervisor 104 may reserve a reserved portion 446 for application 108” (Mesropian [0060] the data loaded into the reserved portions would be prevented from unloading)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the interrupting, suspension, and loading of data described in Couvee with the system in the combination of He and Mesropian. The motivation for doing so would be improve the resuming of the first application as described by Couvee. “The invention is generally directed to a mechanism for anticipated loading of cache memory to load data linked to the execution of a first application, during the execution of a second application executed further to an interruption of execution of the first application, in order to enable optimum resumption of execution of the first application” (Couvee [0042])
Mesropian and Yu discloses denying, by the low-level operating system, execution of the second application in response to the second application requiring storage space in the volatile memory greater than an available portion of the volatile memory, the available portion being equal to the total area of the volatile memory excluding the first portion.
“Thus, in FIG. 4C, hypervisor 104 may reserve a reserved portion 446 for application 108. Reserved portion 446 may not exceed the global limit, and further does not overlap reserved portion 444” (Mesropian [0060] the required storage would be greater than the global limit/available portion)
“Accordingly, when a remaining capacity of the main memory is insufficient, the newly added task may be denied or the previous task may be finished compulsorily. It may be difficult to realize stable multi-tasking in mobile devices” (Yu [0113])
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the denying of execution described in Yu with the system in the combination of He, Mesropian, and Couvee. The motivation for doing so would be to keep the system running as execution of the new task would over provision/allocation of memory which would cause problems to other parts of the system when their memory is taken away.
Regarding Claim 11, Mesropian further discloses wherein the embedded electronic system comprises a non-volatile memory, and wherein the non-volatile memory is external to the embedded electronic system.
“communication interface 522 may also represent a host adapter configured to facilitate communication between computing system 510 and one or more additional network or storage devices via an external bus or communications channel. Examples of host adapters include, without limitation, Small Computer System Interface (SCSI) host adapters, Universal Serial Bus (USB) host adapters, Institute of Electrical and Electronics Engineers (IEEE) 1394 host adapters, Advanced Technology Attachment (ATA), Parallel ATA (PATA), Serial ATA (SATA), and External SATA (eSATA) host adapters, Fibre Channel interface adapters, Ethernet adapters, or the like. Communication interface 522 may also allow computing system 510 to engage in distributed or remote computing” (Mesropian [0091])
“Storage devices 532 and 533 generally represent any type or form of storage device or medium capable of storing data and/or other computer-readable instructions. For example, storage devices 532 and 533 may be a magnetic disk drive (e.g., a so-called hard drive), a solid state drive, a floppy disk drive, a magnetic tape drive, an optical disk drive, a flash drive, or the like” (Mesropian [0094] these storage devices can be connected via the interface disclosed in paragraph [0091])
Regarding Claim 12, Couvee further discloses further comprising transferring an execution code of an application from the non-volatile memory to the volatile memory for execution.
“In parallel, as illustrated in FIG. 7b when the resumption of the execution of a process is planned by the scheduler (step 720)” (Couvee [0083])
“The accessed data are then stored in an upper part of the memory according to predetermined parameters (step 810)” (Couvee [0089])
Regarding Claim 16, Couvee and Mesropian further discloses wherein managing the allocation comprises allocating a main task of an application to a volatile memory area and executing the main task.
“In parallel, as illustrated in FIG. 7b when the resumption of the execution of a process is planned by the scheduler (step 720)” (Couvee [0083])
“Hypervisor 104 may reserve the portion of secure memory for application 108 based on an availability of secure memory. For example, in FIG. 4B, a reserved portion 444 may have be previously reserved, for instance for another application, when hypervisor 104 receives the request from application 108. Hypervisor 104 may be limited by a global limit, such as the size of secure memory 442, from reserving any amount of secure memory. In addition, hypervisor 104 may not reserve portions of secure memory already reserved for another application. Thus, in FIG. 4C, hypervisor 104 may reserve a reserved portion 446 for application 108. Reserved portion 446 may not exceed the global limit, and further does not overlap reserved portion 444” (Mesropian [0060] portion 446 is reserved for execution data of a main task of an application)
Regarding Claim 17, Mesropian further discloses wherein execution data of a plurality of applications are simultaneously present in the volatile memory.
“For example, in FIG. 4B, a reserved portion 444 may have be previously reserved, for instance for another application, when hypervisor 104 receives the request from application 108. Hypervisor 104 may be limited by a global limit, such as the size of secure memory 442, from reserving any amount of secure memory. In addition, hypervisor 104 may not reserve portions of secure memory already reserved for another application. Thus, in FIG. 4C, hypervisor 104 may reserve a reserved portion 446 for application 108” (Mesropian [0060] see fig. 4C execution data for first application would be in portion 444 and execution data of second application would be in portion 446)
Regarding Claim 18, Mesropian further discloses further comprising preventing, by the low-level operating system, access of the execution data of one application to other applications.
“In certain implementations, hypervisor 104 may verify every I/O request to reserved portion 446 to ensure that only authenticated code 110 accesses reserved portion 446, and to prevent any other application or portions of code of application 108 from accessing reserved portion 446” (Mesropian [0048])
Claims 2, 14, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over He (published August 02, 2018), Mesropian (published October 03, 2019), Couvee (published May 02, 2013), and Yu (published March 07, 2013) as applied to claims 1 and 10 above, and further in view of Talagala et al. (US 2013/0332660) (hereinafter Talagala) (published December 12, 2013).
Regarding Claim 2, the combination of He, Mesropian, Couvee, and Yu disclosed the system of claim 1, and Mesropian further discloses wherein the embedded electronic system comprises a non-volatile memory,
“As illustrated in FIG. 1, example system 100 may also include storage device 120. Storage device 120 generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and/or computer-readable instructions” (Mesropian [0036])
But does not explicitly state wherein the embedded electronic system is configured such that the high-level operating systems manage a virtual image of the volatile memory and the non-volatile memory, and wherein the volatile memory and the non-volatile memory appears to be one and the same to the high-level operating system.
He and Talagala discloses wherein the embedded electronic system is configured such that the high-level operating systems manage a virtual image of the volatile memory and the non-volatile memory, and wherein the volatile memory and the non-volatile memory appears to be one and the same to the high-level operating system.
“The virtual machine thus has an address space that is distinct from the address space of the network device 300, which is commonly referred to as a virtual address space. Within the virtual address space, addresses that, in the network device 300, map to physical resources can be referred to as guest physical addresses” (He [0069] the virtual machine would manage the virtual address space that it uses)
“In one embodiment, an extended memory module is configured to use main memory of a host and a non-volatile recording medium as virtual memory of the host” (Talagala [0005])
“While the virtual memory 400 appears to a storage client 116 as a contiguous range of memory that behaves in a manner similar to volatile memory 112, the memory or storage that backs the virtual memory 400 may be physically distributed across different devices or media, across noncontiguous ranges of the same device or media, or the like” (Talagala [0103] see fig. 4 the OS sees the virtual memory and the mapped parts of the volatile and non-volatile memory and it would appear to be the same to the host)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the virtual memory of Talagala with the system in the combination of He, Mesropian, Couvee, and Yu. The motivation for doing so would be to provide a more efficient memory as described by Talagala. "The hybrid checkpointed memory module 136, in certain embodiments, leverages the speed of volatile memory, such as the host volatile memory 112 and/or the device volatile memory 128, with the cost, power-saving, and persistence advantages of the non-volatile storage media 122, to provide a cost and power efficient hybrid memory, capable of being persistently checkpointed to the non-volatile storage media 122" (Talagala [0052])
Regarding Claim 14, the combination of He, Mesropian, Couvee, and Yu disclosed the method of claim 10, but does not explicitly state wherein a non-volatile memory area allocated to the high-level operating system is seen by the high-level operating system as a volatile working memory.
Talagala discloses wherein a non-volatile memory area allocated to the high-level operating system is seen by the high-level operating system as a volatile working memory.
“In one embodiment, an extended memory module is configured to use main memory of a host and a non-volatile recording medium as virtual memory of the host” (Talagala [0005])
“While the virtual memory 400 appears to a storage client 116 as a contiguous range of memory that behaves in a manner similar to volatile memory 112, the memory or storage that backs the virtual memory 400 may be physically distributed across different devices or media, across noncontiguous ranges of the same device or media, or the like” (Talagala [0103] see fig. 4 the OS sees the virtual memory and the mapped parts of the volatile and non-volatile memory and it would appear to be the same to the host)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the virtual memory of Talagala with the system in the combination of He, Mesropian, Couvee, and Yu. The motivation for doing so would be to provide a more efficient memory as described by Talagala. "The hybrid checkpointed memory module 136, in certain embodiments, leverages the speed of volatile memory, such as the host volatile memory 112 and/or the device volatile memory 128, with the cost, power-saving, and persistence advantages of the non-volatile storage media 122, to provide a cost and power efficient hybrid memory, capable of being persistently checkpointed to the non-volatile storage media 122" (Talagala [0052])
Regarding Claim 15, the combination of He, Mesropian, Couvee, and Yu disclosed the method of claim 10, but does not explicitly state wherein the high-level operating systems manage a virtual image of the volatile and non-volatile memories where the volatile and non-volatile memories appear as a single memory.
He and Talagala discloses wherein the high-level operating systems manage a virtual image of the volatile and non-volatile memories where the volatile and non-volatile memories appear as a single memory.
“The virtual machine thus has an address space that is distinct from the address space of the network device 300, which is commonly referred to as a virtual address space. Within the virtual address space, addresses that, in the network device 300, map to physical resources can be referred to as guest physical addresses” (He [0069] the virtual machine would manage the virtual address space that it uses)
“In one embodiment, an extended memory module is configured to use main memory of a host and a non-volatile recording medium as virtual memory of the host” (Talagala [0005])
“While the virtual memory 400 appears to a storage client 116 as a contiguous range of memory that behaves in a manner similar to volatile memory 112, the memory or storage that backs the virtual memory 400 may be physically distributed across different devices or media, across noncontiguous ranges of the same device or media, or the like” (Talagala [0103] see fig. 4 the OS sees the virtual memory and the mapped parts of the volatile and non-volatile memory and it would appear to be the same to the host)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the virtual memory of Talagala with the system in the combination of He, Mesropian, Couvee, and Yu. The motivation for doing so would be to provide a more efficient memory as described by Talagala. "The hybrid checkpointed memory module 136, in certain embodiments, leverages the speed of volatile memory, such as the host volatile memory 112 and/or the device volatile memory 128, with the cost, power-saving, and persistence advantages of the non-volatile storage media 122, to provide a cost and power efficient hybrid memory, capable of being persistently checkpointed to the non-volatile storage media 122" (Talagala [0052])
Claim 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over He (published August 02, 2018), Mesropian (published October 03, 2019), Couvee (published May 02, 2013), and Yu (published March 07, 2013) as applied to claim 1 above, and further in view of Carbunar et al. (US 2012/0304234) (hereinafter Carbunar) (published November 29, 2012).
Regarding Claim 4, the combination of He, Mesropian, Couvee, and Yu disclosed the system of claim 1, and Mesropian further discloses wherein the non-volatile memory is internal to the embedded electronic system, and
“As illustrated in FIG. 1, example system 100 may also include storage device 120. Storage device 120 generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and/or computer-readable instructions” (Mesropian [0036] see fig. 1)
But does not explicitly state wherein the system is configured to transfer the execution data of the task of the second application to the non-volatile memory in response to the available portion of the volatile memory determined to be insufficient for the execution of a task of a third application.
Carbunar discloses wherein the system is configured to transfer the execution data of the task of the second application to the non-volatile memory in response to the available portion of the volatile memory determined to be insufficient for the execution of a task of a third application.
“Additionally, it should be noted that in both FIG. 5 and FIG. 6 the server may determine that there is not enough room to cache the requested content and then determine items to evict from a cache at the server to make room for the requested content, so as to minimize a network penalty associated with evicting the subset of items” (Carbunar [0069] the evicted data is the data from the second application and would be stored in non-volatile memory)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the data eviction disclosed in Carbunar with the system in the combination of He, Mesropian, Couvee, and Yu. The motivation for doing so would be to improve the operations of the memory by being able to make room for new data from different tasks.
Claim 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over He (published August 02, 2018), Mesropian (published October 03, 2019), Couvee (published May 02, 2013), and Yu (published March 07, 2013) as applied to claim 12 above, and further in view of Gross et al. (US 2004/0206981) (hereinafter Gross) (priority to October 21, 2004).
Regarding Claim 13, Mesropian further discloses wherein the non-volatile memory is internal to the embedded electronic system, and
“As illustrated in FIG. 1, example system 100 may also include storage device 120. Storage device 120 generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and/or computer-readable instructions” (Mesropian [0036] see fig. 1)
But does not explicitly state wherein an execution code of an application remains in the non-volatile memory during the execution of a task.
Gross discloses wherein an execution code of an application remains in the non-volatile memory during the execution of a task.
“The present invention is based on the realization that insulating floating gate technology could be used to fabricate both a random-access flash cell array and a serial-access flash cell array on the same die 26, while achieving relatively good performance for both non-code data handling and in-place code execution. The relatively good write/erase performance required for non-code data handling is available because insulating gate technology is a type of NOR technology that can achieve a write/erase speed similar to NAND technology” (Gross [0038] in-place execution would allow the code to remain in the same location such as in non-volatile memory)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the use of in-place execution disclosed in Gross with the system in the combination of He, Mesropian, Couvee, and Yu. The motivation for doing so would be to improve efficiency by allowing the execution of code directly from external memory without having to spend time transferring data to the internal memory.
Claim 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over He (published August 02, 2018) in view of Mesropian (published October 03, 2019), Talagala (published December 12, 2013), and Carbunar (published November 29, 2012).
Regarding Claim 19, He discloses an embedded electronic system, comprising: a volatile memory;
“Network device 100 may include one or more processors 102. Processors 102 may include single or multicore processors. System memory 104 may provide memory resources for processors 102. System memory 104 is typically a form of random access memory (RAM) (e.g., dynamic random access memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM))” (He [0032])
a processor configured to execute a low-level operating system that manages allocation of areas of the volatile memory to a plurality of high-level operating systems, each high-level operating system executing one or more applications,
“As shown in the example depicted in FIG. 1, a host operating system 110 may be loaded in system memory 104 and executed by one or more processors 102. Host operating system 110 may be loaded, for example, when network device 100 is powered on. In certain implementations, host operating system 110 may also function as a hypervisor and facilitate management of virtual machines and other programs that are executed by network device 100. Managing virtual machines may include partitioning resources of network device 100, including processor and memory resources, between the various programs. A hypervisor is a program that enables the creation and management of virtual machine environments including the partitioning and management of processor, memory, and other hardware resources of network device 100 between the virtual machine environments” (He [0033])
“The operating system and applications executing within the guest virtual machine 320 generally use virtual addresses. A virtual machine is “virtual” in the sense that, from the perspective of the operating system and applications running within the virtual machine, the virtual machine appears indistinguishable from a physical machine” (He [0069])
But does not explicitly state a non-volatile memory; and wherein a first portion of the volatile memory is reserved for a storage of execution data of a main task of a first application and a second portion of the volatile memory is reserved for a storage of execution data of a task of a second application, wherein the system is configured to: maintain the execution data of the first application in the first portion when the first application transitions from an active state to a standby state, and wherein the low-level operating system creates a virtual memory image for the high-level operating systems where the volatile memory and the non-volatile memory appear as a single memory space, and transfer execution data from the second portion to the non-volatile memory when the second application is interrupted and a third application requires execution space in the volatile memory.
Mesropian discloses a non-volatile memory; and
“As illustrated in FIG. 1, example system 100 may also include storage device 120. Storage device 120 generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and/or computer-readable instructions” (Mesropian [0036])
wherein a first portion of the volatile memory is reserved for a storage of execution data of a main task of a first application and a second portion of the volatile memory is reserved for a storage of execution data of a task of a second application,
“Hypervisor 104 may reserve the portion of secure memory for application 108 based on an availability of secure memory. For example, in FIG. 4B, a reserved portion 444 may have be previously reserved, for instance for another application, when hypervisor 104 receives the request from application 108. Hypervisor 104 may be limited by a global limit, such as the size of secure memory 442, from reserving any amount of secure memory. In addition, hypervisor 104 may not reserve portions of secure memory already reserved for another application. Thus, in FIG. 4C, hypervisor 104 may reserve a reserved portion 446 for application 108” (Mesropian [0060] one of the reserved portions 444 and 446 in secure memory 142 of volatile memory 140 would be for the first application and the other portion for the second application)
wherein the system is configured to: maintain the execution data of the first application in the first portion when the first application transitions from an active state to a standby state, and
“Hypervisor 104 may reserve the portion of secure memory for application 108 based on an availability of secure memory. For example, in FIG. 4B, a reserved portion 444 may have be previously reserved, for instance for another application, when hypervisor 104 receives the request from application 108” (Mesropian [0060] with a reserved portion allocated to the first application the execution data would stay in the reserved portion until it is deallocated)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the reserving of memory in Mesropian with the system in He. The motivation for doing so would be improve the security of the memory so that there is no cross contamination between applications.
Talagala and He discloses wherein the low-level operating system creates a virtual memory image for the high-level operating systems where the volatile memory and the non-volatile memory appear as a single memory space, and
“In one embodiment, an extended memory module is configured to use main memory of a host and a non-volatile recording medium as virtual memory of the host” (Talagala [0005])
“While the virtual memory 400 appears to a storage client 116 as a contiguous range of memory that behaves in a manner similar to volatile memory 112, the memory or storage that backs the virtual memory 400 may be physically distributed across different devices or media, across noncontiguous ranges of the same device or media, or the like” (Talagala [0103] see fig. 4 the OS sees the virtual memory and the mapped parts of the volatile and non-volatile memory and it would appear to be the same to the host)
“Generally, when the guest virtual machine 320 is initiated, the network device 300 (e.g., through the hypervisor 350 or a host operating system) can allocate a physical memory region in the physical memory 302, referred to here as the VM physical memory 304. The VM physical memory region 304 can be the part of physical memory 302 that is assigned to the guest virtual machine 320 for its exclusive use. The VM physical memory region 304 can be read and written using physical addresses” (He [0068] the virtual machine would use the VM physical memory assigned by the hypervisor and manage the virtual address space that it uses)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the virtual memory of Talagala with the system in the combination of He and Mesropian. The motivation for doing so would be to provide a more efficient memory as described by Talagala. "The hybrid checkpointed memory module 136, in certain embodiments, leverages the speed of volatile memory, such as the host volatile memory 112 and/or the device volatile memory 128, with the cost, power-saving, and persistence advantages of the non-volatile storage media 122, to provide a cost and power efficient hybrid memory, capable of being persistently checkpointed to the non-volatile storage media 122" (Talagala [0052])
Carbunar discloses transfer execution data from the second portion to the non-volatile memory when the second application is interrupted and a third application requires execution space in the volatile memory.
“Additionally, it should be noted that in both FIG. 5 and FIG. 6 the server may determine that there is not enough room to cache the requested content and then determine items to evict from a cache at the server to make room for the requested content, so as to minimize a network penalty associated with evicting the subset of items” (Carbunar [0069] the evicted data is the data from the second application and would be stored in non-volatile memory)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the data eviction disclosed in Carbunar with the system in the combination of He, Mesropian, and Talagala. The motivation for doing so would be to improve the operations of the memory by being able to make room for new data from different tasks.
Claim 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over He (published August 02, 2018), Mesropian (published October 03, 2019), Talagala (published December 12, 2013), and Park (priority to August 01, 2019) as applied to claim 19 above, and further in view of SAAD et al. (US 2018/0310148) (hereinafter Saad) (published October 25, 2018).
Regarding Claim 20, the combination of He, Mesropian, Talagala, and Park disclosed the system of claim 19, and Mesropian further discloses wherein the embedded electronic system is configured to: dynamically adjust sizes of the first portion and the second portion based on execution requirements of active applications.
“In some implementations, the API may allow expanding, based on a request from the authenticated application, the reserved portion of the secure memory based on a remaining portion of the memory. For example, authenticated code 110 may request additional secure memory, for instance expanding reserved portion 446. If enough unreserved secure memory 442 is available, reserved portion 446 may be expanded to satisfy the request, as seen in FIG. 4D” (Mesropian [0070] the reserved portions are dynamically adjusted based on needs)
But does not explicitly state detect whether an application is a resident application based on a request sent by the application at first loading, deny installation of an application as a resident application when a predetermined portion of the volatile memory is already reserved for resident applications,
Saad and Mesropian discloses detect whether an application is a resident application based on a request sent by the application at first loading, (see 112 interpretation above)
“The secure element 10 comprises an operating system 30. Two transport applications 40 and 50 are installed in the secure element 10. The operating system 30 is designed to allow installation of several applications as being implicitly selected on the same communication interface. For instance, applications 40 and 50 are individually configured to be implicitly selected on the first communication interface 20” (Saad [0029])
deny installation of an application as a resident application when a predetermined portion of the volatile memory is already reserved for resident applications,
“The secure element 10 comprises an operating system 30. Two transport applications 40 and 50 are installed in the secure element 10. The operating system 30 is designed to allow installation of several applications as being implicitly selected on the same communication interface. For instance, applications 40 and 50 are individually configured to be implicitly selected on the first communication interface 20” (Saad [0029])
“the operating system 30 is configured to deny a request of activation of one application which his implicitly selected on a given communication interface if another application which his implicitly selected on the same communication interface is already activated” (Saad [0031] the application is not installed as the resident application but secondary as it is deny activation)
“For example, in FIG. 4B, a reserved portion 444 may have be previously reserved, for instance for another application, when hypervisor 104 receives the request from application 108” (Mesropian [0060] portion 444 is already reserved for the first application)
It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the installing of multiple application and denying activation of one in Saad with the system in the combination of He, Mesropian, Talagala, and Park. The motivation for doing so would be to reduce the amount of management needed to maintain multiple applications that uses the same type as disclosed in SAAD. “It may happen that a user needs to have several applications of the same type in a secure element. For instance, when the user travels from city A to city B, he/she has to manually uninstall/unregister the current transport application corresponding to City A before installing the transport application relevant for accessing the urban transport network of City B with implicit selection settings. Such uninstall/install operations are long and may be complex. There are not convenient for a user” (Saad [0005])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hepkin et al. (US 2011/0107054) disclose the pinning of a page to reserve for use by an application
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/S.L./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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