The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination in this application (19/262,757) filed on July 8, 2025.
The Examiner cites particular sections in the references as applied to the claims below for the convenience of the applicant(s). Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant(s) fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claims 1-20 are pending for consideration.
Drawings
The drawings submitted on July 8, 2025 have been considered and accepted.
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on July 8, 2025. U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 6, 8, 10, 13, 15, 17 and 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Li et al. (US PGPUB 2023/0147472 hereinafter referred to as Li).
As per independent claim 1, Li discloses a storage device comprising: a storage controller including an embedding model buffer and an accelerator; and a nonvolatile memory operatively connected to the storage controller, wherein the nonvolatile memory is configured to store target data and model data of an embedding model [(Paragraphs 0054-0059; FIGs. 2A-B and related text) wherein Li teaches wherein the embedded vectors calculated by the computational storage system 130 may be saved to the exposed portions 190 of the caches 175 of the computational storage devices 170 (e.g., in iteration-table-item order), and read from the exposed portions 190 of the caches 175 of the computational storage devices 170 by the GPUs 140. The use of a cache coherent system interconnect 135 may enable the GPUs to copy the embedded vectors directly to the level 2 caches 145 of the GPU system 125, without first copying them to the VRAM 150. This may significantly improve the efficiency of the system (e.g., it may significantly increase the speed and reduce the energy consumption per neural network operation). The GPU system 125 may operate in a data-parallel mode, and each GPU 140 may fetch, from exposed portion 190 of the caches 175 of one of the computational storage devices 170, and process, a respective subset of the embedded vectors produced by the computational storage system 130. The gradients (of the cost function with respect to the weights of the embedding tables 110), may be calculated by the top multi-layer perceptron 115 (which is implemented in the GPU system 125), and written, by the GPU system 125, to the exposed portions 190 of the caches 175 of the computational storage devices 170 by the GPUs 140. The controllers 180 of the computational storage devices 170 may then update the embedding tables 110 based on the gradients to correspond to the claimed limitation], and, wherein the storage controller is configured to: based on a first request from a host, transmit a read command for the target data to the nonvolatile memory, receive the target data from the nonvolatile memory, and generate an embedding vector using the accelerator based on the received target data and the model data loaded into the embedding model buffer [(Paragraphs 0056-0059; FIGs. 2A-B and related text) wherein Li teaches wherein the training pipeline starts from the CPU of the host 120. Processing of the input data may be performed by the host 120, since this approach provides the flexibility to implement different shuffle and partition schemes. The host 120 may (i) notify a GPU 140 to fetch dense features directly from the host's main memory, and (ii) send the sparse features to the computational storage devices 170 through the input-output (io) protocol (e.g., through CXL.io). The computational storage device 170 may fetch corresponding rows from the backing store 185 to the cache 175 of the computational storage device 170 (if it is not already there), and load the rows that are used by the current iteration to an on-chip cache in the controller 180 (e.g., to a memory or buffer in the controller 180) to correspond to the claimed limitation]; and based on a second request from the host, transmit, to the host, the target data and the generated embedding vector [(Paragraphs 0056-0059; FIGs. 2A-B and related text) wherein Li teaches wherein the host 120 may (i) notify a GPU 140 to fetch dense features directly from the host's main memory, and (ii) send the sparse features to the computational storage devices 170 through the input-output (io) protocol (e.g., through CXL.io). The computational storage device 170 may fetch corresponding rows from the backing store 185 to the cache 175 of the computational storage device 170 (if it is not already there), and load the rows that are used by the current iteration to an on-chip cache in the controller 180 (e.g., to a memory or buffer in the controller 180); the training pipeline starts from the CPU of the host 120. Processing of the input data may be performed by the host 120, since this approach provides the flexibility to implement different shuffle and partition schemes. The host 120 may (i) notify a GPU 140 to fetch dense features directly from the host's main memory, and (ii) send the sparse features to the computational storage devices 170 through the input-output (io) protocol (e.g., through CXL.io). The computational storage device 170 may fetch corresponding rows from the backing store 185 to the cache 175 of the computational storage device 170 (if it is not already there), and load the rows that are used by the current iteration to an on-chip cache in the controller 180 (e.g., to a memory or buffer in the controller 180) to correspond to the claimed limitation].
As per dependent claim 3, Li discloses wherein the storage controller is further configured to: convert the received target data into chunk data; and generate the embedding vector by performing an embedding operation on the chunk data using the accelerator [(Paragraphs 0048-0054) wherein the neural network may receive both dense (continuous) and sparse (categorical) inputs. The dense inputs may be processed with the bottom multi-layer perceptron 105, and sparse features may be processed with an embedding operation, e.g., with the embedding tables 110. The sparse inputs may be vectors of indices (i.e., vectors the elements of which include (e.g., are) indices), each index identifying a row of an embedding matrix. The embedding operation, for one sparse input vector, may include (e.g., consist of) retrieving the rows identified by the indices of the sparse input vector, and calculating the sum of the rows, to form a vector that may be referred to as an “embedded vector”. The outputs of the bottom multi-layer perceptron 105 and of the embedding tables 110 may be combined in a feature interaction function and fed to the top multi-layer perceptron 115, which generates the output of the neural network (e.g., a predicted click-through rate (CTR)) to correspond to the claimed limitation].
As per dependent claim 6, Li discloses wherein the storage controller is further configured to: receive a model read request from the host; transmit a read command for the model data to the nonvolatile memory based on the model read request; receive the model data from the nonvolatile memory; and load the model data into the embedding model buffer [(Paragraphs 0056-0059; FIGs. 2A-B and related text) wherein Li teaches wherein the host 120 may (i) notify a GPU 140 to fetch dense features directly from the host's main memory, and (ii) send the sparse features to the computational storage devices 170 through the input-output (io) protocol (e.g., through CXL.io). The computational storage device 170 may fetch corresponding rows from the backing store 185 to the cache 175 of the computational storage device 170 (if it is not already there), and load the rows that are used by the current iteration to an on-chip cache in the controller 180 (e.g., to a memory or buffer in the controller 180); the training pipeline starts from the CPU of the host 120. Processing of the input data may be performed by the host 120, since this approach provides the flexibility to implement different shuffle and partition schemes. The host 120 may (i) notify a GPU 140 to fetch dense features directly from the host's main memory, and (ii) send the sparse features to the computational storage devices 170 through the input-output (io) protocol (e.g., through CXL.io). The computational storage device 170 may fetch corresponding rows from the backing store 185 to the cache 175 of the computational storage device 170 (if it is not already there), and load the rows that are used by the current iteration to an on-chip cache in the controller 180 (e.g., to a memory or buffer in the controller 180) to correspond to the claimed limitation].
As for independent claims 8 and 15, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
As for dependent claims 10 and 17, the applicant is directed to the rejections to claim 3 set forth above, as they are rejected based on the same rationale.
As for dependent claims 13 and 20, the applicant is directed to the rejections to claim 6 set forth above, as they are rejected based on the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 9 and 16 are rejected under 35 U.S.C. 103(a) as being disclosed by Li, as applied to claims 1, 8 and 15, in view of Park et al. (US PGPUB 2017/0315879 hereinafter referred to as Park).
As per dependent claim 2, Li discloses the storage device of claim 1.
Li does not appear to explicitly disclose wherein the storage controller is further configured to: based on the first request, check whether the model data is loaded into the embedding model buffer; transmit an input/output (I0) fail response to the host, based on a first check result that the model data is not loaded into the embedding model buffer; and transmit the read command for the target data to the nonvolatile memory, based on a second check result that the model data is loaded into the embedding model buffer.
Park discloses wherein the storage controller is further configured to: based on the first request, check whether the model data is loaded into the embedding model buffer; transmit an input/output (I0) fail response to the host, based on a first check result that the model data is not loaded into the embedding model buffer [(Paragraphs 0076 and 0171) wherein Park teaches where the fault detection module FDM may detect a fault generated at any other element(s) of the storage device 100 as well as the nonvolatile memory device 110. For example, when the buffer memory 130 does not respond or when an access of the buffer memory 130 fails, the fault detection module FDM may determine that the global fault is generated. In addition, when a super capacitor or a tantalum capacitor is present in the storage device 100, the fault detection module FDM may receive a fail signal from an auxiliary power supply. In response to the fail signal, the fault detection module FDM may determine whether the global fault is generated. If the global fault is generated, the fault informing module FIM may send the fault information to the host device 20 to correspond to the claimed limitation]; and transmit the read command for the target data to the nonvolatile memory, based on a second check result that the model data is loaded into the embedding model buffer [(Paragraphs 0077-0079) wherein Park teaches where FIG. 6 illustrates the fault detection module FDM detecting a fault based on a detection policy according to an exemplary embodiment of the inventive concept. Referring to FIGS. 1 and 6, the fault detection module FDM may perform fault detection based on a direct detection policy set in the detection policy module DPM. In operation S510, the host device 20 may send an access request to the controller 120. In operation S520, the host device 20 may send the access request to the nonvolatile memory device 110 in response to the access request of the host device 20 to correspond to the claimed limitation].
Li and Park are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of Li and Park before him or her, to modify the device of Li to include checking whether model data is loaded into the buffer of Park because it will enhance storage allocation.
The motivation for doing so would be [“permit write, read, and erase operations with respect to the logical addresses, which belong to the range of the reduced logical addresses, without restriction” (Paragraph 0123 by Park)].
Therefore, it would have been obvious to combine Li and Park to obtain the invention as specified in the instant claim.
As for dependent claims 9 and 16, the applicant is directed to the rejections to claim 2 set forth above, as they are rejected based on the same rationale.
Claims 4, 11 and 18 are rejected under 35 U.S.C. 103(a) as being disclosed by Li, as applied to claims 1, 8 and 15, in view of Eggert et al. (US PGPUB 2025/0111204 hereinafter referred to as Eggert).
As per dependent claim 4, Li discloses the storage device of claim 1.
Li does not appear to explicitly disclose wherein the target data comprises text data in page units, and wherein the chunk data comprises text data in at least one of a word, a sentence, or a paragraph.
Eggert discloses wherein the target data comprises text data in page units, and wherein the chunk data comprises text data in at least one of a word, a sentence, or a paragraph [(Paragraphs 0007 and 0011) wherein the natural-language oriented memory storage system that includes language embedding of text chunks. This approach uses language embedding in order to find a preselection of relevant text chunks (snippets) based on a determined similarity of a query with the chunks of text in the embedding space. The preselection provides identifiable chunks of text that contain text that is semantically similar and hence assumed relevant for answering the query. Together with the initial query, the (pre-) selected chunks of text are passed to the LLM for generating an answer to the query. The known mixed-structure approach suffers from basing the preselection of relevant text chunks exclusively on a similarity of the embedding. Other memory items, which may be relevant for the query but do not contain semantically similar terms, e.g., because they include complementary information, will not be considered for generating the response to correspond to the claimed limitation].
Li and Eggert are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of Li and Eggert before him or her, to modify the device of Li to include the data chunks of texts of Eggert because it will enhance storage allocation.
The motivation for doing so would be [“Improving continuously and incrementally, a growing proprietary memory without the need of costly retraining or fine-tuning general LLMs is desirable” (Paragraph 0008 by Eggert)].
Therefore, it would have been obvious to combine Li and Eggert to obtain the invention as specified in the instant claim.
As for dependent claims 11 and 18, the applicant is directed to the rejections to claim 4 set forth above, as they are rejected based on the same rationale.
Claims 5, 12 and 19 are rejected under 35 U.S.C. 103(a) as being disclosed by Li, as applied to claims 1, 8 and 15, in view of Bottger et al. (US PGPUB 2021/0081355 hereinafter referred to as Bottger).
As per dependent claim 5, Li discloses wherein the storage controller is further configured to: receive a model open request from the host; transmit a read command for metadata of the model data to the nonvolatile memory based on the model open request; receive the metadata from the nonvolatile memory [(Paragraphs 0056-0059; FIGs. 2A-B and related text) wherein Li teaches wherein the host 120 may (i) notify a GPU 140 to fetch dense features directly from the host's main memory, and (ii) send the sparse features to the computational storage devices 170 through the input-output (io) protocol (e.g., through CXL.io). The computational storage device 170 may fetch corresponding rows from the backing store 185 to the cache 175 of the computational storage device 170 (if it is not already there), and load the rows that are used by the current iteration to an on-chip cache in the controller 180 (e.g., to a memory or buffer in the controller 180); the training pipeline starts from the CPU of the host 120. Processing of the input data may be performed by the host 120, since this approach provides the flexibility to implement different shuffle and partition schemes. The host 120 may (i) notify a GPU 140 to fetch dense features directly from the host's main memory, and (ii) send the sparse features to the computational storage devices 170 through the input-output (io) protocol (e.g., through CXL.io). The computational storage device 170 may fetch corresponding rows from the backing store 185 to the cache 175 of the computational storage device 170 (if it is not already there), and load the rows that are used by the current iteration to an on-chip cache in the controller 180 (e.g., to a memory or buffer in the controller 180) to correspond to the claimed limitation].
Li does not appear to explicitly disclose generate a file descriptor based on the metadata; and transmit the generated file descriptor to the host.
Bottger discloses generate a file descriptor based on the metadata; and transmit the generated file descriptor to the host [(Paragraphs 0069-0071) wherein the descriptor file is generated. For example, when the PDB is unplugged from the host CDB, an PDB descriptor is generated. In an embodiment, the PDB descriptor contains information about the names and full paths of tablespaces. The PDB descriptor file may be formatted according to XML or JSON for example. In an embodiment, the PDB descriptor contains all required information to allow the PDB to subsequently “plug” into the same or different CDB. At step 410, the descriptor file and data files associated with the PDB are combined into an archive file. Data files that contain the contents of the unplugged PDB, including schema, tables, and records are written into the archive file. An archive file may be a tar file, a compressed file, or an archive of any format that aggregates multiple files into one file, such as a library file. At step 412, the archive file is copied or otherwise transferred to a tier-two storage to correspond to the claimed limitation].
Li and Bottger are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of Li and Bottger before him or her, to modify the device of Li to include the file descriptor of Bottger because it will enhance storage allocation.
The motivation for doing so would be [“enable limited or expensive hardware and/or software resources to service a greater number of cloud users and instances without requiring the purchase of additional resources or expensive upgrades of the current resources and without impacting the core functionality or overall performance of such services” (Paragraph 0006 by Bottger)].
Therefore, it would have been obvious to combine Li and Bottger to obtain the invention as specified in the instant claim.
As for dependent claims 12 and 19, the applicant is directed to the rejections to claim 5 set forth above, as they are rejected based on the same rationale.
Claims 7 and 14 are rejected under 35 U.S.C. 103(a) as being disclosed by Li, as applied to claims 1, 8 and 15, in view of Lee et al. (US PGPUB 2017/0282865 hereinafter referred to as Lee), and further in view of in view of Tadokoro et al. (US PGPUB 2024/0282865 hereinafter referred to as Tadokoro).
As per dependent claim 7, Li discloses the storage device of claim 1.
Li does not appear to explicitly disclose wherein the storage controller is further configured to: receive a model close request from the host, and perform a close operation on the model data in the nonvolatile memory based on the model close request; and receive a model data flush request from the host, and remove the model data loaded into the embedding model buffer based on the model data flush request.
Lee discloses wherein the storage controller is further configured to: receive a model close request from the host, and perform a close operation on the model data in the nonvolatile memory based on the model close request [(Paragraphs 0005-0010) wherein Lee teaches a method of operating a data storage device including a non-volatile memory device. The method includes receiving an update command from a host; and closing a first log block, which is included in the non-volatile memory device and which includes an open word line, in response to the update command to correspond to the claimed limitation].
Li and Lee are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of Li and Lee before him or her, to modify the device of Li to include the close requests of Lee because it will enhance storage allocation.
The motivation for doing so would be [“to avoid update data transmitted from the host being subsequently written to an empty page of the first log block” (Paragraph 0016 by Lee)].
Li does not appear to explicitly disclose receive a model data flush request from the host, and remove the model data loaded into the embedding model buffer based on the model data flush request.
Tadokoro discloses receive a model data flush request from the host, and remove the model data loaded into the embedding model buffer based on the model data flush request [(Paragraphs 0018) wherein the memory controller 12 may receive a command requesting a flush process (hereinafter referred to as “flush command”) from the host 14. The flush process is a process in which the host 14 requests the memory system 1 to make all data nonvolatile, and the process is executed in response to the flush command from the host 14. Upon receiving the flush command from the host 14, the memory system 1 executes a process of writing any unwritten data stored in the write buffer 11A to a NAND flash memory chip 23 (also referred to as a non-volatilization process). The end location of the unwritten data stored in the write buffer 11A when the flush command is issued becomes target data for the nonvolatile process corresponding to the flush command to correspond to the claimed limitation].
Li and Tadokoro are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of Li and Tadokoro before him or her, to modify the device of Li to include the of Tadokoro because it will enhance storage allocation.
The motivation for doing so would be [“restore data even when momentary shutdown, such as improper shutdown of power supply, occurs during writing and data written in the lower block is lost” (Paragraph 0014 by Tadokoro)].
Therefore, it would have been obvious to combine Li and Tadokoro to obtain the invention as specified in the instant claim.
As for dependent claim 14, the applicant is directed to the rejections to claim 7 set forth above, as they are rejected based on the same rationale.
Pertinent Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Eom et al., US PGPUB 2020/0151055 – teaches STORAGE DEVICE USING HOST MEMORY AND OPERATING METHOD THEREOF.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMED GEBRIL whose telephone number is (571)270-1857. The examiner can normally be reached on Monday-Friday, 8:00am-5:00pm.ALT. Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857.
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/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135
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