DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/09/2026 is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-8, 14, 16 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Resnick (US2011/0099431) in view of Harris et al. (US6,601,151).
With respect claim 1, Resnick teaches a controller coupled to the set of queues (see paragraph 28; memory controller 100 includes a request queue 110, a bank decoder 120, bank queues (130-0, 130-1, through 130-n)) and capable of:
for the first read queue, determining whether a first memory bank of the set of memory banks to be accessed by a first read request of the first read queue is available (see Fig. 4 and paragraph 61-62; operation block 401 a next memory request is retrieved from the appropriate bank queue. The appropriate bank queue may be determined by using a round-robin scheme or a prioritized selection based on bank queue… process is currently in a read sequence, operation continues at decision block 404, which determines if the request is a read and if the requested bank is not busy (e.g., being activated or pre-charged) (i.e., it is determined if the memory bank to be accessed by the queue is available)); and
based on determining that the first memory bank is available, scheduling the first read request for execution (see Fig. 4 and paragraphs 63-64; If the bank is to remain open, operation block 414 performs the read cycle on the memory bus 280 (FIG. 2). If the bank is to be closed, operation block 416 performs the read cycle on the memory bus 280 (FIG. 2), while indicating, in the same command, that a precharge is needed after the read operation. With the read cycle completed, some embodiments may include a wait decision block 418, which waits until there is space in the read buffer 154 (FIG. 2) to store the returned read data (i.e., if bank being accessed by the queue is available, the read is performed)).
Resnick does not explicitly teach for the second read queue determining whether a second memory bank of the set of memory banks to be accessed by a second read request that is at a front of the second read queue is same as the first memory bank; and based on determining that the second memory bank is same as the first memory bank, refraining from scheduling the second read request for execution; and based on refraining from scheduling the second read request for execution, determining whether a third memory bank of the set of memory banks to be accessed by a third read request that is next to the second read request in the second read queue is same as the first memory bank.
However, Resnick teaches wherein when a prior read is executed it is determined if read cycles are to continue, and if read operations are to be continued updating the bank number (i.e., a second bank and bank queue is selected) (see Fig. 4, and paragraph 65); and a next memory request is retrieved from the appropriate bank queue (see paragraph 61); which determines if the request is a read and if the requested bank is not busy (e.g., being activated or pre-charged) (i.e., it is determined if bank being accessed by the new read is busy/being used by a previously read). If not, operation block 406 updates the bank number for the current read request and cycles to look at the next bank/queue (i.e., if the bank being accessed is busy, the second request is not processed and a new/updated bank/bank queue is selected; then the process of determining if the bank being accessed is available is repeated) (see paragraph 62).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system to include the above mentioned to execute requests having a higher priority in a timely manner (see Resnick, paragraph 45).
Resnick et al. does not teach a set of read queues including a first read queue and a second read queue each capable of storing one or more read requests to access a set of memory banks, wherein the first read queue is designated as a priority read queue.
However, Harris teaches a first and second read queues 30 and 80; wherein the first read queue 30 receives high priority read requests, the second read queue 80 receives low priority read requests (see column 11, lines 47-52).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Resnick to include the above mentioned to increase overall system performance (see Harris, column 3, lines 54-59).
With respect claim 2, Resnick does not explicitly teach wherein the controller is capable of: for the second read queue, based on determining that the second memory bank is different from the first memory bank, scheduling the second read request for execution.
However, Resnick teaches wherein when a prior read is executed it is determined if read cycles are to continue, and if read operations are to be continued updating the bank number (i.e., a second bank and bank queue is selected) (see Fig. 4, and paragraph 65); and a next memory request is retrieved from the appropriate bank queue (see paragraph 61); which determines if the request is a read and if the requested bank is not busy (e.g., being activated or pre-charged) (i.e., it is determined if bank being accessed by the new read is busy/being used by a previously read); and based on determining that the memory bank being accessed is available, scheduling the read request for execution (see Fig. 4 and paragraphs 63-64; If the bank is to remain open, operation block 414 performs the read cycle on the memory bus 280 (FIG. 2). If the bank is to be closed, operation block 416 performs the read cycle on the memory bus 280 (FIG. 2), while indicating, in the same command, that a precharge is needed after the read operation. With the read cycle completed, some embodiments may include a wait decision block 418, which waits until there is space in the read buffer 154 (FIG. 2) to store the returned read data (i.e., if bank being accessed by the queue is available, the read is performed).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system to include the above mentioned to execute requests having a higher priority in a timely manner (see Resnick, paragraph 45).
With respect claim 3, Resnick teaches wherein the first read request is executed prior to the second read request available (see Fig. 4 and paragraph 61-62 and 64; operation block 401 a next memory request is retrieved from the appropriate bank queue. The appropriate bank queue may be determined by using a round-robin scheme or a prioritized selection based on bank queue… process is currently in a read sequence, operation continues at decision block 404, which determines if the request is a read and if the requested bank is not busy (e.g., being activated or pre-charged) (i.e., it is determined if the memory bank to be accessed by the queue is available)… and after the first read is executed a new/second command is selected to be executed).
With respect claim 5, Resnick teaches wherein the first read request is at a front of the first read queue (see paragraph 56; requests with higher priority are at the front of the queue).
With respect claim 6, Resnick teaches wherein the controller is capable of: for the first scheduling the first read request for execution (see paragraphs 61-62; a memory request is retrieved from the appropriate bank queue (see paragraph 61); which determines if the request is a read and if the requested bank is not busy (e.g., being activated or pre-charged) (i.e., it is determined if bank being accessed by the new read is busy/being used by a previously read). If not, operation block 406 updates the bank number for the current read request and cycles to look at the next bank/queue (i.e., if the bank being accessed is busy, the request is not processed)).
Resnick does not explicitly teach based on refraining from scheduling the first read request for execution, determining whether a fourth memory bank of the set of memory banks to be accessed by a fourth read request that is next to the first read request in the first read queue is available; and based on determining that the fourth memory bank is available, scheduling the fourth read request for execution; and for the second read queue, determining whether the second memory bank is same as the fourth memory bank.
However, Resnick teaches wherein when a next memory request is retrieved from the appropriate bank queue (see paragraph 61); which determines if the request is a read and if the requested bank is not busy (e.g., being activated or pre-charged) (i.e., it is determined if bank being accessed by the new read is busy/being used by a previously read). If not, operation block 406 updates the bank number for the current read request and cycles to look at the next bank/queue (i.e., if the bank being accessed is busy, the second request is not processed and a new/updated bank/bank queue is selected; then the process of determining if the bank being accessed is available is repeated) (see paragraph 62).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system to include the above mentioned to execute requests having a higher priority in a timely manner (see Resnick, paragraph 45).
With respect claim 7, Resnick does not explicitly teach wherein the controller is capable of: for the second read queue, based on determining that the second memory bank is same as the fourth memory bank, refraining from scheduling the second read request for execution; and based on refraining from scheduling the second read request for execution, determining whether the third memory bank is same as the fourth memory bank.
However, Resnick teaches wherein when a next memory request is retrieved from the appropriate bank queue (see Fig. 4 and paragraph 61); which determines if the request is a read and if the requested bank is not busy (e.g., being activated or pre-charged) (i.e., it is determined if bank being accessed by the new read is busy/being used by a previously read). If not, operation block 406 updates the bank number for the current read request and cycles to look at the next bank/queue (i.e., if the bank being accessed is busy, the second request is not processed and a new/updated bank/bank queue is selected; then the process of determining if the bank being accessed is available is repeated) (see Fig. 4 and paragraph 62).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system to include the above mentioned to execute requests having a higher priority in a timely manner (see Resnick, paragraph 45).
With respect claim 8, Resnick does not explicitly teach wherein the controller is capable of: for the second read queue, based on determining that the second memory bank is different from the fourth memory bank, scheduling the second read request for execution.
However, Resnick teaches execution a memory request is retrieved from the appropriate bank queue (see paragraph 61); which determines if the request is a read and if the requested bank is not busy (e.g., being activated or pre-charged) (i.e., it is determined if bank being accessed by a new read is busy/being used by a previously read). If not, operation block 406 updates the bank number for the current read request and cycles to look at the next bank/queue (i.e., if the bank being accessed is busy, the request is not processed) (see paragraphs 61-62).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system to include the above mentioned to execute requests having a higher priority in a timely manner (see Resnick, paragraph 45).
With respect claim 14, Resnick teaches wherein the controller is coupled to the set of queues (see paragraph 28; memory controller 100 includes a request queue 110, a bank decoder 120, bank queues (130-0, 130-1, through 130-n)) and capable of:
for the first write queue, determining whether a fourth memory bank to be accessed by a first write request at a front of the first write queue is available (see Fig. 4 and paragraph 66; operation block 401 a next memory request is retrieved from the appropriate bank queue. The appropriate bank queue may be determined by using a round-robin scheme or a prioritized selection based on bank queue… if the process is currently in a write sequence, operation continues at decision block 454, which determines if the request is a write and if the requested bank is not busy (i.e., it is determined if the memory bank to be accessed by the queue is available)); and
based on determining that the fourth memory bank is available, scheduling the first write request for execution (see paragraph 67; If the bank is not open, operation block 460 activates the bank. Decision block 462 tests to determine whether the control logic is set so that the bank should be left open at the conclusion of the current write request (i.e., if bank is not busy write request is performed)).
Resnick does not teach a set of write queues including a first write queue and a second write queue each capable of storing one or more write requests to access the set of memory banks.
However, Harris et al. teaches first and second read queues 30 and 80, and a single write queue 130… if multiple write queues are provided, source priority values can be allotted to write access requests as well as read access requests and the routing performed solely on the basis of the source priority value (see column 11, lines 48-60).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Resnick to include the above mentioned to increase overall system performance (see Harris, column 3, lines 54-59).
With respect claim 16, Resnick teaches wherein the controller is capable of: for the first write queue, determining whether the fourth memory bank is available based on determining whether the fourth memory bank is being accessed by another request (see Fig. 4 and paragraphs 63-64; If the bank is to remain open, operation block 414 performs the read cycle on the memory bus 280 (FIG. 2). If the bank is to be closed, operation block 416 performs the read cycle on the memory bus 280 (FIG. 2), while indicating, in the same command, that a precharge is needed after the read operation. With the read cycle completed, some embodiments may include a wait decision block 418, which waits until there is space in the read buffer 154 (FIG. 2) to store the returned read data (i.e., if bank being accessed is not being accessed by any other command/queue, the next command is performed)).
With respect claim 19, Resnick does not explicitly teaches wherein the controller is capable of: for the first write queue, based on determining that the fourth memory bank is not available, refraining from scheduling the first write request for execution; and for the second write queue, determining whether a fifth memory bank to be accessed by a second write request that is at a front of the second write queue is available.
However, Resnick teaches wherein when a next memory request is retrieved from the appropriate bank queue (see Fig. 4 and paragraph 61); which determines if the request is a read request or a write request and if the requested bank is not busy (i.e., it is determined if bank being accessed by the new read is busy/being used by a previously read). If not, operation block 406 updates the bank number for the current read request and cycles to look at the next bank/queue (i.e., if the bank being accessed is busy, the second request is not processed and a new/updated bank/bank queue is selected; then the process of determining if the bank being accessed is available is repeated) (see Fig. 4 and paragraph 62 and 66).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system to include the above mentioned to execute requests having a higher priority in a timely manner (see Resnick, paragraph 45).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Resnick (US2011/0099431) and Harris et al. (US6,601,151) as applied to claims 1-2 above, and further in view of Tam (US8,171,234).
With respect claim 4, Resnick and Harris et al. do not teach wherein the first read request is executed concurrently with the second read request.
However, Tam teaches Multiple different memory banks may be concurrently accessed in response to access requests received on different ports (see column 1, lines 54-67)… a read operation initiated on the read port P1 during the first cycle of the system clock signal CLK may be performed to a second (different) memory bank within memory core 101. A read operation initiated on the read port P2 during the first cycle of the system clock signal CLK may be concurrently performed to a third (different) memory bank within memory core 101 (see column 10, lines 51-57).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Resnick and Harris et al. to include the above mentioned to optimize the performance and power of memory system (see Tam, column 11, lines 11-12).
Claim(s) 9 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Resnick (US2011/0099431) and Harris et al. (US6,601,151) as applied to claims 1 and 14 above, and further in view of Dortu et al. (US8,635,393).
With respect claim 9, Resnick and Harris et al. do not teach wherein the controller is capable of: for the first read queue, determining whether the first memory bank is available based on lapse of time since a most recent access of the first memory bank.
However, Dortu teaches state checking device thus checks the memory bank state, in particular, by logging or detecting a time log since the time of the last read command for the memory bank to be checked and comparing said time log with the word line cycle time t.sub.RC. If the period of time which has elapsed is within the word line cycle time t.sub.RC, it is generally not possible to directly read the data which are to be read from the relevant memory bank, with the result that the "t.sub.RC condition" is not satisfied. Alternatively, it is possible for the active memory banks to generate a state signal which indicates that they are available for a read access operation (see column 4, lines 45-56).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Resnick and Harris er al. to include the above mentioned to achieve a shorter effective access time (see Dortu, column 3, lines 10-14).
With respect claim 15, Resnick and Harris et al. do not teach wherein the controller is capable of: for the first write queue, determining whether the fourth memory bank is available based on lapse of time since a most recent access of the fourth memory bank.
However, Dortu et al. teaches wherein ccess of read and write commands to the memory banks 20 and shadow memory banks 30 is effected internally by means of a control device 40 containing a state checking device 50 (see column 6, lines 40-43); and state checking device thus checks the memory bank state, in particular, by logging or detecting a time log since the time of the last read command for the memory bank to be checked and comparing said time log with the word line cycle time t.sub.RC. If the period of time which has elapsed is within the word line cycle time t.sub.RC, it is generally not possible to directly read the data which are to be read from the relevant memory bank, with the result that the "t.sub.RC condition" is not satisfied. Alternatively, it is possible for the active memory banks to generate a state signal which indicates that they are available for a read access operation (see column 4, lines 45-56).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Resnick and Harris er al. to include the above mentioned to achieve a shorter effective access time (see Dortu, column 3, lines 10-14).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Resnick (US2011/0099431) and Harris et al. (US6,601,151) as applied to claim 1 above, and further in view of Bolyn et al. (US5,920,898).
With respect claim 13, Resnick and Harris et al. do not teach wherein the system comprises a set of read requestors including a first read requestor and a second read requestor, and wherein the first read queue is capable of storing read requests associated exclusively with the first read requestor and the second read queue is capable of storing read requests associated exclusively with the second read requestor.
Bolyn et al. teaches wherein memory requests from a plurality of requestors are maintained in a corresponding plurality of memory request queue (see column 3, lines 59-61)… one memory request queue is provided for each requestor 302 that interfaces with the interface controller 328 (see column 9, lines 21-35 and column 11, lines 66-67).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Resnick and Harris er al. to include the above mentioned to optimizes the ordering of pending memory requests that originate from a plurality of requesters to best utilize the overlapping control sequence capabilities (see Bolyn, column 11, lines 22-25).
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Resnick (US2011/0099431) and Harris et al. (US6,601,151) as applied to claims 1 and 14 above, and further in view of Keil et al. (US2020/0065028).
With respect claim 17, Resnick teaches wherein the controller is capable of: determining that a read request is to access the fourth memory bank available (see Fig. 4 and paragraph 61-62; operation block 401 a next memory request is retrieved from the appropriate bank queue. The appropriate bank queue may be determined by using a round-robin scheme or a prioritized selection based on bank queue… process is currently in a read sequence, operation continues at decision block 404, which determines if the request is a read and if the requested bank is not busy (e.g., being activated or pre-charged) (i.e., it is determined if the memory bank to be accessed by the queue is available)).
Resnick and Harris et al. do not teach determining whether the first write queue is full; and based on that the first write queue is not full, scheduling the read request for execution before the first write request.
However, Keil et al. teaches wherein memory controller circuit 110 may continue to store received write requests into write request queue 140 until a number of queued write requests reaches a threshold number, as indicated by threshold 141. During this time, memory controller circuit 110 may continue to schedule and execute read requests. After the number of queued write requests reaches threshold 141, one or more of the queued write requests, such as, e.g., write requests 144-146, are scheduled by placing the write requests into scheduled request buffer 130 to be executed in a scheduled order (see paragraph 28).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Resnick and Harris et al. to include the above mentioned to achieve a specified memory access efficiency (see Keil, paragraph 4).
With respect claim 18, Resnick teaches wherein the controller is capable of: determining that a read request is to access the fourth memory bank (see Fig. 4 and paragraph 61-62; operation block 401 a next memory request is retrieved from the appropriate bank queue. The appropriate bank queue may be determined by using a round-robin scheme or a prioritized selection based on bank queue… process is currently in a read sequence, operation continues at decision block 404, which determines if the request is a read and if the requested bank is not busy (e.g., being activated or pre-charged) (i.e., it is determined if the memory bank to be accessed by the queue is available)).
Resnick and Harris et al. do not teach determining whether the first write queue is full; and based on that the first write queue is full, scheduling the first write request for execution before the read request.
However, Keil et al. teaches wherein memory controller circuit 110 may continue to store received write requests into write request queue 140 until a number of queued write requests reaches a threshold number, as indicated by threshold 141. During this time, memory controller circuit 110 may continue to schedule and execute read requests. After the number of queued write requests reaches threshold 141, one or more of the queued write requests, such as, e.g., write requests 144-146, are scheduled by placing the write requests into scheduled request buffer 130 to be executed in a scheduled order (see paragraph 28).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Resnick and Harris er al. to include the above mentioned to achieve a specified memory access efficiency (see Keil, paragraph 4).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Resnick (US2011/0099431) and Harris et al. (US6,601,151) as applied to claims 1, 14 and 19 above, and further in view of Venkatramani et al. (US8,285,914).
With respect claim 20, Resnick and Harris et al. do not teach wherein the controller is capable of: determining the availability of the fourth memory bank before the fifth memory bank based on determining that the first write queue includes more write requests than the second write queue.
Venkatramani et al. teaches determine one or more of the banks that are available, select one or more of the requests to send to the memory based on which of the one or more of the banks that are available and have a request to be serviced (see column 1, lines 49-54)… wherein a threshold may be set for bank queues 720. When the fullness of a bank queue 720 goes beyond the threshold, the corresponding bank 412 may be given a higher priority. For example, the bank priority vector (FIG. 10) associated with one or more of requestors 210 may be modified to give that bank 412 more accesses (see column 10, lies 14-21).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Resnick and Harris er al. to include the above mentioned to improve the delay through data processing device (see Venkatramani, column 11, lines 20-21).
Allowable Subject Matter
Claims 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: based on scheduling the first read request for execution, determining whether the first read request is at a front of the first read queue; and based on determining that the first read request is at the front of the first read queue, designating the second read queue as the priority read queue as recited in claim 10.
Harris et al. (US6,601,151) teaches a first and second read queues 30 and 80; wherein the first read queue 30 receives high priority read requests, the second read queue 80 receives low priority read requests (see column 11, lines 47-52).
However, Harris et al. does not teach based on scheduling the first read request for execution, determining whether the first read request is at a front of the first read queue; and based on determining that the first read request is at the front of the first read queue, designating the second read queue as the priority read queue as recited in claim 10.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al. (US6,507,886) teaches a scheduler for avoiding bank conflict in issuing concurrent requests to memory.
Calle et al. (US6,839,797) teaches bank queue for each bank in each channel keeps track of bank availability. When read or write requests are received at the tree memory controller, the controller checks the availability of each bank in a channel, identifies a first available bank, and executes the read request from the first available bank (see Abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARACELIS RUIZ whose telephone number is (571)270-1038. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G. Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ARACELIS RUIZ/Primary Examiner, Art Unit 2139
Prosecution Insights