NON-FINAL REJECTION
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-25 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-25 of U.S. Patent No. 12,360,902, 1-24 of U.S. Patent No. 11,720,496, and 1-24 of U.S. Patent No. 11,176,041. Although the claims at issue are not identical, they are not patentably distinct from each other as discussed below.
Regarding claim 1, U.S. Patent No. 12,360,902 discloses:
A method for cache coherency in a reconfigurable cache architecture, comprising:
determining at least one access parameter based on a memory access command comprising at least an address of a memory to access, wherein the at least one access parameter includes at least one of (claim 1: determining at least one access parameter based on the memory access command, wherein the at least one access parameter includes at least one of:):
a processing core ID, a thread ID, and a cache bit (claim 1: a processing core ID, a thread ID, and a cache bit); and
maintaining cache coherency by: computing a deterministic function over the at least one access parameter and the address to achieve cache coherency (claim 1: maintaining cache coherency by: computing a deterministic function over the at least one access parameter and the address to achieve cache coherency); and
determining a target cache bin for serving the memory access command based in part on an outcome of computing the deterministic function (claim 1: determining a target cache bin for serving the memory access command based in part on an outcome of computing the deterministic function).
Regarding claim 2, U.S. Patent No. 12,360,902 further discloses:
The method of claim 1, wherein the target cache bin is at least a portion of at least one cache node (claim 2: wherein the target cache bin is at least a portion of at least one cache node).
Regarding claim 3, U.S. Patent No. 12,360,902 further discloses:
The method of claim 1, wherein the reconfigurable cache architecture is distributed over a plurality of separate physical cache nodes, operating substantially independently and electrically coupled to the memory (claim 3: wherein the reconfigurable cache architecture is distributed over a plurality of separate physical cache nodes, operating substantially independently and electrically coupled to the memory);
wherein each cache node is partitionable into a plurality of cache bins; and wherein the target cache bin is one of the plurality of cache bins (claim 3: wherein each cache node is partitionable into a plurality of cache bins; and wherein the target cache bin is one of the plurality of cache bins).
Regarding claim 4, U.S. Patent No. 12,360,902 further discloses:
The method of claim 1, wherein the reconfigurable cache architecture is distributed over a plurality of separate physical cache nodes, operating substantially independently and electrically coupled to the memory (claim 4: wherein the reconfigurable cache architecture is distributed over a plurality of separate physical cache nodes, operating substantially independently and electrically coupled to the memory);
wherein each cache node is partitionable into a plurality of cache bins; and wherein each cache bin is included in a respective cache node of the plurality of separate physical cache nodes (claim 4: wherein each cache bin is included in a respective cache node of the plurality of separate physical cache nodes).
Regarding claim 5, U.S. Patent No. 12,360,902 further discloses:
The method of claim 3, further comprising:
dynamically partitioning each cache node into at least two cache bins based on utilization of the respective plurality of cache bins of the cache node (claim 5: dynamically partitioning each cache node into at least two cache bins based on utilization of the respective plurality of cache bins of the cache node).
Regarding claim 6, U.S. Patent No. 12,360,902 further discloses:
The method of claim 5, further comprising:
initially partitioning each cache node into a predetermined number of cache bins (claim 6: initially partitioning each cache node into a predetermined number of cache bins);
collecting statistics with respect to the usage of each cache bin (claim 6: collecting statistics with respect to the usage of each cache bin); and
reconfiguring the initial partitioning of each cache node based on the collected statistics (claim 6: reconfiguring the initial partitioning of each cache node based on the collected statistics).
Regarding claim 7, U.S. Patent No. 12,360,902 further discloses:
The method of claim 6, wherein reconfiguring of the partitioning of each cache node is performed after each execution iteration (claim 7: wherein the reconfiguration of the partitioning of each cache node is performed after each execution iteration).
Regarding claim 8, U.S. Patent No. 12,360,902 further discloses:
The method of claim 6, further comprising:
dynamically allocating more cache storage to at least one of the cache bins (claim 8: dynamically allocating more cache storage to at least one of the cache bins).
Regarding claim 9, U.S. Patent No. 12,360,902 further discloses:
The method of claim 1, wherein the memory access command includes a unitary identification of any one of:
a physical entity and a logical entity (claim 9: wherein the memory access command includes a unitary identification of any one of: a physical entity and a logical entity).
Regarding claim 10, U.S. Patent No. 12,360,902 further discloses:
The method of claim 9, wherein the physical entity is any one of:
a processing core, and a shared portion of the memory (claim 10: wherein the physical entity is any one of: a processing core, and a shared portion of the memory).
Regarding claim 11, U.S. Patent No. 12,360,902 further discloses:
The method of claim 9, wherein the logical entity is any one of:
a process and a thread (claim 11: wherein the logical entity is any one of: a process and a thread).
Regarding claim 12, U.S. Patent No. 12,360,902 further discloses:
The method of claim 9, wherein determining the at least one access parameter further comprises:
determining if the memory access command is associated with the logical entity (claim 12: wherein determining the at least one access parameter further comprises: determining if the memory access command is associated with the logical entity); and
setting the access parameter as a logical entity identifier when it is determined that the memory access command is associated with the logical entity (claim 12: setting the access parameter as a logical entity identifier when it is determined that the memory access command is associated with the logical entity).
Regarding claim 13, U.S. Patent No. 12,360,902 further discloses:
The method of claim 9, wherein determining the at least one access parameter further comprises:
determining if the memory access command is associated with the physical entity (claim 13: wherein determining the at least one access parameter further comprises: determining if the memory access command is associated with the physical entity); and
setting the access parameter as a physical entity identifier when it is determined that the memory access command is associated with the physical entity (claim 13: setting the access parameter as a physical entity identifier when it is determined that the memory access command is associated with the physical entity).
Regarding claim 14, U.S. Patent No. 12,360,902 further discloses:
The method of claim 12, further comprising:
determining at least one cache attribute, wherein the at least one cache attribute includes at least one of (claim 14: determining at least one cache attribute, wherein the at least one cache attribute includes at least one of:):
a never cache certain value, an always cache certain value, or an always check certain value (claim 14: a never cache certain value, an always cache certain value, or an always check certain value).
Regarding claim 15, U.S. Patent No. 12,360,902 further discloses:
The method of claim 3, wherein the reconfigurable cache architecture is utilized to accelerate an execution of a program by a processing circuitry (claim 15: wherein the reconfigurable cache architecture is utilized to accelerate an execution of a program by a processing circuitry).
Claims 18-25 recite limitations similar to those of claims 1-17. Therefore claims 18-25 are rejected under the same rationale as claims 1-17.
The claims of the instant application are not patentably distinct from the claims of U.S. Patent No. 11,720,496 and U.S. Patent No. 11,176,041. For example, claim 1 of the instant application is not patentably distinct from claim 1 of US Patent No. 11,720,496 or from claim 1 of U.S. Patent No. 11,176,041. Claim 1 of the instant application therefore is not patently distinct from claim 1 of the US Patent No. 11,720,496 or from claim 1 of U.S. Patent No. 11,176,041 and is unpatentable for obvious-type double patenting. Claims 2-25 of the instant application corresponds to various limitations as recited in claims 2-24 of US Patent No. 11,720,496 and claims 2-24 of U.S. Patent No. 11,176,041, and are rejected on the ground of nonstatutory obviousness-type double patenting on the same rationale as claim 1 above.
Allowable Subject Matter
Claims 1-25 are allowable over the prior art.
While one or more reasons are offered below citing reasons that the claims are allowable over the prior art, it is each claim taken as a whole, including interrelationships and interconnections between various claimed elements, which are allowable over the prior art of record and not any individual limitation of a claim. The prior art of Niu et al. (US 2016/0140041) and Williamson et al. (US 2006/0236074), when taken alone or in combination with each other, fail to anticipate and/or make obvious to one of ordinary skill in the art the claimed invention prior to the effective filing date.
Regarding claim 1, the prior art, alone or in combination, does not disclose the following limitations, as claimed, in combination with the other claimed limitations:
“A method for cache coherency in a reconfigurable cache architecture, comprising: determining at least one access parameter based on a memory access command comprising at least an address of a memory to access, wherein the at least one access parameter includes at least one of: a processing core ID, a thread ID, and a cache bit; and maintaining cache coherency by: computing a deterministic function over the at least one access parameter and the address to achieve cache coherency; and determining a target cache bin for serving the memory access command based in part on an outcome of computing the deterministic function.”
Regarding claim 18, the prior art, alone or in combination, does not disclose the following limitations, as claimed, in combination with the other claimed limitations:
“A non-transitory computer readable medium having stored thereon instructions for causing at least one processing circuitry to execute a process for cache coherency in a reconfigurable cache architecture, the process comprising: determining at least one access parameter based on a memory access command comprising at least an address of a memory to access, wherein the at least one access parameter includes at least one of: a processing core ID, a thread ID, and a cache bit; and maintaining cache coherency by: computing a deterministic function over the at least one access parameter and the address to achieve cache coherency; and determining a target cache bin for serving the memory access command based in part on an outcome of computing the deterministic function.”
Regarding claim 19, the prior art, alone or in combination, does not disclose the following limitations, as claimed, in combination with the other claimed limitations:
“A system for cache coherency, comprising: a memory; at least one processing circuitry connected to the memory and configured to: determine at least one access parameter based on a memory access command comprising at least an address of a memory to access, wherein the at least one access parameter includes at least one of: a processing core ID, a thread ID, and a cache bit; and maintain cache coherency by: computing a deterministic function over the at least one access parameter and the address to achieve cache coherency; and determining a target cache bin for serving the memory access command based in part on an outcome of computing the deterministic function.”
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Conclusion
The prior art made of record and not relied upon, Bamford et al. (US 2004/0215883) and Jeddeloh (US 2002/0133673), is considered pertinent to applicant's disclosure because the disclose caching data.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY A WARREN whose telephone number is (571)270-7288. The examiner can normally be reached M-Th 7:30am-5pm, Alternate F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P. Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TRACY A WARREN/Primary Examiner, Art Unit 2137
Prosecution Insights