Prosecution Insights
Last updated: October 01, 2026
Application No. 19/264,390

THREAT ANALYSIS SYSTEM AND THREAT ANALYSIS METHOD

Non-Final OA §101
Filed
Jul 09, 2025
Priority
Jul 24, 2024 — JP 2024-118957
Examiner
LE, THANH T
Art Unit
2495
Tech Center
2400 — Computer Networks
Assignee
Panasonic Holdings Corporation
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
1y 4m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
205 granted / 247 resolved
+25.0% vs TC avg
Strong +33% interview lift
Without
With
+32.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
11 currently pending
Career history
260
Total Applications
across all art units

Statute-Specific Performance

§101
10.2%
-29.8% vs TC avg
§103
58.3%
+18.3% vs TC avg
§102
7.1%
-32.9% vs TC avg
§112
20.5%
-19.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 247 resolved cases

Office Action

§101
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of Claims 2. This Office Action is issued in response to the claims filed on 07/09/2025. Claims 1-8 are pending in this Office Action. Priority 3. Acknowledgement is made of Applicant’s priority claim of Japanese Patent Application No. 2024-118957 filed on July 24, 2024. Information Disclosure Statement 4. The information disclosure statement (IDS) filed on 10/09/2025 has been considered by the Examiner. Claim Rejections - 35 USC § 101 5. 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. 6. Claims 1-8 are rejected under 35 U.S.C. 101. a. Claim 1 is rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract ideas without significantly more. Step 2A, Prong 1: The claim recites “obtains …; analyzes …; generates…; and outputs…” These limitations, as drafted, under their broadest reasonable interpretations cover performance of the limitations in the mind or on paper. For example, the limitation “obtains design information on design of the analysis target system” under its broadest reasonable interpretation, covers performance of the limitation in the mind or on paper. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or on paper, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites abstract ideas. Step 2A, Prong 2: This judicial exception is not integrated into a practical application because the claims do not recite any application of the limitations besides abstract ideas. Therefore, the claim is directed to abstract ideas. Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because besides the abstract ideas, additional elements ‘memory’ and ‘processor’ are recited at a high level of generality with no more than mere instructions to apply the exception using generic computer components. Therefore, the claim is not patent eligible. Claims 2-7 depends on claim 1 and they do not limit independent claim 1 or themselves to a practical application or amount to significantly more than the judicial exception; therefore, claims 2-7 are also not patent eligible. Similar to claim 1, claim 8 is not patent eligible. Allowable Subject Matter 7. Claims 1-8 are allowable over prior art and would be allowable if rewritten to overcome the rejections under 35 USC § 101 set forth in this Office action. The following is an examiner’s statement of reasons for allowance: Regarding independent claims 1 and 8: a. Wada et al. (US 20240193273 A1) discloses a threat analysis method includes acquiring system configuration information indicating hardware components of a system for which threat analysis is performed, function allocation information indicating functions allocated to the hardware components, an asset information indicating assets used in each function, and asset input/output information indicating hardware components of input/output sources and input/output destination of the asset; deriving a physical data flow that indicates a flow of the asset corresponding to each hardware component and a logical data flow that indicates a flow of the asset corresponding to each function in accordance with the acquired information and analyzing a likelihood of an attack on the asset and an impact of the attack on the asset for each of the hardware components and each of the functions in accordance with the physical data flow and the logical data flow; and outputting a result of the analysis (Fig.7 with associated text). b. Mizushima et al. (US 2024/0281540 A1) discloses a configuration information acquisition means acquires configuration information of a system to be analyzed. A threat analysis means analyzes a way of attack that can be implemented in the system to be analyzed. An attack route generation means generates an attack route from the start point to the end point of the attack. A risk value calculation means calculates a risk value of the generated attack route. A result output means outputs a risk analysis result containing the calculated risk value. A risk re-analysis means causes re-analysis of risks for the system in which a security measure planned for the system is introduced to be performed from any one of the configuration information acquisition means, the threat analysis means, the attack route generation means, and the risk value calculation means to conduct re-analysis of risks depending on the security measure planned for the system (Figs.1 and 4 with associated text). c. Koteshwara et al. (US 20240070288 A1) discloses a method comprising identifying hardware and software components of a system architecture, and generating a multi-layered graph based on the hardware and software components. The multi-layered graph includes a hardware layer representing a lowest level of hardware architecture of the system architecture. The method further comprises extracting one or more properties of the multi-layered graph, computing one or more security metrics based on the one or more properties, and quantifying a security risk of the system architecture based on the one or more security metrics (Fig.1 with associated text). The prior arts of record fail to either disclose or sufficiently suggest the combination features as claimed and arranged by applicant. Although the above references teach similar aspects of the independent claims 1 and 8, none of these references individually or in reasonable combination discloses all the limitations as claimed in the independent claims and each of these independent claims as a whole is not obvious over these prior arts. Therefore, independent claims 1 and 8 are allowable over the prior arts of record and dependent claims are allowable by virtue of their dependence on the independent claims. Prior Art of Record 8. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure: see attached PTO-892 Notice of References Cited. Conclusion 9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH T. LE whose telephone number is (571)270-0279. The examiner can normally be reached on Monday-Friday 8:00 am - 4:30 pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Farid Homayounmehr can be reached on 571-272-3739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THANH T LE/Primary Examiner, Art Unit 2495
Read full office action

Prosecution Timeline

Jul 09, 2025
Application Filed
Aug 11, 2026
Non-Final Rejection mailed — §101
Sep 08, 2026
Interview Requested
Sep 16, 2026
Examiner Interview Summary
Sep 16, 2026
Applicant Interview (Telephonic)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
99%
With Interview (+32.8%)
2y 7m (~1y 4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 247 resolved cases by this examiner. Grant probability derived from career allowance rate.

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