DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/09/2025, 11/26/2025, 12/29/2025 and 05/07/2026 is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
In page 1, paragraph 1, where it says “Application No. 17/955,014, filed September…” should be --Application No. 17/955,014, now U.S. Patent No. 12,386,557, filed September--.
Appropriate correction is required.
Claim Objections
Claims 7 and 17 are objected to because of the following informalities:
In claim 7, line 1, where it says “comprises on of a CMB address” should be --comprises one of a CMB address--.
In claim 17, line 1, where it says “comprises on of a CMB address” should be --comprises one of a CMB address--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5, 11 and 15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Muthiah et al. (US 12,008,251).
With respect to claim 1, Muthiah et al. teaches receiving from a host, by a first non-volatile memory device of a plurality of non-volatile memory devices, a host command comprising device information for accessing each of the plurality of non-volatile memory devices (see column 6, lines 51-53; column 10, lines 66-67 and column 11, lines 1-15; storage devices 120 include a plurality of media devices 140, such as flash memory devices… during a write operation initiated by a host 102, storage system 100 receives a host write command (e.g., in a set of one or more host write commands) via interface 112 and directs the host write command to data storage device 120.1 (configured as master storage device 204) via interconnect fabric 114 (see FIG. 1). Storage device 120.1 receives the host write command through interconnect fabric interface 301 and directs the command to peer rate leveler 322 for processing… The host write command may include one or more host data units and indicate one or more storage locations by host logical block address (i.e. information for memories to be accessed));
identifying, by the first non-volatile memory device, a plurality of divided portions of host data corresponding to the host command (see column 11, lines 12-25; Peer rate leveler 322 may divide the host data unit into data blocks for data striping, allocate the data blocks among the peer storage devices, and send the data units in peer write commands to the target peer storage devices);
transferring, by the first non-volatile memory device to each of the plurality of non- volatile memory devices other than the first non-volatile memory device and using the device information in the host command, a respective one of the plurality of divided portions of the host data (see column 11, lines 12-35 and column 12, 21-32; storage device 120.1 may manage the set of host logical block addresses corresponding to the aggregate storage locations of all of the peer group (e.g., the storage media locations in storage devices 120.2-120.n). Peer rate leveler 322 may divide the host data unit into data blocks for data striping, allocate the data blocks among the peer storage devices, and send the data units in peer write commands to the target peer storage devices (i.e., data is transferred to non-volatile memories)).
With respect to claim 5, Muthiah et al. teaches wherein the device information comprises priority information for processing the host data corresponding to the host command (see column 18, lines 34-42; storage command handler 336 may parse the received storage commands to determine command parameters and/or identify or locate corresponding host data units for write commands. In some embodiments, storage command handler 336 may place incoming storage commands in one or more command queues 306.2, such as host command queues or peer command queues, and process them based on queue order and/or priority).
With respect to claim 11, Muthiah et al. teaches a plurality of non-volatile memory devices including a first non-volatile memory device comprising a non-volatile memory and a controller (see Fig. 1 and column 4, lines 63-67 and column 5, lines 1-2; data storage devices 120 are, or include, solid-state drives (SSDs). Each data storage device 120.1-120.n may include a non-volatile memory (NVM) or device controller 130 based on compute resources (processor and memory) and a plurality of NVM or media devices 140 for data storage (e.g., one or more NVM device(s), such as one or more flash memory devices)), wherein the controller is configured to:
receive from a host, a host command comprising device information for accessing each of the plurality of non-volatile memory devices (see column 6, lines 51-53; column 10, lines 66-67 and column 11, lines 1-15; storage devices 120 include a plurality of media devices 140, such as flash memory devices… during a write operation initiated by a host 102, storage system 100 receives a host write command (e.g., in a set of one or more host write commands) via interface 112 and directs the host write command to data storage device 120.1 (configured as master storage device 204) via interconnect fabric 114 (see FIG. 1). Storage device 120.1 receives the host write command through interconnect fabric interface 301 and directs the command to peer rate leveler 322 for processing… The host write command may include one or more host data units and indicate one or more storage locations by host logical block address (i.e. information for memories to be accessed));
identify a plurality of divided portions of host data corresponding to the host command (see column 11, lines 12-25; Peer rate leveler 322 may divide the host data unit into data blocks for data striping, allocate the data blocks among the peer storage devices, and send the data units in peer write commands to the target peer storage devices);
transfer, to each of the plurality of non-volatile memory devices other than the first non-volatile memory device and using the device information in the host command, a respective one of the plurality of divided portions of the host data (see column 11, lines 12-35 and column 12, 21-32; storage device 120.1 may manage the set of host logical block addresses corresponding to the aggregate storage locations of all of the peer group (e.g., the storage media locations in storage devices 120.2-120.n). Peer rate leveler 322 may divide the host data unit into data blocks for data striping, allocate the data blocks among the peer storage devices, and send the data units in peer write commands to the target peer storage devices (i.e., data is transferred to non-volatile memories)).
With respect to claim 15, Muthiah et al. teaches wherein the device information comprises priority information for processing the host data corresponding to the host command (see column 18, lines 34-42; storage command handler 336 may parse the received storage commands to determine command parameters and/or identify or locate corresponding host data units for write commands. In some embodiments, storage command handler 336 may place incoming storage commands in one or more command queues 306.2, such as host command queues or peer command queues, and process them based on queue order and/or priority).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4 and 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muthiah et al. (US 12,008,251) in view of Jogand-Coulomb et al. (US 8,452,934).
With respect to claim 2, Muthiah et al. does not teach wherein the device information includes permission information of at least one of the plurality of non-volatile memory devices other than the first non-volatile memory device.
However, Jogand-Coulomb et al. teaches wherein the device information includes permission information of at least one of the plurality of non-volatile memory devices (see column 13, lines 13-20; authentication data is received from a host device. For example, the host device may be the host device 204 depicted in FIGS. 2-3. The authentication data may include one or more credentials or other information to be evaluated to determine authorization to access protected content at a memory device).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Muthiah et al. to include the above mentioned to improve performance of the device by controlling access of the memory device (see Jogand-Coulomb, column 2, lines 16-21).
With respect to claim 3, Jogand-Coulomb et al. does not teach wherein the permission information comprises one or more types of operations for which the at least one non-volatile memory device is permitted to be accessed by the first non-volatile memory device.
However, Jogand-Coulomb et al. teaches wherein the permission information comprises one or more types of operations for which the at least one non-volatile memory device is permitted to be accessed by the first non-volatile memory device (see column 13, lines 27-41; a first request is received from the host device to write data to a non-volatile memory device. The non-volatile memory device includes a directory table having a first write protected portion and also includes a file allocation table (FAT) having a second write protected portion).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Muthiah et al. to include the above mentioned to improve performance of the device by controlling access of the memory device (see Jogand-Coulomb, column 2, lines 16-21).
With respect to claim 4, Muthiah et al. does not teach wherein the permission information comprises authentication credentials for accessing the at least one non-volatile memory device.
However, Jogand-Coulomb et al. teaches wherein the permission information comprises authentication credentials for accessing the at least one non-volatile memory device (see column 13, lines 13-20; authentication data may include one or more credentials or other information to be evaluated to determine authorization to access protected content at a memory device).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Muthiah et al. to include the above mentioned to improve performance of the device by controlling access of the memory device (see Jogand-Coulomb, column 2, lines 16-21).
With respect to claim 12, Muthiah et al. does not teach wherein the device information includes permission information of at least one of the plurality of non-volatile memory devices other than the first non-volatile memory device.
However, Jogand-Coulomb et al. teaches wherein the device information includes permission information of at least one of the plurality of non-volatile memory devices (see column 13, lines 13-20; authentication data is received from a host device. For example, the host device may be the host device 204 depicted in FIGS. 2-3. The authentication data may include one or more credentials or other information to be evaluated to determine authorization to access protected content at a memory device).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Muthiah et al. to include the above mentioned to improve performance of the device by controlling access of the memory device (see Jogand-Coulomb, column 2, lines 16-21).
With respect to claim 13, Muthiah et al. does not teach wherein the permission information comprises one or more types of operations for which the at least one non-volatile memory device is permitted to be accessed by the first non-volatile memory device.
However, Jogand-Coulomb et al. teaches wherein the permission information comprises one or more types of operations for which the at least one non-volatile memory device is permitted to be accessed by the first non-volatile memory device (see column 13, lines 27-41; a first request is received from the host device to write data to a non-volatile memory device. The non-volatile memory device includes a directory table having a first write protected portion and also includes a file allocation table (FAT) having a second write protected portion).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Muthiah et al. to include the above mentioned to improve performance of the device by controlling access of the memory device (see Jogand-Coulomb, column 2, lines 16-21).
With respect to claim 14, Muthiah et al. does not teach wherein the permission information comprises authentication credentials for accessing the at least one non-volatile memory device.
However, Jogand-Coulomb et al. teaches wherein the permission information comprises authentication credentials for accessing the at least one non-volatile memory device (see column 13, lines 13-20; authentication data may include one or more credentials or other information to be evaluated to determine authorization to access protected content at a memory device).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Muthiah et al. to include the above mentioned to improve performance of the device by controlling access of the memory device (see Jogand-Coulomb, column 2, lines 16-21).
Claim(s) 6-7 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muthiah et al. (US 12,008,251) in view of Moss et al. (US 11,157,212).
With respect to claim 6, Muthiah et al. does not teach wherein the device information comprises an address of a buffer of the host containing the host data.
However, Moss et al. teaches wherein the device information comprises an address of a buffer of the host containing the host data (see column 6, lines 56-64; host 172 implements a controller memory buffer (CMB) 180 as an allocated portion of the local memory 178 for its own use… The controller places the contents in the CMB at the designated addresses (i.e., buffer address)).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Muthiah et al. to include the above mentioned to facilitate enhanced operation of the system (see Moss, column 2, lines 48-54).
With respect to claim 7, Muthiah et al. does not teach wherein the address comprises on of a CMB address, a SLM address and a PMR address.
However, Moss et al. teaches wherein the device information comprises an address of a buffer of the host containing the host data (see column 6, lines 56-64; host 172 implements a controller memory buffer (CMB) 180 as an allocated portion of the local memory 178 for its own use… The controller places the contents in the CMB at the designated addresses (i.e., CMB address)).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Muthiah et al. to include the above mentioned to facilitate enhanced operation of the system (see Moss, column 2, lines 48-54).
With respect to claim 16, Muthiah et al. does not teach wherein the device information comprises an address of a buffer of the host containing the host data.
However, Moss et al. teaches wherein the device information comprises an address of a buffer of the host containing the host data (see column 6, lines 56-64; host 172 implements a controller memory buffer (CMB) 180 as an allocated portion of the local memory 178 for its own use… The controller places the contents in the CMB at the designated addresses (i.e., buffer address)).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Muthiah et al. to include the above mentioned to facilitate enhanced operation of the system (see Moss, column 2, lines 48-54).
With respect to claim 17, Muthiah et al. does not teach wherein the address comprises on of a CMB address, a SLM address and a PMR address.
However, Moss et al. teaches wherein the device information comprises an address of a buffer of the host containing the host data (see column 6, lines 56-64; host 172 implements a controller memory buffer (CMB) 180 as an allocated portion of the local memory 178 for its own use… The controller places the contents in the CMB at the designated addresses (i.e., CMB address)).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Muthiah et al. to include the above mentioned to facilitate enhanced operation of the system (see Moss, column 2, lines 48-54).
Claim(s) 8 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muthiah et al. (US 12,008,251) and Moss et al. (US 11,157,212).as applied to claims 1, 6, 11 and 16 above, and further in view of Hahn et al. (US 11,561,909).
With respect to claim 8, Muthiah et al. and Moss et al. do not teach wherein transferring comprises performing a DMA transfer between the buffer of the host and buffers in the other of the plurality of non-volatile memory devices.
However, Hahn et al. teaches wherein transferring comprises performing a DMA transfer between the buffer of the host and buffers in the other of the plurality of non-volatile memory devices (see column 4, lines 49-55; data buffers 124a may be used to store data to be written to non-volatile memory 104 or to store data that was read from non-volatile memory 104. The memory controller 102 may perform a DMA of data from data buffers 124a when writing data to non-volatile memory 104. The memory controller 102 may perform a DMA of data to data buffers 124a when reading data from non-volatile memory 104).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Muthiah et al. and Moss et al. to include the above mentioned to improve efficiency (see Hahn, column 24, lines 53-61).
With respect to claim 18, Muthiah et al. and Moss et al. do not teach wherein transferring comprises performing a DMA transfer between the buffer of the host and buffers in the other of the plurality of non-volatile memory devices.
However, Hahn et al. teaches wherein transferring comprises performing a DMA transfer between the buffer of the host and buffers in the other of the plurality of non-volatile memory devices (see column 4, lines 49-55; data buffers 124a may be used to store data to be written to non-volatile memory 104 or to store data that was read from non-volatile memory 104. The memory controller 102 may perform a DMA of data from data buffers 124a when writing data to non-volatile memory 104. The memory controller 102 may perform a DMA of data to data buffers 124a when reading data from non-volatile memory 104).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Muthiah et al. and Moss et al. to include the above mentioned to include the above mentioned to improve efficiency (see Hahn, column 24, lines 53-61).
Claim(s) 9-10 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muthiah et al. (US 12,008,251) in view of Haimzon et al. (US 11,698,881).
With respect to claim 9, Muthiah et al. does not teach wherein the plurality of divided portions of the host data collectively comprise a stripe of data in a RAID storage.
However, Haimzon et al. teaches wherein the plurality of divided portions of the host data collectively comprise a stripe of data in a RAID storage (see column 8, lines 40-47; where each Ethernet enabled SSD corresponds to a “disk” of the RAID and each Ethernet enabled SSD has a copy of the same data… the one Ethernet enabled SSD may copy the data to another Ethernet enabled SSDs over the connection 138 to form the RAID).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Muthiah et al. and Moss et al. to include the above mentioned to improve performance of the device by reducing an amount of data transferred between the SSDs and the host and/or reducing processing by the host (see Haimzon, column 3, lines 63-67 and column 4, lines 1-3).
With respect to claim 10, Muthiah et al. does not teach wherein transferring is performed using a NVMeOF protocol.
However, Haimzon et al. teaches wherein transferring is performed using a NVMeOF protocol (see column 2, lines 25-32 and column 11, lines 10-28; connection between the first SSD and the second SSD over the network fabric, wherein the first SSD is communicatively coupled to the second SSD further over an interconnect associated with a host computer; based on a non-volatile memory over fabric (NVMe-oF) communication protocol).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Muthiah et al. and Moss et al. to include the above mentioned to improve performance of the device by reducing an amount of data transferred between the SSDs and the host and/or reducing processing by the host (see Haimzon, column 3, lines 63-67 and column 4, lines 1-3).
With respect to claim 19, Muthiah et al. does not teach wherein the plurality of divided portions of the host data collectively comprise a stripe of data in a RAID storage.
However, Haimzon et al. teaches wherein the plurality of divided portions of the host data collectively comprise a stripe of data in a RAID storage (see column 8, lines 40-47; where each Ethernet enabled SSD corresponds to a “disk” of the RAID and each Ethernet enabled SSD has a copy of the same data… the one Ethernet enabled SSD may copy the data to another Ethernet enabled SSDs over the connection 138 to form the RAID).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Muthiah et al. and Moss et al. to include the above mentioned to improve performance of the device by reducing an amount of data transferred between the SSDs and the host and/or reducing processing by the host (see Haimzon, column 3, lines 63-67 and column 4, lines 1-3).
With respect to claim 20, Muthiah et al. does not teach wherein transferring is performed using a NVMeOF protocol.
However, Haimzon et al. teaches wherein transferring is performed using a NVMeOF protocol (see column 2, lines 25-32 and column 11, lines 10-28; connection between the first SSD and the second SSD over the network fabric, wherein the first SSD is communicatively coupled to the second SSD further over an interconnect associated with a host computer; based on a non-volatile memory over fabric (NVMe-oF) communication protocol).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Muthiah et al. and Moss et al. to include the above mentioned to improve performance of the device by reducing an amount of data transferred between the SSDs and the host and/or reducing processing by the host (see Haimzon, column 3, lines 63-67 and column 4, lines 1-3).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al. (US2022/0083267) teaches high bandwidth controller memory buffer for peer to peer data transfer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARACELIS RUIZ whose telephone number is (571)270-1038. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G. Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ARACELIS RUIZ/Primary Examiner, Art Unit 2139
Prosecution Insights