DETAILED ACTION
This office action is in response to an Amendment/Request for Reconsideration filed 8/12/2026 for application 19/264,468 filed 7/9/2025 that claims priority to 18/538,448 and provisional application 63/432,322.
Claims 1-2, 11, and 20 have been amended. No claims have been cancelled. No claims are new. Thus Claims 1-20 have been examined.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4, and 6-10 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6-9, and 11-12 of U.S. Patent No.12,373,107. Although the claims at issue are not identical, they are not patentably distinct from each other as a comparison of the claims show the limitations of the claims of the instant application shown in the first column are found in the listed claims of U.S. Patent No. 12,373,107 as shown in the second column shown below:
19/264,468
12,373,107
1.
A system comprising:
1.
A computer system
a processor device; and
for executing a program on a processor
a compiler configured to translate a program into a deterministic schedule comprising a set of scheduled instructions for execution on the processor device, the set of scheduled instructions comprising:
a compiler for generating an explicit plan for how the processor will execute the program by specifying a deterministic schedule
at least one first instruction, the at least one first instruction configured to implement a non-deterministic operation; and
9.
issuing read/write requests to the DRAM
at least one second instructions to cause a memory maintenance operation, wherein the at least one second instruction is scheduled based on a known duration to complete the memory maintenance operation and a worst case time to complete the non-deterministic operation
to prevent interference with the at least one first instruction
13.
12.
9.
Wherein a pre-determined refresh/maintenance window is used by the compiler when it compiles the program.
Wherein a predetermined worst case memory of each memory channel delay is used by the compiler when it compiles the program.
wherein the system uses the deterministic schedule to determine when to stop issuing read/write requests to the DRAM to ensure that a refresh or maintenance cycle does not start before the response of an issued request can be returned.
2.
3.
Wherein the compiler accounts for the worst case time to complete the non-deterministic operation when translating the program into the deterministic schedule.
wherein the at least one first instruction is to cause memory access by the processor device during execution of the program
12.
9.
Wherein a predetermined worst case memory of each memory channel delay is used by the compiler when it compiles the program.
Issuing read/write requests to the DRAM
4.
wherein the memory maintenance operation comprises a memory refresh operation
9.
ensure that a refresh or maintenance cycle does not start before the response of an issued request can be returned
6.
wherein the plurality of memory banks comprise dynamic random access memory (DRAM)
7.
refresh all the banks
6.
wherein the external memory I a DRAM
7.
the system further comprises a plurality of memory banks; and
7.
refresh all the banks
the at least one second instruction is to cause the memory maintenance operation at a first time on a first subset of the plurality of memory banks
1.
a compiler for generating an explicit plan for how the processor will execute the program by specifying a deterministic schedule
8.
wherein the at least one first instruction is to cause memory access to a memory bank of a second subset of the plurality of memory banks during the memory maintenance operation of the first subset of the plurality of memory banks.
7.
periodically refresh all the banks simultaneously wherein each all-bank refresh and maintenance cycle is included in the deterministic schedule
9.
wherein the set of scheduled instructions further comprises at least one third instruction to cause a second memory maintenance operation at a second time on a second subset of the plurality of memory banks.
7.
periodically refresh all the banks simultaneously wherein each all-bank refresh and maintenance cycle is included in the deterministic schedule
10.
wherein the compiler is configured to: determine a response return time associated with the at least one first instruction; determine a request window for scheduling the memory maintenance operation associated with the at least one second instruction; and schedule the at least one first instruction and the at least one second instruction based on the response return time and the request window.
7.
further comprising a DRAM controller that uses the "all-bank" method to periodically refresh all the banks simultaneously wherein each all-bank refresh and maintenance cycle is included in the deterministic schedule.
8.
wherein the system issues read/write requests for execution during a request window.
Please note that MPEP § 804 states: “A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional. As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Shah (Shah et al., US 2021/0312320 A1) and further in view of Querbach (QUERBACH et al., US 2017/0352406 A1).
Regarding claim 1, Shah teaches A system comprising: a processor device; (Sha Fig. 9 and [0075] discloses a SOC that implements the inventive concepts that includes MLA 970. Sha [0021] discloses a machine learning accelerator (MLA) contains processing elements.) and a compiler configured to translate a program into a deterministic schedule comprising a set of scheduled instructions for execution on the processor device, (Shah Fig. 1 and [0021] discloses the system contains a compiler 120 that takes a machine learning network 100 (a program) that generates program 150 that is a set of instructions that are executed by processing elements in the MLA according to a schedule determined by the compiler (i.e. statically scheduled instructions what knows how long it takes to execute each instruction), thus produces a deterministic schedule.)
the set of scheduled instructions comprising: at least one first instruction, the at least one first instruction configured to implement a non-deterministic operation; (Shah [0027] discloses that the program 150 may contain non-deterministic phases 154X,Y, that may be data fetch of instructions from off-chip memory.)
and at least one second instruction …(Shah Fig. 1B and [0026] that shows there may be a deterministic phase 152B that executes instructions whose time required for each computation is known. ),
wherein the at least one second instruction is scheduled based on a known duration to complete the memory maintenance operation (Shah Fig 1B and [0026-[0028] discloses the compiler identifies the amount of time required for the deterministic phase 152B that is a fixed duration and an example of a request window for schedule deterministic/second operations.) and a worst case time to complete the non-deterministic operation. (Shah [0028] discloses that the deterministic phase begins when all of the tiles have signal they have completed their non-deterministic instructions. Thus the deterministic operations are scheduled by the compiler when all non-deterministic operations have completed, thus taking into account the maximum time required for all non-deterministic operations (i.e. the worst case time for non-deterministic operations).)
to prevent interference with the at least one first instruction. (Shah Fig. 5B and [0060] discloses that the deterministic/second instructions are performed after the non-deterministic/first instructions, thus the deterministic/second instructions does not interfere with the scheduling of non-deterministic/first instructions.)
However, Shah does not explicitly disclose one second instruction to cause a memory maintenance operation.. based on a known duration to complete the memory maintenance operation.
Querbach, of a similar field of endeavor, further teaches one second instruction to cause a memory maintenance operation, based on a known duration to complete the memory maintenance operation… (Querbach [Abstract], [0017], and [0020] discloses that the system has deterministic control over both when to start a refresh command and when it will be done. Thus the deterministic phase of Shah may execute a refresh operation that is an example of a maintenance operation.)
Shah and Querbach are in a similar field of endeavor, as both relate to schedule operations at a DRAM memory. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention having Shah and Querbach before them to incorporate the deterministic scheduling of refresh operations to a DRAM memory as detailed in Querbach that supports DRAM memory and seeks to deterministically schedule memory operations as taught by Shah. Thus combining prior art elements according to known methods to yield predictable results (enable the controller to precisely control the timing of operations executed by memory devices and control the maximum time a memory is unavailable for routine operations such as read or writes to the memory.).
The motivation to combine Querbach into Shah for claims 2-20 are the same as those set forth in claim 1 above.
Regarding claim 2, the combination of Shah and Querbach teaches all of the limitations of claim 1 above. Shah further teaches wherein the compiler accounts for a worst case time to complete the non-deterministic operation when translating the program into the deterministic schedule. (Shah [0028] discloses that the deterministic phase begins when all of the tiles have signal they have completed their non-deterministic instructions. Thus the deterministic operations are scheduled by the compiler when all non-deterministic operations have completed, thus taking into account the maximum time required for all non-deterministic operations (i.e. the worst case time for non-deterministic operations).)
Regarding claim 3, the combination of Shah and Querbach teaches all of the limitations of claim 1 above. Shah further teaches wherein the at least one first instruction is to cause memory access by the processor device during execution of the program. (Shah Fig. 1 and [0021] discloses the system contains a compiler 120 that takes a machine learning network 100 (a program) that generates program 150 that is a set of instructions that are executed by processing elements in the MLA.)
Regarding claim 4, the combination of Shah and Querbach teaches all of the limitations of claim 1 above.
Querbach further teaches wherein the memory maintenance operation comprises a memory refresh operation. (Querbach [Abstract], [0017], and [0020] discloses that the system has deterministic control over both when to start a refresh command and when it will be done. Thus the deterministic phase of Shah may execute a refresh operation that is an example of a maintenance operation.)
The motivation to combine Querbach into the existing combination is the same as set forth in claim 1 above.
Regarding claim 5, the combination of Shah and Querbach teaches all of the limitations of claim 1 above.
Querbach further teaches wherein the system further comprises a plurality of memory banks, (Querbach [0033] discloses the memory is organized as a plurality of banks of memory.) and wherein the at least one second instruction is to cause the memory maintenance operation on the plurality of memory banks. (Querbach [0038] discloses the memory controller processes refresh commands for a plurality of banks.)
The motivation to combine Querbach into the existing combination is the same as set forth in claim 1 above.
Regarding claim 6, the combination of Shah and Querbach teaches all of the limitations of claim 5 above.
Querbach further teaches wherein the plurality of memory banks comprise dynamic random access memory (DRAM). (Querbach [0033] discloses memory device 140 is composed of resources 160 organized into banks. Querbach [0026] discloses the memory devices may be DRAM. Thus the plurality of memory banks may comprise a DRAM.)
The motivation to combine Querbach into the existing combination is the same as set forth in claim 1 above.
Regarding claim 7, the combination of Shah and Querbach teaches all of the limitations of claim 1 above.
wherein: the system further comprises a plurality of memory banks; (Querbach [0033] discloses the memory is organized as a plurality of banks of memory.) and the at least one second instruction is to cause the memory maintenance operation at a first time (Querbach [Abstract], [0017], and [0020] discloses that the system has deterministic control over both when to start a refresh command and when it will be done. Thus the deterministic phase of Shah may execute a refresh operation that is an example of a maintenance operation.) on a first subset of the plurality of memory banks. (Querbach [0050] discloses the system will refreshes N of Q rows of a bank.)
The motivation to combine Querbach into the existing combination is the same as set forth in claim 1 above.
Regarding claim 8, the combination of Shah and Querbach teaches all of the limitations of claim 7 above.
wherein the at least one first instruction is to cause memory access to a memory bank of a second subset of the plurality of memory banks during the memory maintenance operation of the first subset of the plurality of memory banks. (Querbach [0026] discloses each channel is independently operable and different channels may be operated in parallel. Querbach [0033] discloses the channels may be composed of banks of memory. Thus Shah in view of Querbach suggests to a POSITA there may be two channels operating independently that are performing deterministic memory refreshes.)
The motivation to combine Querbach into the existing combination is the same as set forth in claim 1 above.
Regarding claim 9, the combination of Shah and Querbach teaches all of the limitations of claim 7 above.
Querbach further teaches wherein the set of scheduled instructions further comprises at least one third instruction to cause a second memory maintenance operation at a second time on a second subset of the plurality of memory banks. (Querbach [0026] discloses each channel is independently operable and different channels may be operated in parallel. Querbach [0033] discloses the channels may be composed of banks of memory. Thus Shah in view of Querbach suggests to a POSITA there may be two channels operating independently that are performing deterministic memory refreshes. Thus there may be a third instruction to cause a second refresh (a second memory maintenance operation) on a second time on a second subset of the plurality of memory banks in the second channel. See also Querbach [Abstract] and [] that discloses the system determines when the refresh may start.)
The motivation to combine Querbach into the existing combination is the same as set forth in claim 1 above.
Regarding claim 10, the combination of Shah and Querbach teaches all of the limitations of claim 1 above. Shah further teaches wherein the compiler is configured to: determine a response return time associated with the at least one first instruction; (Shah [0028] discloses that the deterministic phase begins when all of the tiles have signal they have completed their non-deterministic instructions. Thus Shah [0026-[0028] discloses the compiler determines when all non-deterministic operations have completed, thus determines a response return time associated with at least one first/non-deterministic instruction.)
Shah in view of Querbach further teaches determine a request window for scheduling the memory maintenance operation associated with the at least one second instruction; (Shah Fig 1B and [0026-[0028] discloses the compiler identifies the amount of time required for the deterministic phase 152B that is a fixed duration and an example of a request window for schedule deterministic/second operations that may be a maintenance operation per Shah in view of Querbach) and schedule the at least one first instruction and the at least one second instruction based on the response return time and the request window. (Shah Fig 1B and [0026]-[0028] discloses that the deterministic phase begins when all of the tiles have signal they have completed their non-deterministic instructions. Thus the compiler schedules non-deterministic operations at 154Y (i.e. at least on first/non-deterministic instruction) and deterministic (i.e. at least one second/deterministic instruction) at 152B based on the response window (i.e. based on the deterministic phase 152B window).)
The motivation to combine Querbach into the existing combination is the same as set forth in claim 1 above.
Regarding claim 11, Shah teaches A method, comprising: (Shah [0020] discloses the inventive concepts are directed to methods.)
The remainder of claim 11 recites limitations described in claim 1 above and thus is rejected based on the teaching and rationale of claim 1 above.)
Regarding claim 12, Shah and Querbach teaches all of the limitations of claim 11 above.
Shah further teaches wherein the at least one first instruction is to cause memory access by a processor device during execution of the at least one first instruction. (Shah [0027] discloses that the non-deterministic instruction of the first instruction may be a data fetch (i.e. read) instruction that is an example of a memory access request.)
Regarding claim 13, Shah and Querbach teaches all of the limitations of claim 11 above.
The remainder of claim 13 recites limitations described in claim 4 above and thus is rejected based on the teaching and rationale of claim 4 above.)
Regarding claim 14, Shah and Querbach teaches all of the limitations of claim 11 above.
The remainder of claim 14 recites limitations described in claim 5 above and thus is rejected based on the teaching and rationale of claim 5 above.)
Regarding claim 15, Shah and Querbach teaches all of the limitations of claim 14 above.
The remainder of claim 15 recites limitations described in claim 6 above and thus is rejected based on the teaching and rationale of claim 6 above.)
Regarding claim 16, Shah and Querbach teaches all of the limitations of claim 11 above.
The remainder of claim 16 recites limitations described in claim 7 above and thus is rejected based on the teaching and rationale of claim 7 above.)
Regarding claim 17, Shah and Querbach teaches all of the limitations of claim 16 above.
The remainder of claim 17 recites limitations described in claim 8 above and thus is rejected based on the teaching and rationale of claim 8 above.)
Regarding claim 18, Shah and Querbach teaches all of the limitations of claim 16 above.
The remainder of claim 18 recites limitations described in claim 9 above and thus is rejected based on the teaching and rationale of claim 9 above.)
Regarding claim 19, Shah and Querbach teaches all of the limitations of claim 11 above.
The remainder of claim 19 recites limitations described in claim 10 above and thus is rejected based on the teaching and rationale of claim 10 above.)
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Shah (Shah et al., US 2021/0312320 A1) and further in view of Querbach (QUERBACH et al., US 2017/0352406 A1) and Housty (Housty et al., US 2010/0325371 A1).
Regarding claim 20, Shah teaches A method, comprising: (Shah [0020] discloses the inventive concepts are directed to methods.
obtaining, from the memory controller, a response return time corresponding to a maximum time for the memory controller to return a response to a memory access request; (Shah [0026] discloses the compiler schedules instructions into one or more deterministic phases where the time required for each component of an instruction is known and statically scheduled. Given the actual time required is known, the system knows the minimum and maximum time required for the access request as they are equal to the time required for the instruction.)
and translating, by a compiler, a program into a deterministic schedule comprising a set of scheduled instructions for execution on a processor device, (Examiner notes that a deterministic schedule is a schedule where a schedule the specify when each instruction will be executed. Shah Fig. 1B and [0021] and [0021]-[0028] discloses the system contains a compiler 120 that takes a machine learning network 100 (a program) that generates program 150 that is a set of instructions that are executed by processing elements in the MLA according to a schedule determined by the compiler.)
wherein the compiler translates the program into the deterministic schedule (Shah Fig. 1 and [0021] discloses the system contains a compiler 120 that takes a machine learning network 100 (a program) that generates program 150 that is a set of instructions that are executed by processing elements in the MLA according to a schedule determined by the compiler (i.e. statically scheduled instructions what knows how long it takes to execute each instruction), thus produces a deterministic schedule.) based on the response return time, (Shah [0028] discloses that the deterministic phase begins when all of the tiles have signal they have completed their non-deterministic instructions. Thus the deterministic operations are scheduled by the compiler when all non-deterministic operations have completed, thus taking into account the maximum time required for all non-deterministic operations (i.e. based on the response return time ) and a known duration to complete a memory maintenance operation. (Shah Fig. 1B and [0026] that shows there may be a deterministic phase 152B that executes instructions whose time required for each computation is known. ),
However, the combination does not explicitly disclose querying a memory controller to initiate training one or more attached memory channels; polling the memory controller to determine that the one or more attached memory channels are trained; … wherein the compiler translates the program into the deterministic schedule based on the response return time, and a known duration to complete a memory maintenance operation
Querbach, of a similar field of endeavor, further discloses wherein the compiler translates the program into the deterministic schedule based on the response return time, and a known duration to complete a memory maintenance operation (Querbach [Abstract], [0017], and [0020] discloses that the system has deterministic control over both when to start a refresh command and when it will be done. Thus the deterministic phase of Shah may execute a refresh operation that is an example of a maintenance operation.)
Shah and Querbach are in a similar field of endeavor, as both all to schedule operations at a DRAM memory. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention having Shah and Querbach before them to incorporate the deterministic scheduling of refresh operations to a DRAM memory as detailed in Querbach that supports DRAM memory and seeks to deterministically schedule memory operations as taught by Shah. Thus combining prior art elements according to known methods to yield predictable results (enable the controller to precisely control the timing of operations executed by memory devices and control the maximum time a memory is unavailable for routine operations such as read or writes to the memory.).
However, the combination does not explicitly disclose querying a memory controller to initiate training one or more attached memory channels; polling the memory controller to determine that the one or more attached memory channels are trained;
Housty, of a similar field of endeavor, further teaches querying a memory controller to initiate training one or more attached memory channels; (Examiner notes that per paragraph [0042] of the instant application the training of the memory may be done as aa boot process totally independent of the compiled program and may be any standard training that is performed during a boot. Housty [0019] discloses a training synchronizer needs to be told the values of channel training parameters to use, where the training synchronizer initiates the training of the memory using these parameters.)
polling the memory controller to determine that the one or more attached memory channels are trained; (Housty [0006] discloses the BIOS software polls a completion bit for each channel to determine an access request used perform the training is completed, thus the system is polling the memory controller to determine that one or more memory channels are trained.)
Shah, Querbach, and Housty are in a similar field of endeavor as both relate to managing a memory Device such as a DRAM memory. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention, having the teachings of Shah and Housty before them, to modify the teachings of Shah and Querbach, to include the teachings of Housty that includes training DRAM memory parameters during the bootup processes as taught by Shah that supports DRAM memory that require memory training to accurately store data. Thus combining prior art elements according to known methods to achieve predictable results (to accurate store data in DRAM memory).
Response to Remarks
Examiner thanks applicant for their claim amendments and remarks of 8/12/2026. They have been fully considered.
Regarding II. Rejections for Non-statutory Obvious-type Double Patenting.
Applicant argues on page 6 of their remarks ‘Without acquiescing to or otherwise commenting on the merits of the rejection, Applicant has amended the claims to overcome the present rejection, and respectfully submits that the nonstatutory obviousness-type double patenting rejection is rendered moot by the amendments contained herein.’
Examiner respectfully notes ‘A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers)’. Applicant has merely stated the double patenting rejection is moot. However, MPEP requires ‘a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims’. Declaring the rejection moot is not showing/demonstrating/explaining how the claims subject to the rejection are patentable distinct from the reference claims. Examiner notes that the MPEP does not provide a third option of amending the claims without further explanation other than the claims have been amended.
In accordance with MPEP § 804 and §714.03 the examiner will hold any response/amendments to this application that fail to address a double patenting rejection as deliberate and not fully responsive when the response does not contain either: 1) an approved terminal disclaimer, or 2) a complete and concise explanation of how the inventions are patentably distinct from one another.
Regarding - Rejections under 35 U.S.C. § 103
Applicant argues on pages 6-7 of their remarks ‘Applicant respectfully traverses the cited references in view of the amendments to claim 1 contained herein. Shah divides execution into deterministic and non-deterministic "phases," and schedules instructions to execute only after a non-deterministic operation is completed. For instance, paragraph [0041] of Shah recites "data transfer from off-chip DRAM is more unpredictable in timing. As a result, these instructions are non-deterministic in nature and they are executed by the microcontroller 277. Therefore, they are executed in one of the non- deterministic phases and they are not statically scheduled." In paragraph [0042], Shah clarifies that "the Tiles execute only statically scheduled instructions, and all non-statically scheduled instructions are executed by processing elements outside the Tile mesh, for example, the microcontroller 277." Therefore, Shah does not disclose "a compiler configured to translate a program into a deterministic schedule comprising at least one first instruction, the at least one first instruction configured to implement a non-deterministic operation."’’
Examiner respectfully disagrees. As noted in the rejection above ‘Shah Fig. 1 and [0021] discloses the system contains a compiler 120 that takes a machine learning network 100 (a program) that generates program 150 that is a set of instructions that are executed by processing elements in the MLA according to a schedule determined by the compiler (i.e. statically scheduled instructions what knows how long it takes to execute each instruction), thus produces a deterministic schedule. Shah [0027] discloses that the program 150 may contain non-deterministic phases 154X,Y, that may be data fetch of instructions from off-chip memory and each instruction is an example of a non-deterministic command. Shah Fig. 1B and [0026] that shows there may be a deterministic phase 152B that executes instructions whose time required for each computation is known and each instruction is an example of a deterministic phase (a second command).
Applicant argues on pages 6-7 of their remarks ‘Furthermore, Shah certainly does not disclose "wherein the at least one second instruction is scheduled based on a worst case time to complete the non-deterministic operation" as Shah describes the non-deterministic operations as "unpredictable in timing."
Examiner respectfully disagrees. Shah [0028] discloses that the deterministic phase begins when all of the tiles have signal they have completed their non-deterministic instructions. Thus the deterministic operations are scheduled by the compiler when all non-deterministic operations have completed, thus taking into account the maximum time required for all non-deterministic operations (i.e. the worst case time for non-deterministic operations). While the worst case time is unpredictable, the system schedules it based on the maximum time required for all non-deterministic operations (the worst case time).
Applicant further argues on page 9 of their remarks ‘The remaining cited references fail to cure the deficiency of Shah.
Examiner respectfully notes that Shaw is not deficient.
Applicants’ arguments with respect to independent claims 11 and 20 all reply upon arguments similar to claim 1 above and has been addressed in the response to remarks of claim 1 above.
Applicants’ argument with respect to dependent claims 2-9, 11-15, and 17-22 all rely upon perceived errors in bases claims and thus have been addressed in the rejection and remarks of the base claims.
Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Shalem (SHALEM US 2022/0365764 A1) - Shalem [0003]-[0005] discloses that the ISO 26262 standard in road vehicles requires memory management functions should ensure deterministic behavior with worst-case scenario execution time. Thus any system that implements memory management in a road vehicle would schedule the memory operations using worst-case estimates to ensure deterministic behavior.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANICE M. GIROUARD whose telephone number is (469)295-9131. The examiner can normally be reached M-F 9:30 - 7:30.
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/JANICE M. GIROUARD/Primary Examiner, Art Unit 2138
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