Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting – Non-statutory
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claim(s) 22-28, 35-41 is/are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1-9 of Patent No. US12379991B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim(s) 22, 35 is/are similar to claim(s) 1 of US12379991B2. Therefore the patent claim and the application claim would have been obvious.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim(s) 29-34 is/are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claim(s) is/are drawn to software per se.
Claim(s) 29 recites a host system comprising “a host controller.” It does not comprise “host controller” in the par 18 of the Spec. As such, the noted claim(s) is/are drawn to software per se. It is suggested that “a processor chipset” is recited in the claim(s), based on par 18 of the Spec, “The host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset.“
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim(s) 22-28, 35-41 is/are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claims fall within at least one of the four categories of patent eligible subject matter. However, the claimed invention is directed to performing steps that fall within the mental process groupings of abstract ideas because they cover concepts performed in the human mind. An analysis of the claims regarding subject matter eligibility follows:
Step1: Claim(s) 22-28, 35-41 recite a system and a medium, therefore satisfying Step 1 of the analysis.
Step 2A, Prong 1: Claim(s) 22, 35 recite detect a fault condition of the memory system, which, under their broadest reasonable interpretation, covers performance of the limitations entirely in the human mind and/or with the aid of pen and paper. Specifically, the steps of “detect” may be practically performed in the human mind using observation, evaluation, and judgement of the memory system (MPEP 2106.04(a)(2), subsection Ill). For example, “detect” in the context of the claim(s) encompasses a user detecting a fault condition of the memory system.
Claim(s) 23-28, 36-41 recite further limitations that fall under the judicial exception as recited in claim(s) 22, 35. Each of the further limitations encompass performance of the steps within the human mind.
Step 2A, Prong 2: The additional elements recited in claim(s) 22, 35, “a control circuitry,” “memory arrays,” “memory system,” “physical host interface,” “medium,” “processors,” “set, in an exception event status attribute, a first indication that the fault condition corresponds to a system level fault;” “set, in a register, a second indication of a type of the system level fault;” “transmit, to a host system, a first message that indicates an occurrence of the fault condition in accordance with setting the first indication in the exception event status attribute; and” “transmit, to the host system, the second indication of the type of the system level fault” do not integrate the judicial exception into a practical application. These limitations are directed to implementing the abstract idea using generic computer components (MPEP 2106.05(f)).
Claim(s) 23-28, 36-41 recite further details regarding UPIU, event alert bit, and a safe mode of operation. These claims contain no additional elements which would integrate the abstract idea into a practical application.
Accordingly, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the identified abstract idea.
Step 2B: Claim(s) 22, 35 do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed in Step 2A, Prong 2 above, the recitations of “a control circuitry,” “memory arrays,” “memory system,” “physical host interface,” “medium,” “processors,” “set, in an exception event status attribute, a first indication that the fault condition corresponds to a system level fault;” “set, in a register, a second indication of a type of the system level fault;” “transmit, to a host system, a first message that indicates an occurrence of the fault condition in accordance with setting the first indication in the exception event status attribute; and” “transmit, to the host system, the second indication of the type of the system level fault,” are recited at a high level of generality. These elements amount to receiving or transmitting data over a network or storing and retrieving information in memory, and thus are well-understood, routine, conventional activity (MPEP 2106.05(d), subsection II).
Regarding claim(s) 23-28, 36-41, the additional elements are not sufficient to amount to significantly more than the judicial exception because they simply apply the exception using a generic computer.
Therefore, claim(s) 22-28, 35-41 recite an abstract idea without significantly more, and are not patent eligible.
Matter Not Found in the Prior Art
There is no prior art rejection for independent claim(s) 22, 29, 35, and would be allowable if rewritten to overcome the rejection(s) under double patenting rejection, 35 U.S.C. 101.
The following is an examiner’s statement of reasons:
This is a CON of Patent No. US12379991B2. The elements of independent claim(s) 22, 29, 35 were not found through a search of the prior art, nor were they considered obvious by the examiner. In particular, among the prior art of records, US20190278651A1, do/does not teach or suggest, in combination with the remaining limitations:
As in claim 22, “set, in an exception event status attribute, a first indication that the fault condition corresponds to a system level fault;set, in a register, a second indication of a type of the system level fault;transmit, to a host system, a first message that indicates an occurrence of the fault condition in accordance with setting the first indication in the exception event status attribute;”
As in claim 29, “receive, from the memory system, a message responsive to the command, the message comprising a first indication that a fault condition exists at the memory system;transmit, to the memory system, a read request for information associated with the fault condition; andreceive, from the memory system responsive to the read request, a second indication indicating a type of the fault condition.”
As in claim 35, “set, in an exception event status attribute, a first indication that the fault condition corresponds to a system level fault; set, in a register, a second indication of a type of the system level fault; transmit, to a host system, a first message that indicates an occurrence of the fault condition in accordance with setting the first indication in the exception event status attribute;”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATHERINE LIN whose telephone number is (571)431-0706. The examiner can normally be reached Monday-Friday; 8 a.m. - 5 p.m. EST.
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/KATHERINE LIN/Primary Examiner, Art Unit 2113
