DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Other References:
Zhang (US 20210150362) - [0024] As shown in FIG. 1, the memory 120 may include a program 125 for implementing the BBS-based neural network model compression – relates to claimed in-memory operator.
Non-patent Literature – Lawlor, Orion Sky, In-memory data compression for sparse matrices, Proceedings of the 3rd Workshop on Irregular Applications: Architectures and Algorithms, Article No.: 6, pages 1-6, Nov 17, 2013 – relates to claimed memory device comprising in-memory operator.. encoding data stored in memories…. matrix coordinate.
In order to potentially overcome the rejections, the Office suggest amending the claims to clarify the limitations related to:
(Claim 1 and respective dependent claims) memory device comprising in encoding the data stored… generate metadata depending on an encoding scheme or a type of operation to be performed … an assigned operation … using the generated metadata, decode;
(Claim 30 and respective dependent claims) operating method comprising… in encoding … whether to generate metadata depending on … … performing an assigned operation … using the generated metadata, decoding. This is a method claim with contingent limitation (whether to…) with improper scope definition. Specifically, the claim only recites the condition of what happens in response to determination to generate the metadata, however, the claim does not recite what happens in the scenario when the determination is made not to generate the metadata. The Office suggests that claim needs to recite the condition when the whether condition has negative results.
IDS filed 6/5/2026 and 7/10/25 have been considered.
Drawings filed 7/10/2025 are accepted.
Oath filed 7/10/2025 has been placed in the file.
Preliminary Amendment 9/25/2025: Claims 1-20 were cancelled; Claims 21-38 pending.
Continuation Application 17/865824 was abandoned (2/9/2026). Confirmed by Applicant (see interview summary).
Specification
The disclosure is objected to:
The specification states in para [0001] lines 1-2 that U.S. Application No. 17865824,… (now allowed); however Application 17/865,824 was not allowed, it was abandoned.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-23, 25, 26, 28, 30-32, 34, 35, 37 are rejected under 35 U.S.C. 103 as being unpatentable over Willcock (US 20170269865 A1) and in view of Jain (US 20220012592 A1)
Claim 21. Willcock discloses A memory device (eg. 0048 Fig. 1A 1B – memory device 120), comprising:
a memory bank comprising a plurality of memories and an in-memory operator (eg., 0025 Fig. 1B - bank of subarrays; 0048 a memory device 120 having a plurality of banks (e.g., 121-0, . . . , 121-N as shown in FIG. 1B; 0025 - controllers for operations components (e.g., each controller being a sequencer, a state machine, a microcontroller, a sub-processor, ALU circuitry, or some other type of controller) to execute a set of instructions to perform an operation on data) and
a memory controller configured to control the memory bank (eg., 0038 - channel controller 143 can include a logic component 160 to allocate a plurality of locations (e.g., controllers for subarrays) in the arrays of each respective bank to store bank commands),
wherein the in-memory operator is configured to: (eg., 0038 - channel controller 143 can dispatch commands (e.g., PIM commands) to the plurality of memory devices 120-1, . . . , 120-N to store those program instructions within a given bank of a memory device. The channel controller 143 can, in various embodiments, issue instructions for operations to be stored by the operations component 172 (e.g., as addressed via controller 140) )
encode data stored in at least one of the plurality of memories (eg., 0014 - operations component being formed on pitch with the memory cells of the array and being configured to compute functions (e.g., operations), on pitch with the memory cells. 0040 - The controller 140 can be a state machine, a sequencer, or some other type of controller. The controller 140 can, control performance of Boolean logical operations and/or shifting data (e.g., right or left) in a row of an array (e.g., memory array 130).).
Willcock does not disclose, but Jain discloses
in encoding the stored data, determine whether to generate metadata depending on an encoding scheme or a type of an operation to be performed on an encoded data, the metadata comprising information on the encoded data, in response to determination to generate the metadata, generate the metadata related to the encoding (eg., 0040 - FIG. 2, the compression deciding circuitry 206 determines a compression process to be executed by the compressing circuitry 208. In some examples, the compression deciding circuitry 206 determines the compression process to be executed by the compressing circuitry 208; 0041 Fig; 2 - when the compressing circuitry 208 executes the first compression process, the compressing circuitry 208 is to generate a bitmap indicative of respective locations of the weights in a weight matrix; 0043 - meta-data generating circuitry 210 determines meta-data for the compressed data),
perform an assigned operation based on the encoded data (eg., 0043 - FIG. 2, the meta-data generating circuitry 210 stores the meta-data via the memory 212. Specifically, the meta-data generating circuitry 210 stores the meta-data),
and using the generated metadata, decode the encoded data on which the operation is performed (eg., 0028 - meta-data indicates a location of the compressed matrix and a process to be executed to decompress the matrix.);
and
wherein the in-memory operator is further configured to generate the metadata when any one or any combination of any two or more of size information of the encoded data, encoding type information, and matrix coordinate information corresponding to the encoded data is required in the operation (eg., 0028 In response to the matrix being compressed, the meta-data indicates a cache size of the compressed matrix and a compression operation utilized to compress the matrix. Accordingly, the meta-data indicates a location of the compressed matrix).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with banks and microcontroller for compressing data as disclosed by Willcock, with Jain, providing the benefit of an explosion in demand for accelerated inference (see Jain, 0003) generate meta-data corresponding to a matrix (e.g., a tile) of neural network weights… the meta-data indicates whether the matrix is compressed (0028).
Claim 22. Willcock does not disclose, but Jain discloses
wherein the in-memory operator is further configured to, in response to reception of a transmission request from another device for the encoded data on which the operation is performed, transmit, to the other device, decoded data obtained by decoding the encoded data on which the operation is performed (eg., [0035] In the illustrated example of FIG. 1, the matrix decompressing circuitry 106 decompresses at least a portion of the compressed data to obtain one or more of the weight matrices in response to a request from the neural network circuitry 102.; 0066 - FIG. 6, the data transceiver 602 receives a data request from the neural network circuitry 102 via the bus 108. In FIG. 6, in response to the data being decompressed, the data transceiver 602 transmits the data to the neural network circuitry 102 via the bus 108.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with banks and microcontroller for compressing data as disclosed by Willcock, with Jain, providing the benefit of an explosion in demand for accelerated inference (see Jain, 0003) generate meta-data corresponding to a matrix (e.g., a tile) of neural network weights… the meta-data indicates whether the matrix is compressed (0028).
Claim 23. Willcock does not disclose, but Jain discloses
wherein the in-memory operator is further configured to determine not to generate the metadata, perform the assigned operation based on the encoded data and decode the encoded data on which the operation is performed without using the metadata (eg., 0111 Fig. 12 - the compressed data identifying circuitry 302 can determine the data is uncompressed in response to receiving a second signal. In some examples, the compressed data identifying circuitry 302 determines the data is compressed in response to receiving the data from the compressing circuitry 208 (FIG. 2). In response to the compressed data identifying circuitry 302 determining the data is compressed, the operations 1300 proceed to block 1204. In response to the compressed data identifying circuitry 302 determining the data is uncompressed, the operations 1300 proceed to block 1206.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with banks and microcontroller for compressing data as disclosed by Willcock, with Jain, providing the benefit of an explosion in demand for accelerated inference (see Jain, 0003) generate meta-data corresponding to a matrix (e.g., a tile) of neural network weights… the meta-data indicates whether the matrix is compressed (0028).
Claim 25. Willcock does not disclose, but Jain discloses
wherein the in-memory operator is further configured to generate encoded data by removing values corresponding to a reference value from values comprised in the stored data (eg., 0054 Fig. 4 - matrix compressing circuitry 104 obtains pruned data 404 in response to the pruning circuitry 204 pruning a tile of neural network weights. Specifically, the pruning circuitry 204 can remove the neural network weights in the tile that have a value below a threshold).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with banks and microcontroller for compressing data as disclosed by Willcock, with Jain, providing the benefit of an explosion in demand for accelerated inference (see Jain, 0003) generate meta-data corresponding to a matrix (e.g., a tile) of neural network weights… the meta-data indicates whether the matrix is compressed (0028).
Claim 26. Willcock does not disclose, but Jain discloses
wherein the in-memory operator is further configured to, in response to completion of the operation, store result data of the operation in the at least one of the plurality of memories (eg., 0043 - FIG. 2, the meta-data generating circuitry 210 stores the meta-data via the memory 212. Specifically, the meta-data generating circuitry 210 stores the meta-data for the respective weight matrices in a leading cache line of the memory 212.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with banks and microcontroller for compressing data as disclosed by Willcock, with Jain, providing the benefit of an explosion in demand for accelerated inference (see Jain, 0003) generate meta-data corresponding to a matrix (e.g., a tile) of neural network weights… the meta-data indicates whether the matrix is compressed (0028).
Claim 28. Willcock does not disclose, but Jain discloses
wherein the in-memory operator is further configured to encode the stored data using either one or both of sparsification compression and quantization compression (eg., 0029 - sparsity can be utilized to compress neural network weights while reducing the bandwidth utilization between a dynamic random access memory (DRAM) and a core and/or between cores; 0030 - methodology that leverages advanced vector extension (AVX) and advanced matrix extension (AMX) technology to enable compression of quantized neural network ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with banks and microcontroller for compressing data as disclosed by Willcock, with Jain, providing the benefit of an explosion in demand for accelerated inference (see Jain, 0003) generate meta-data corresponding to a matrix (e.g., a tile) of neural network weights… the meta-data indicates whether the matrix is compressed (0028).
Claim 30. Willcock discloses An operating method (eg. 0048 Fig. 1A 1B – memory device 120), comprising:
encoding, by an in-memory operator comprised in a memory bank, data stored in at least one of a plurality of memories of the memory bank, (eg., 0014 - operations component being formed on pitch with the memory cells of the array and being configured to compute functions (e.g., operations), on pitch with the memory cells. 0040 - The controller 140 can be a state machine, a sequencer, or some other type of controller. The controller 140 can, control performance of Boolean logical operations and/or shifting data (e.g., right or left) in a row of an array (e.g., memory array 130); ., 121-0, . . . , 121-N as shown in FIG. 1B; 0025 - controllers for operations components (e.g., each controller being a sequencer, a state machine, a microcontroller, a sub-processor, ALU circuitry, or some other type of controller) to execute a set of instructions to perform an operation on data).
Willcock does not disclose, but Jain discloses
in encoding the stored data, determining, by the in-memory operator, whether to generate metadata depending on an encoding scheme or a type of an operation to be performed on an encoded data, the metadata comprising information on the encoded data, in response to determination to generate the metadata, generating, by the in-memory operator, the metadata related to the encoding (eg., 0040 - FIG. 2, the compression deciding circuitry 206 determines a compression process to be executed by the compressing circuitry 208. In some examples, the compression deciding circuitry 206 determines the compression process to be executed by the compressing circuitry 208; 0041 Fig; 2 - when the compressing circuitry 208 executes the first compression process, the compressing circuitry 208 is to generate a bitmap indicative of respective locations of the weights in a weight matrix; 0043 - meta-data generating circuitry 210 determines meta-data for the compressed data),
performing, by the in-memory operator, an assigned operation based on the encoded data (eg., 0043 - FIG. 2, the meta-data generating circuitry 210 stores the meta-data via the memory 212. Specifically, the meta-data generating circuitry 210 stores the meta-data),
and using the generated metadata, decoding, by the in-memory operator, the encoded data on which the operation is performed (eg., 0028 - meta-data indicates a location of the compressed matrix and a process to be executed to decompress the matrix.);
wherein the determining whether to generate metadata comprises generating the metadata when any one or any combination of any two or more of size information of the encoded data, encoding type information, and matrix coordinate information corresponding to the encoded data is required in the operation (eg., 0028 In response to the matrix being compressed, the meta-data indicates a cache size of the compressed matrix and a compression operation utilized to compress the matrix. Accordingly, the meta-data indicates a location of the compressed matrix).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with banks and microcontroller for compressing data as disclosed by Willcock, with Jain, providing the benefit of an explosion in demand for accelerated inference (see Jain, 0003) generate meta-data corresponding to a matrix (e.g., a tile) of neural network weights… the meta-data indicates whether the matrix is compressed (0028).
Claim 31 is rejected for reasons similar to Claim 22 above.
Claim 32 is rejected for reasons similar to Claim 23 above.
Claim 34 is rejected for reasons similar to Claim 25 above.
Claim 35 is rejected for reasons similar to Claim 26 above.
Claim 37 is rejected for reasons similar to Claim 28 above.
Claims 24, 33 are rejected under 35 U.S.C. 103 as being unpatentable over Willcock (US 20170269865 A1) and in view of Jain (US 20220012592 A1) and Rigo (US 20200274552 A1)
Claim 24. Willcock in view of Jain does not disclose, but Rigo discloses
wherein the in-memory operator is further configured to, in response to reception of a transmission request from another device for the encoded data on which the operation is performed, transmit, to the other device, the encoded data on which the operation is performed and the metadata (eg., 0042 Fig. 3 - If the data compressor 106 compresses the block out of order or in parallel, the data assembler 212 monitors the compression to be able to reassemble the compressed blocks of data in the same order as the data from the dataset. At block 310 the example interface 202 transmits the compressed data set to the off-chip memory 104 of FIG. to be stored as compressed data.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with banks and microcontroller for compressing data as disclosed by Willcock, with Jain, with Rigo providing the benefit of neural networks are connected to off-chip memory (e.g., memory located off the processor chip) to provide increase available capacity of the on-chip neural network (see Rigo, 0002).
Claim 33 is rejected for reasons similar to Claim 24 above.
Claims 27, 36 are rejected under 35 U.S.C. 103 as being unpatentable over Willcock (US 20170269865 A1) and in view of Jain (US 20220012592 A1) and Qi (US 20230090429 A1)
Claim 27. Willcock in view of Jain does not disclose, but Qi discloses
another memory bank comprising another in-memory operator, wherein the in-memory operator and the other in-memory operator are configured to generate encoded data by compressing the stored data in parallel in a buffer of the memory bank (eg., 0071 - FIG. 2B, the memory unit 940 includes multiple memory bank groups 943a-d, each of the memory bank groups including one or more memory banks having multiple memory locations associated with respective memory addresses, which provides hardware foundation for parallel memory access at different locations by different hardware accelerators during a single cycle.; 0011 - to perform data compression and decompression ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with banks and microcontroller for compressing data as disclosed by Willcock, with Jain, with Qi providing the benefit of a high-performance on-chip memory controller for performing computations of machine learning models (see Qi, 0001) a high-performance on-chip controller that addresses low-latency and high throughput problems (0042).
Claim 36 is rejected for reasons similar to Claim 27 above.
Claims 29, 38 are rejected under 35 U.S.C. 103 as being unpatentable over Willcock (US 20170269865 A1) and in view of Jain (US 20220012592 A1) and Latorre (US 20200373941 A1)
Claim 29. Willcock in view of Jain does not disclose, but Latorre discloses
wherein the in-memory operator is further configured to generate encoded data having a smaller size than a size of the stored data by encoding the stored data (eg., 0015 - compress the data (e.g., reduce the data size) to save bandwidth resources when transmitting the data and save memory resources when storing the data; 0026 Fig. 3 - parallel processing units (PPUs) 310 to 310-N (hereinafter PPUs 310s) and their respective memories 315 to 315-N).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device with banks and microcontroller for compressing data as disclosed by Willcock, with Jain, with Latorre providing the benefit of hardware can be simplified and optimized to process data, e.g., computed, transmitted and stored, much faster and much more efficiently than the conventional compression techniques that rely on a non-structured sparsity format (see Latorre, 0016).
Claim 38 is rejected for reasons similar to Claim 29 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAUTAM SAIN whose telephone number is (571)270-3555. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached at 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135
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