The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-11 are presented for examination in this application (19/265,663) filed on July 10, 2025. Claims 12-20 are withdrawn as being not elected on response to elect filed on 8/24/2026.
The Examiner cites particular sections in the references as applied to the claims below for the convenience of the applicant(s). Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant(s) fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claims 1-11 are pending for consideration.
Drawings
The drawings submitted on July 10, 2025 have been considered and accepted.
Information Disclosure Statement
6.Acknowledgment is made of the information disclosure statements filed on 7/10/2025. U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 U.S.C. 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-9 are rejected under 35 U.S.C. 112 (b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as claims recite “whether the write command is from a host device memory range that is near a last model load read” as it is unclear what “near a last model read” refer to as it is a relative term and it is unclear how the host device memory range is near a last model load read and if the last load read refers to a read operation/command performed within the model when it is completed or else.
All dependent claims are rejected as having the same deficiencies as the claims they depend from.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103(a) as being disclosed by D’Eliseo et al. (US PGPUB 2023/0342823 hereinafter referred to as D’Eliseo), in view of Iyigun et al. (US 8,990,441 hereinafter referred to as Iyigun).
As per independent claim 1, D’Eliseo discloses a data storage device, comprising: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: perform a model load operation [(Paragraphs 0016, 0036 and 0059 ; FIGs. 1 and 5 and related text) wherein D’Eliseo teaches cache agent 134 receives, from a requestor, such as cache manager 114, a series of multiple cache read commands (e.g., sequential read commands) requesting first data from a memory array of memory device 130 and spread across multiple memory planes. Cache agent 134 further receives, from the requestor, a cache read context switch command and a snap read command requesting second data from one of the plurality of memory planes of the memory array of memory device 130; cache agent 134 receives and processes memory access commands, such as read commands, cache read commands, cache read context switch commands, snap read commands, and cache read context restore commands. In one embodiment, cache agent 134 receives a series of multiple cache read commands (e.g., sequential read commands) requesting first data from memory array 250 and spread across multiple memory planes 372(0)-372(3) to correspond to the claimed limitation]; receive a command from a host device during the performing [(Paragraphs 0036 and 0059 ; FIGs. 1 and 5 and related text) wherein D’Eliseo teaches cache agent 134 receives, from a requestor, such as cache manager 114, a series of multiple cache read commands (e.g., sequential read commands) requesting first data from a memory array of memory device 130 and spread across multiple memory planes. Cache agent 134 further receives, from the requestor, a cache read context switch command and a snap read command requesting second data from one of the plurality of memory planes of the memory array of memory device 130; cache agent 134 receives and processes memory access commands, such as read commands, cache read commands, cache read context switch commands, snap read commands, and cache read context restore commands. In one embodiment, cache agent 134 receives a series of multiple cache read commands (e.g., sequential read commands) requesting first data from memory array 250 and spread across multiple memory planes 372(0)-372(3) to correspond to the claimed limitation]; wherein the prioritizing occurs during the performing [(Paragraphs 0036 and 0059 ; FIGs. 1 and 5 and related text) wherein D’Eliseo teaches cache agent 134 receives, from a requestor, such as cache manager 114, a series of multiple cache read commands (e.g., sequential read commands) requesting first data from a memory array of memory device 130 and spread across multiple memory planes. Cache agent 134 further receives, from the requestor, a cache read context switch command and a snap read command requesting second data from one of the plurality of memory planes of the memory array of memory device 130; cache agent 134 receives and processes memory access commands, such as read commands, cache read commands, cache read context switch commands, snap read commands, and cache read context restore commands. In one embodiment, cache agent 134 receives a series of multiple cache read commands (e.g., sequential read commands) requesting first data from memory array 250 and spread across multiple memory planes 372(0)-372(3) to correspond to the claimed limitation].
D’Eliseo does not appear to explicitly disclose determine whether the command is a paging input/output (I/O) write command, wherein the determining occurs during the performing; and prioritize command execution based upon the determination.
Iyigun discloses determine whether the command is a paging input/output (I/O) write command, wherein the determining occurs during the performing; and prioritize command execution based upon the determination [(Column 11, lines 19-43) wherein Iyigun teaches the memory manager can swap out of volatile memory to hybrid drive 102 an application, which refers to swapping out the private pages of an application that are not already stored in (backed by) a file. The memory manager can also swap in from hybrid drive 102 to volatile memory the application. The LBAs accessed as part of I/O accesses when swapping an application to or from hybrid drive 102 are assigned the priority level of the page or swap file priority category. During swapping in or out a page of memory or an application, I/O accesses are assigned the priority level of the page or swap file priority category. LBA priority record 206 need not be accessed to determine the priority level of LBAs during swapping in or out a page of memory or an application. Rather, I/O module 208 can be configured to assign the priority level of the page or swap file priority category to I/O accesses during swapping in or out a page of memory or an application without consulting LBA priority record 206. In one or more embodiments, the swapping in or out of a page of memory or an application is managed by one or more modules operating in a kernel mode of the operating system. These one or more modules can assign each I/O access they perform the priority level of the page or swap file priority category without consulting LBA priority record 206 to correspond to the claimed limitation].
D’Eliseo and Iyigun are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of D’Eliseo before him or her, to modify the device of D’Eliseo to include the of paging operations of Iyigun because it will enhance storage performance.
The motivation for doing so would be [“Performance improvements obtained by storing LBAs for random I/O accesses in performance part 112 are typically greater than when storing LBAs for sequential I/O accesses in part 114. Thus, by lowering the priority levels of LBAs for sequential I/O accesses, the LBAs for sequential I/O access are more likely to be stored in base part 114 than in performance part 112” (Column 15, lines 13-19 by Iyigun)].
Therefore, it would have been obvious to combine Iyigun and D’Eliseo to obtain the invention as specified in the instant claim.
Claims 2-4 are rejected under 35 U.S.C. 103(a) as being disclosed by D’Eliseo/ Iyigun, as applied to claim 1, in view of Benisty et al. (US PGPUB 2018/0321844 hereinafter referred to as Benisty).
As per dependent claim 2, D’Eliseo/ Iyigun discloses the data storage device of claim 1.
D’Eliseo/ Iyigun does not appear to explicitly disclose wherein the controller is further configured to determine whether the command is a read command or a write command.
Benisty discloses wherein the controller is further configured to determine whether the command is a read command or a write command [(Paragraphs 0036 and 0104) wherein Benisty teaches where the memory device may also prioritize based on a type of command (or a type of request). As discussed above, commands may necessitate different requests, such as a read request from the host device (e.g., a PCIe read request to read data from the host device) or a write request to the host device (e.g., a PCIe write request to write data to host device). There are different types of PCIe read requests including, without limitation: command fetching (e.g., the memory device reads a command from the submission queue resident on the host device); PRP fetching (e.g., the memory device, using a pointer, reads a PRP list from the host device); or data fetching (e.g., in an NVMe write command flow, the memory device reads data from the host that is to be written to flash memory) to correspond to the claimed limitation].
D’Eliseo/ Iyigun and Benisty are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of D’Eliseo/ Iyigun and Benisty before him or her, to modify the device of D’Eliseo/ Iyigun to include the determination of command type of Benisty because it will enhance storage performance.
The motivation for doing so would be [“the memory device may determine priority for communications separately for the ingress path and the egress path ” (Paragraph 0048 by Benisty)].
Therefore, it would have been obvious to combine D’Eliseo/ Iyigun and Benisty to obtain the invention as specified in the instant claim.
As per claim 3, D’Eliseo discloses wherein the controller is further configured to determine that the command is a read command [(Paragraphs 0016, 0036 and 0059; FIGs. 1 and 5 and related text) wherein D’Eliseo teaches cache agent 134 receives, from a requestor, such as cache manager 114, a series of multiple cache read commands (e.g., sequential read commands) requesting first data from a memory array of memory device 130 and spread across multiple memory planes. Cache agent 134 further receives, from the requestor, a cache read context switch command and a snap read command requesting second data from one of the plurality of memory planes of the memory array of memory device 130; cache agent 134 receives and processes memory access commands, such as read commands, cache read commands, cache read context switch commands, snap read commands, and cache read context restore commands. In one embodiment, cache agent 134 receives a series of multiple cache read commands (e.g., sequential read commands) requesting first data from memory array 250 and spread across multiple memory planes 372(0)-372(3) to correspond to the claimed limitation].
Iyigun teaches wherein the controller is configured to determine whether the read command is a new model load [(Column 11, lines 44-53) wherein Iyigun teaches Information collection module 202 obtains information identifying I/O accesses during launching of an application on the computing device. Launching an application on the computing device refers to starting running of the application on the computing device. The information can identify I/O accesses for a particular amount of time (e.g., five seconds) after beginning launching the application as I/O accesses during the launching of the application. Different information can be obtained by module 202 for each different application launched on the computing device to correspond to the claimed limitation].
As per claim 4, Iyigun discloses wherein the controller is configured to assign a higher priority to the new model load compared to a read command that is not the new model load [(Column 6, lines 64-67 and Column 7, lines 1-10) wherein Iyigun teaches the rules or criteria identify data to be assigned a particular priority level based on whether placing the data in performance part 112 is expected to increase the user-noticeable speed of the device (e.g., the speed at which a computing device boots or launches an application) and/or reduce the power consumption of the computing device. Additionally, the rules or criteria can identify data to be assigned a particular priority level so that there is a sufficient amount of data (e.g., 1 gigabyte or 4 gigabytes of data) at a lowest priority level in performance part 112 so that LBA data assigned the lowest priority level can be removed from performance part 112 and placed in base part 114 as desired (thus keeping LBA data with a higher priority level in performance part 112). Examples of these rules and criteria for particular priority categories are discussed in additional detail below to correspond to the claimed limitation].
Claims 5-11 are rejected under 35 U.S.C. 103(a) as being disclosed by D’Eliseo/ Iyigun, as applied to claim 1, in view of Benisty and further in view of Agarawal et al. (US PGPUB 2023/0325225 hereinafter referred to as Agarawal).
As per dependent claim 5, D’Eliseo/ Iyigun discloses the data storage device of claim 1.
D’Eliseo/ Iyigun does not appear to explicitly disclose wherein the controller is further configured to determine that the command is a write command.
Benisty discloses wherein the controller is further configured to determine that the command is a write command [(Paragraphs 0036 and 0104) wherein Benisty teaches where the memory device may also prioritize based on a type of command (or a type of request). As discussed above, commands may necessitate different requests, such as a read request from the host device (e.g., a PCIe read request to read data from the host device) or a write request to the host device (e.g., a PCIe write request to write data to host device). There are different types of PCIe read requests including, without limitation: command fetching (e.g., the memory device reads a command from the submission queue resident on the host device); PRP fetching (e.g., the memory device, using a pointer, reads a PRP list from the host device); or data fetching (e.g., in an NVMe write command flow, the memory device reads data from the host that is to be written to flash memory) to correspond to the claimed limitation].
D’Eliseo/ Iyigun and Benisty are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of D’Eliseo/ Iyigun and Benisty before him or her, to modify the device of D’Eliseo/ Iyigun to include the determination of command type of Benisty because it will enhance storage performance.
The motivation for doing so would be [“the memory device may determine priority for communications separately for the ingress path and the egress path ” (Paragraph 0048 by Benisty)].
D’Eliseo/ Iyigun does not appear to explicitly disclose wherein the controller is configured to determine whether the write command is from a host device memory range that is near a last model load read.
Agarawal discloses wherein the controller is configured to determine whether the write command is from a host device memory range that is near a last model load read [(Paragraphs 0032 and 0040) wherein Agarawal teaches wherein, in response to a read request for cache line CL $A, if the metatag portion, indicates that the near memory contains cache line CL $B, then that results in a miss. Accordingly, the internal memory controller sends a request for cache line CL $A to the far memory system. In addition, a blocking entry is set in the internal memory controller for the other cache line entry that maps to the near memory location; when a cache line is written to the memory, every write needs to be preceded by a read to ensure that the near memory location contains the address being written. Thus, the internal memory controller first issues a read command to read the data from the near memory, which happens to be the data being written so there is a hit. Next, the internal memory controller encrypts the data with the per-VM key (e.g., key A) and writes the data to the near memory. Finally, the internal memory controller sends the completion (CMP) message to the home agent to correspond to the claimed limitation].
D’Eliseo/ Iyigun and Agarawal are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of D’Eliseo/ Iyigun and Agarawal before him or her, to modify the device of D’Eliseo/ Iyigun to include the determination of memory location proximity of Agarawal because it will enhance storage performance.
The motivation for doing so would be [“mitigate this impact by ensuring that the hit rate for the near memory is high, such that fewer memory accesses require the swapping of the data between the near memory and the far memory” (Paragraph 0037 by Agarawal)].
Therefore, it would have been obvious to combine D’Eliseo/ Iyigun and Agarawal to obtain the invention as specified in the instant claim.
As per claim 6, Iyigun discloses wherein the controller is configured to assign a higher priority to write commands that are near the last model load read as compared to write commands that are not near the last model load read [(Column 11, lines 15-43) wherein Iyigun teaches the LBAs accessed as part of I/O accesses when swapping a page file to or from hybrid drive 102 are assigned the priority level of the page or swap file priority category; the memory manager can swap out of volatile memory to hybrid drive 102 an application, which refers to swapping out the private pages of an application that are not already stored in (backed by) a file. The memory manager can also swap in from hybrid drive 102 to volatile memory the application. The LBAs accessed as part of I/O accesses when swapping an application to or from hybrid drive 102 are assigned the priority level of the page or swap file priority category, where it will be obvious to one or ordinary skill in the art to modify the priority module of Iyigun to include the different priority levels as claimed to correspond to the claimed limitation].
As per claim 7, Iyigun discloses wherein the controller is configured to assign a higher priority to paging I/O write commands as compared to write commands that are not near the last model load read and are not paging I/O write commands [(Column 11, lines 15-43) wherein Iyigun teaches the LBAs accessed as part of I/O accesses when swapping a page file to or from hybrid drive 102 are assigned the priority level of the page or swap file priority category; the memory manager can swap out of volatile memory to hybrid drive 102 an application, which refers to swapping out the private pages of an application that are not already stored in (backed by) a file. The memory manager can also swap in from hybrid drive 102 to volatile memory the application. The LBAs accessed as part of I/O accesses when swapping an application to or from hybrid drive 102 are assigned the priority level of the page or swap file priority category, where it will be obvious to one or ordinary skill in the art to modify the priority module of Iyigun to include the different priority levels as claimed to correspond to the claimed limitation].
As per claim 8, D’Eliseo/ Iyigun does not appear to explicitly disclose write commands near a last model load read.
Agarawal discloses write commands near a last model load read [(Paragraphs 0032 and 0040) wherein Agarawal teaches wherein, in response to a read request for cache line CL $A, if the metatag portion, indicates that the near memory contains cache line CL $B, then that results in a miss. Accordingly, the internal memory controller sends a request for cache line CL $A to the far memory system. In addition, a blocking entry is set in the internal memory controller for the other cache line entry that maps to the near memory location; when a cache line is written to the memory, every write needs to be preceded by a read to ensure that the near memory location contains the address being written. Thus, the internal memory controller first issues a read command to read the data from the near memory, which happens to be the data being written so there is a hit. Next, the internal memory controller encrypts the data with the per-VM key (e.g., key A) and writes the data to the near memory. Finally, the internal memory controller sends the completion (CMP) message to the home agent to correspond to the claimed limitation].
D’Eliseo/ Iyigun and Agarawal are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filling date, it would have been obvious to one of ordinary skill in the art, having the teachings of D’Eliseo/ Iyigun and Agarawal before him or her, to modify the device of D’Eliseo/ Iyigun to include the determination of memory location proximity of Agarawal because it will enhance storage performance.
The motivation for doing so would be [“mitigate this impact by ensuring that the hit rate for the near memory is high, such that fewer memory accesses require the swapping of the data between the near memory and the far memory” (Paragraph 0037 by Agarawal)].
Iyigun discloses wherein the prioritizing comprises prioritizing write commands near a last model load read [(Column 6, lines 64-67 and Column 7, lines 1-10 and 55-67) wherein Iyigun teaches the rules or criteria identify data to be assigned a particular priority level based on whether placing the data in performance part 112 is expected to increase the user-noticeable speed of the device (e.g., the speed at which a computing device boots or launches an application) and/or reduce the power consumption of the computing device. Additionally, the rules or criteria can identify data to be assigned a particular priority level so that there is a sufficient amount of data (e.g., 1 gigabyte or 4 gigabytes of data) at a lowest priority level in performance part 112 so that LBA data assigned the lowest priority level can be removed from performance part 112 and placed in base part 114 as desired (thus keeping LBA data with a higher priority level in performance part 112). Examples of these rules and criteria for particular priority categories are discussed in additional detail below; Priority determination module 204 maintains an LBA priority record 206 identifying the priority levels assigned to particular LBAs. Generally, LBA priority record 206 identifies, for a given LBA, the priority level to which the LBA is assigned. In some situations, however, a particular LBA may be assigned to no priority level, in which case no identification of an assigned priority level may be included in LBA priority record 206 for the LBA, where it will be obvious to one or ordinary skill in the art to modify the priority module of Iyigun to include the different priority levels as claimed to correspond to the claimed limitation].
Benisty further teaches the prioritizing comprises prioritizing write commands that are paging I/O write commands, write commands that are not paging I/O write commands, read commands that are for model loading, and read commands that are not for model loading [(Paragraphs 0036 and 0104) wherein Benisty teaches where the memory device may also prioritize based on a type of command (or a type of request). As discussed above, commands may necessitate different requests, such as a read request from the host device (e.g., a PCIe read request to read data from the host device) or a write request to the host device (e.g., a PCIe write request to write data to host device). There are different types of PCIe read requests including, without limitation: command fetching (e.g., the memory device reads a command from the submission queue resident on the host device); PRP fetching (e.g., the memory device, using a pointer, reads a PRP list from the host device); or data fetching (e.g., in an NVMe write command flow, the memory device reads data from the host that is to be written to flash memory) to correspond to the claimed limitation].
As per claim 9, Iyigun discloses wherein write commands that are near the last model load read have a higher priority than write commands that are paging I/O write commands [(Column 11, lines 15-43) wherein Iyigun teaches the LBAs accessed as part of I/O accesses when swapping a page file to or from hybrid drive 102 are assigned the priority level of the page or swap file priority category; the memory manager can swap out of volatile memory to hybrid drive 102 an application, which refers to swapping out the private pages of an application that are not already stored in (backed by) a file. The memory manager can also swap in from hybrid drive 102 to volatile memory the application. The LBAs accessed as part of I/O accesses when swapping an application to or from hybrid drive 102 are assigned the priority level of the page or swap file priority category, where it will be obvious to one or ordinary skill in the art to modify the priority module of Iyigun to include the different priority levels as claimed to correspond to the claimed limitation], and wherein write commands that are paging I/O write commands have higher priority than write commands that are not paging I/O write commands [(Column 6, lines 64-67 and Column 7, lines 1-10 and 55-67) wherein Iyigun teaches the rules or criteria identify data to be assigned a particular priority level based on whether placing the data in performance part 112 is expected to increase the user-noticeable speed of the device (e.g., the speed at which a computing device boots or launches an application) and/or reduce the power consumption of the computing device. Additionally, the rules or criteria can identify data to be assigned a particular priority level so that there is a sufficient amount of data (e.g., 1 gigabyte or 4 gigabytes of data) at a lowest priority level in performance part 112 so that LBA data assigned the lowest priority level can be removed from performance part 112 and placed in base part 114 as desired (thus keeping LBA data with a higher priority level in performance part 112). Examples of these rules and criteria for particular priority categories are discussed in additional detail below; Priority determination module 204 maintains an LBA priority record 206 identifying the priority levels assigned to particular LBAs. Generally, LBA priority record 206 identifies, for a given LBA, the priority level to which the LBA is assigned. In some situations, however, a particular LBA may be assigned to no priority level, in which case no identification of an assigned priority level may be included in LBA priority record 206 for the LBA to correspond to the claimed limitation].
As per claim 10, Iyigun discloses wherein read commands that are for model loading have a higher priority than read commands that are not for model loading [(Column 6, lines 64-67 and Column 7, lines 1-10 and 55-67) wherein Iyigun teaches the rules or criteria identify data to be assigned a particular priority level based on whether placing the data in performance part 112 is expected to increase the user-noticeable speed of the device (e.g., the speed at which a computing device boots or launches an application) and/or reduce the power consumption of the computing device. Additionally, the rules or criteria can identify data to be assigned a particular priority level so that there is a sufficient amount of data (e.g., 1 gigabyte or 4 gigabytes of data) at a lowest priority level in performance part 112 so that LBA data assigned the lowest priority level can be removed from performance part 112 and placed in base part 114 as desired (thus keeping LBA data with a higher priority level in performance part 112). Examples of these rules and criteria for particular priority categories are discussed in additional detail below; Priority determination module 204 maintains an LBA priority record 206 identifying the priority levels assigned to particular LBAs. Generally, LBA priority record 206 identifies, for a given LBA, the priority level to which the LBA is assigned. In some situations, however, a particular LBA may be assigned to no priority level, in which case no identification of an assigned priority level may be included in LBA priority record 206 for the LBA, where it will be obvious to one or ordinary skill in the art to modify the priority module of Iyigun to include the different priority levels as claimed to correspond to the claimed limitation].
As per claim 11, Iyigun discloses wherein read commands that are for model loading have a higher priority than write commands that are not for paging I/O write commands [(Column 6, lines 64-67 and Column 7, lines 1-10 and 55-67) wherein Iyigun teaches the rules or criteria identify data to be assigned a particular priority level based on whether placing the data in performance part 112 is expected to increase the user-noticeable speed of the device (e.g., the speed at which a computing device boots or launches an application) and/or reduce the power consumption of the computing device. Additionally, the rules or criteria can identify data to be assigned a particular priority level so that there is a sufficient amount of data (e.g., 1 gigabyte or 4 gigabytes of data) at a lowest priority level in performance part 112 so that LBA data assigned the lowest priority level can be removed from performance part 112 and placed in base part 114 as desired (thus keeping LBA data with a higher priority level in performance part 112). Examples of these rules and criteria for particular priority categories are discussed in additional detail below; Priority determination module 204 maintains an LBA priority record 206 identifying the priority levels assigned to particular LBAs. Generally, LBA priority record 206 identifies, for a given LBA, the priority level to which the LBA is assigned. In some situations, however, a particular LBA may be assigned to no priority level, in which case no identification of an assigned priority level may be included in LBA priority record 206 for the LBA, where it will be obvious to one or ordinary skill in the art to modify the priority module of Iyigun to include the different priority levels as claimed to correspond to the claimed limitation].
Pertinent Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kan et al., US PGPUB 2022/ 0100256 – teaches REDUCING POWER CONSUMPTION OF MEMORY DEVICES AT AN INFORMATION HANDLING SYSTEM.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMED GEBRIL whose telephone number is (571)270-1857. The examiner can normally be reached on Monday-Friday, 8:00am-5:00pm.ALT. Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857.
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/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135
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