Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-8,10-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6,8-11 of U.S. Patent No. 12386704. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-6,8-11 of U.S. Patent No. 12386704 contain every element of claims 1-8,10-14 of the instant application and thus anticipate the claims of the instant application. Therefore, the claims of the instant application are not patentably distinct from the earlier patent claims and as such are unpatentable.
There is no double patenting rejection for claims 10,15,16.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Manganelli et al. (USPN 20210335432A1).
As per claim 1, Manganelli et al. discloses a controller comprising: a processing unit configured to: generate a command for controlling a program operation or a read operation of a semiconductor memory device (paragraph 0037 - The memory manager 125 can parse or format host commands (e.g., commands received from a host) into device commands (e.g., commands associated with operation of a memory array, etc.), or generate device commands (e.g., to accomplish various memory management functions) for the array controller 135 or one or more other components of the memory device 110.; paragraph 0039 - The array controller 135 can include, among other things, circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing one or more memory cells of the memory device 110 coupled to the memory controller 115. The memory operations can be based on, for example, host commands received from the host 105, or internally generated by the memory manager 125 (e.g., in association with wear leveling, error detection or correction, etc.).);
generate parity data corresponding to a weak page among a plurality of pages included in the semiconductor memory device; and recover data programmed in the weak page based on the parity data and data programmed in pages adjacent to the weak page when an uncorrectable error is included in the data programmed in the weak page (paragraph 0081 - The parity pages shown in FIG. 9 are parity pages that are calculated for the P.sub.n data items in FIGS. 7 and 8. As the data items are programmed to the NAND in FIG. 7, the parity can be calculated and stored in volatile memory (e.g., Random Access Memory). At a first time, T0, the portions of data items P.sub.1-P.sub.12 can be written to page lines 0-11 and plane 0-3 of die 700. At the same time, the parity values of these data items: 902-924 can be calculated and stored in volatile storage such as RAM, as shown in FIG. 9.;
paragraph 0084 - The parity data stored in RAM or in the SLC 1000 may be used to recover a page of user data. Turning back to FIG. 7, if plane 1 is corrupted (as shown in FIG. 5), only a single portion of the P.sub.n data items may be corrupted by virtue of the failure on plane 1. The system may utilize the parity data to recover these portions. A.sub.n individual portion of the user data may be recoverable by applying an XOR operation on the remaining pages and the parity page…. Similarly, if a page line is corrupted as shown in FIG. 6, only a single portion of the user data page may be lost. For example, if any one of page lines 0-3 of FIG. 7 are corrupted, only a single portion of a particular user page may be lost. For example, if the pages on page line 1 are corrupted, then the second portion of P.sub.1 715 is corrupted, but the first, second, and fourth portions are not and as a result, the third portion may be reconstructed using the parity value.;
paragraph 0040 - The array controller 135 can include an error correction code (ECC) component 140, which can include, among other things, an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of the memory device 110 coupled to the memory controller 115. The memory controller 115 can be configured to actively detect and recover from error occurrences (e.g., bit errors, operation errors, etc.) associated with various operations or storage of data, while maintaining integrity of the data transferred between the host 105 and the memory device 110, or maintaining integrity of stored data (e.g., using redundant RAID storage, etc.), and can remove (e.g., retire) failing memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.), and
a data storage configured to store the parity data (paragraph 0081 - The parity pages shown in FIG. 9 are parity pages that are calculated for the P.sub.n data items in FIGS. 7 and 8. As the data items are programmed to the NAND in FIG. 7, the parity can be calculated and stored in volatile memory (e.g., Random Access Memory). At a first time, T0, the portions of data items P.sub.1-P.sub.12 can be written to page lines 0-11 and plane 0-3 of die 700. At the same time, the parity values of these data items: 902-924 can be calculated and stored in volatile storage such as RAM, as shown in FIG. 9.).
As per claim 2, Manganelli et al. discloses wherein the processing unit generates the parity data based on the data programmed in the weak page and data programmed in one or more pages adjacent to the weak page (paragraph 0081 - The parity pages shown in FIG. 9 are parity pages that are calculated for the P.sub.n data items in FIGS. 7 and 8. As the data items are programmed to the NAND in FIG. 7, the parity can be calculated and stored in volatile memory (e.g., Random Access Memory). At a first time, T0, the portions of data items P.sub.1-P.sub.12 can be written to page lines 0-11 and plane 0-3 of die 700. At the same time, the parity values of these data items: 902-924 can be calculated and stored in volatile storage such as RAM, as shown in FIG. 9.;
Paragraph 0071 - For example, in some examples, the first and second portions may be stored adjacent to each other in terms of being stored in adjacent page lines and adjacent planes (e.g., as shown in FIG. 7). As used herein, adjacent means a next page line and/or plane in sequence. In some examples, the second and third portions may be stored adjacent to each other in terms of being stored in adjacent page lines and adjacent planes. In some examples, the third and fourth portions may be stored adjacent to each other in terms of being stored in adjacent page lines and adjacent planes. See for example, FIGS. 1, 710, 715, 720, and 725 (discussed in more detail below). The portions of data are thus stored so that corruption on a single plane or a single word line does not corrupt more than a single portion of the data.;
paragraph 0073 - As shown in FIG. 7, in one example improved NAND data placement schema, the portions are striped diagonally such that each portion of a particular data item P.sub.x is on a different plane and a different page from the other portions.;
paragraph 0040 - The array controller 135 can include an error correction code (ECC) component 140, which can include, among other things, an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of the memory device 110 coupled to the memory controller 115. The memory controller 115 can be configured to actively detect and recover from error occurrences (e.g., bit errors, operation errors, etc.) associated with various operations or storage of data, while maintaining integrity of the data transferred between the host 105 and the memory device 110, or maintaining integrity of stored data (e.g., using redundant RAID storage, etc.), and can remove (e.g., retire) failing memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.).
As per claim 6, Manganelli et al. discloses wherein the processing unit: generates the parity data by performing an exclusive-OR (XOR) operation on the data programmed in the weak page and the data programmed in the pages adjacent to the weak page (paragraph 0081 - The parity pages shown in FIG. 9 are parity pages that are calculated for the P.sub.n data items in FIGS. 7 and 8. As the data items are programmed to the NAND in FIG. 7, the parity can be calculated and stored in volatile memory (e.g., Random Access Memory). At a first time, T0, the portions of data items P.sub.1-P.sub.12 can be written to page lines 0-11 and plane 0-3 of die 700. At the same time, the parity values of these data items: 902-924 can be calculated and stored in volatile storage such as RAM, as shown in FIG. 9.;
paragraph 0040 - The array controller 135 can include an error correction code (ECC) component 140, which can include, among other things, an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of the memory device 110 coupled to the memory controller 115. The memory controller 115 can be configured to actively detect and recover from error occurrences (e.g., bit errors, operation errors, etc.) associated with various operations or storage of data, while maintaining integrity of the data transferred between the host 105 and the memory device 110, or maintaining integrity of stored data (e.g., using redundant RAID storage, etc.), and can remove (e.g., retire) failing memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.); and
stores a weak page information for identifying weak pages among the plurality of pages and the parity data in the data storage (paragraph 0038 – The memory manager 125 can include a set of management tables 130 configured to maintain various information associated with one or more component of the memory device 110 (e.g., various information associated with a memory array or one or more memory cells coupled to the memory controller 115). For example, the management tables 130 can include information regarding block age, block erase count, error history, or one or more error counts (e.g., a write operation error count, a read bit error count, a read operation error count, an erase error count, etc.) for one or more blocks of memory cells coupled to the memory controller 115.).
As per claim 7, Manganelli et al. discloses wherein the processing unit generates the command for controlling the semiconductor memory device to read data stored in the weak page (paragraph 0037 - The memory manager 125 can parse or format host commands (e.g., commands received from a host) into device commands (e.g., commands associated with operation of a memory array, etc.), or generate device commands (e.g., to accomplish various memory management functions) for the array controller 135 or one or more other components of the memory device 110.; paragraph 0039 - The array controller 135 can include, among other things, circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing one or more memory cells of the memory device 110 coupled to the memory controller 115. The memory operations can be based on, for example, host commands received from the host 105, or internally generated by the memory manager 125 (e.g., in association with wear leveling, error detection or correction, etc.).).
As per claim 8, Manganelli et al. discloses wherein the processing unit recovers the data programmed in the weak page by performing an exclusive-OR (XOR) operation on the parity data and the data programmed in the pages adjacent to the weak page (paragraph 0081 - The parity pages shown in FIG. 9 are parity pages that are calculated for the P.sub.n data items in FIGS. 7 and 8. As the data items are programmed to the NAND in FIG. 7, the parity can be calculated and stored in volatile memory (e.g., Random Access Memory). At a first time, T0, the portions of data items P.sub.1-P.sub.12 can be written to page lines 0-11 and plane 0-3 of die 700. At the same time, the parity values of these data items: 902-924 can be calculated and stored in volatile storage such as RAM, as shown in FIG. 9.;
Paragraph 0071 - For example, in some examples, the first and second portions may be stored adjacent to each other in terms of being stored in adjacent page lines and adjacent planes (e.g., as shown in FIG. 7). As used herein, adjacent means a next page line and/or plane in sequence. In some examples, the second and third portions may be stored adjacent to each other in terms of being stored in adjacent page lines and adjacent planes. In some examples, the third and fourth portions may be stored adjacent to each other in terms of being stored in adjacent page lines and adjacent planes. See for example, FIGS. 1, 710, 715, 720, and 725 (discussed in more detail below). The portions of data are thus stored so that corruption on a single plane or a single word line does not corrupt more than a single portion of the data.;
paragraph 0073 - As shown in FIG. 7, in one example improved NAND data placement schema, the portions are striped diagonally such that each portion of a particular data item P.sub.x is on a different plane and a different page from the other portions.;
paragraph 0040 - The array controller 135 can include an error correction code (ECC) component 140, which can include, among other things, an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of the memory device 110 coupled to the memory controller 115. The memory controller 115 can be configured to actively detect and recover from error occurrences (e.g., bit errors, operation errors, etc.) associated with various operations or storage of data, while maintaining integrity of the data transferred between the host 105 and the memory device 110, or maintaining integrity of stored data (e.g., using redundant RAID storage, etc.), and can remove (e.g., retire) failing memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.).
As per claim 9, Manganelli et al. discloses a method of operating a controller, the method comprising:
determining whether to program data to a selected page among a plurality of pages included in a semiconductor memory device (paragraph 0040 - The array controller 135 can include an error correction code (ECC) component 140, which can include, among other things, an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of the memory device 110 coupled to the memory controller 115. The memory controller 115 can be configured to actively detect and recover from error occurrences (e.g., bit errors, operation errors, etc.) associated with various operations or storage of data, while maintaining integrity of the data transferred between the host 105 and the memory device 110, or maintaining integrity of stored data (e.g., using redundant RAID storage, etc.), and can remove (e.g., retire) failing memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.);
determining whether the selected page is a weak page (paragraph 0084 - The parity data stored in RAM or in the SLC 1000 may be used to recover a page of user data. Turning back to FIG. 7, if plane 1 is corrupted (as shown in FIG. 5), only a single portion of the P.sub.n data items may be corrupted by virtue of the failure on plane 1. The system may utilize the parity data to recover these portions. A.sub.n individual portion of the user data may be recoverable by applying an XOR operation on the remaining pages and the parity page…. Similarly, if a page line is corrupted as shown in FIG. 6, only a single portion of the user data page may be lost. For example, if any one of page lines 0-3 of FIG. 7 are corrupted, only a single portion of a particular user page may be lost. For example, if the pages on page line 1 are corrupted, then the second portion of P.sub.1 715 is corrupted, but the first, second, and fourth portions are not and as a result, the third portion may be reconstructed using the parity value.);
generating parity data based on data programmed in the selected page and data programmed in one or more pages adjacent to the selected page when the selected page is determined as the weak page (paragraph 0084 - The parity data stored in RAM or in the SLC 1000 may be used to recover a page of user data. Turning back to FIG. 7, if plane 1 is corrupted (as shown in FIG. 5), only a single portion of the P.sub.n data items may be corrupted by virtue of the failure on plane 1. The system may utilize the parity data to recover these portions. A.sub.n individual portion of the user data may be recoverable by applying an XOR operation on the remaining pages and the parity page…. Similarly, if a page line is corrupted as shown in FIG. 6, only a single portion of the user data page may be lost. For example, if any one of page lines 0-3 of FIG. 7 are corrupted, only a single portion of a particular user page may be lost. For example, if the pages on page line 1 are corrupted, then the second portion of P.sub.1 715 is corrupted, but the first, second, and fourth portions are not and as a result, the third portion may be reconstructed using the parity value.);
recovering data programmed in the weak page based on the parity data and data programmed in pages adjacent to the weak page in response to identifying that an uncorrectable error is included in the data programmed in the weak page (paragraph 0081 - The parity pages shown in FIG. 9 are parity pages that are calculated for the P.sub.n data items in FIGS. 7 and 8. As the data items are programmed to the NAND in FIG. 7, the parity can be calculated and stored in volatile memory (e.g., Random Access Memory). At a first time, T0, the portions of data items P.sub.1-P.sub.12 can be written to page lines 0-11 and plane 0-3 of die 700. At the same time, the parity values of these data items: 902-924 can be calculated and stored in volatile storage such as RAM, as shown in FIG. 9.;
paragraph 0084 - The parity data stored in RAM or in the SLC 1000 may be used to recover a page of user data. Turning back to FIG. 7, if plane 1 is corrupted (as shown in FIG. 5), only a single portion of the P.sub.n data items may be corrupted by virtue of the failure on plane 1. The system may utilize the parity data to recover these portions. A.sub.n individual portion of the user data may be recoverable by applying an XOR operation on the remaining pages and the parity page…. Similarly, if a page line is corrupted as shown in FIG. 6, only a single portion of the user data page may be lost. For example, if any one of page lines 0-3 of FIG. 7 are corrupted, only a single portion of a particular user page may be lost. For example, if the pages on page line 1 are corrupted, then the second portion of P.sub.1 715 is corrupted, but the first, second, and fourth portions are not and as a result, the third portion may be reconstructed using the parity value.;
paragraph 0040 - The array controller 135 can include an error correction code (ECC) component 140, which can include, among other things, an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of the memory device 110 coupled to the memory controller 115. The memory controller 115 can be configured to actively detect and recover from error occurrences (e.g., bit errors, operation errors, etc.) associated with various operations or storage of data, while maintaining integrity of the data transferred between the host 105 and the memory device 110, or maintaining integrity of stored data (e.g., using redundant RAID storage, etc.), and can remove (e.g., retire) failing memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.).
As per claim 12, Manganelli et al. discloses further comprising storing the parity data in the controller (paragraph 0081 - FIG. 9 illustrates a logical placement of the parity pages in a volatile memory of the controller or other component of the NAND according to some examples of the present disclosure. The parity pages shown in FIG. 9 are parity pages that are calculated for the P.sub.n data items in FIGS. 7 and 8. As the data items are programmed to the NAND in FIG. 7, the parity can be calculated and stored in volatile memory (e.g., Random Access Memory). At a first time, T0, the portions of data items P.sub.1-P.sub.12 can be written to page lines 0-11 and plane 0-3 of die 700. At the same time, the parity values of these data items: 902-924 can be calculated and stored in volatile storage such as RAM, as shown in FIG. 9.).
As per claim 15, Manganelli et al. discloses further comprising controlling the semiconductor memory device to read the data programmed in the weak page again when the recovering is failed (paragraph 0040 - The array controller 135 can include an error correction code (ECC) component 140, which can include, among other things, an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of the memory device 110 coupled to the memory controller 115. The memory controller 115 can be configured to actively detect and recover from error occurrences (e.g., bit errors, operation errors, etc.) associated with various operations or storage of data, while maintaining integrity of the data transferred between the host 105 and the memory device 110, or maintaining integrity of stored data (e.g., using redundant RAID storage, etc.), and can remove (e.g., retire) failing memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5,13,14 are rejected under 35 U.S.C. 103 as being unpatentable over Manganelli et al. (USPN 20210335432A1) in view of McGlaughlin et al. (USPN 20160364181A1).
As per claim 5, Manganelli et al. discloses wherein the processing unit generates the command for controlling the semiconductor memory device (paragraph 0037 - The memory manager 125 can parse or format host commands (e.g., commands received from a host) into device commands (e.g., commands associated with operation of a memory array, etc.), or generate device commands (e.g., to accomplish various memory management functions) for the array controller 135 or one or more other components of the memory device 110.).
Manganelli et al. fails to explicitly state program the parity data to a memory block different from a memory block including the weak page.
Manganelli et al. does disclose in paragraph 0084 - The parity data stored in RAM or in the SLC 1000 may be used to recover a page of user data. Turning back to FIG. 7, if plane 1 is corrupted (as shown in FIG. 5), only a single portion of the P.sub.n data items may be corrupted by virtue of the failure on plane 1. The system may utilize the parity data to recover these portions. A.sub.n individual portion of the user data may be recoverable by applying an XOR operation on the remaining pages and the parity page…. Similarly, if a page line is corrupted as shown in FIG. 6, only a single portion of the user data page may be lost. For example, if any one of page lines 0-3 of FIG. 7 are corrupted, only a single portion of a particular user page may be lost. For example, if the pages on page line 1 are corrupted, then the second portion of P.sub.1 715 is corrupted, but the first, second, and fourth portions are not and as a result, the third portion may be reconstructed using the parity value.
McGlaughlin et al. discloses program the parity data to a memory block different from a memory block including the weak page paragraph 0030 - The second level error detection circuitry can detect errors that are not correctable by the first level error detection, e.g., uncorrectable error correction code (UECC) errors, such as by determining that there are more than a threshold amount of correctable errors. Second level error detection circuitry can include RAID exclusive or (XOR) circuitry.; paragraph 0032 - In a number of embodiments, the second stripe map 122 can be used by second level error detection circuitry to perform a RAID read error recovery operation. A RAID read error recovery operation can be performed when an UECC error occurs and data from a bad page that is part of one or more stripes in memory devices 110-1, . . . , 110-N can be moved to different pages. A bad page can be a page where a UECC error occurs when performing a read operation. The RAID read error recovery operation can use the second stripe map 122 by locating the page identifier of the bad page in the second stripe map 122 and determine the stripes in memory devices 110-1, . . . , 110-N that included the bad page. The stripes that are identified by the second stripe map 122 as including the bad page can be updated so that the data from the bad page is recovered using parity data and the data is moved to a different page in memory devices 110-1, . . . , 110-N.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the data is moved to a different page in memory devices of McGlaughlin in the reconstructing using parity of Manganelli. A person of ordinary skill in the art would have been motivated to make the modification because the data is able to be used for future use.
As per claim 13, Manganelli et al. fails to explicitly state controlling the semiconductor memory device to program the parity data to a memory block different from a memory block including the weak page.
Manganelli et al. does disclose in paragraph 0084 - The parity data stored in RAM or in the SLC 1000 may be used to recover a page of user data. Turning back to FIG. 7, if plane 1 is corrupted (as shown in FIG. 5), only a single portion of the P.sub.n data items may be corrupted by virtue of the failure on plane 1. The system may utilize the parity data to recover these portions. A.sub.n individual portion of the user data may be recoverable by applying an XOR operation on the remaining pages and the parity page…. Similarly, if a page line is corrupted as shown in FIG. 6, only a single portion of the user data page may be lost. For example, if any one of page lines 0-3 of FIG. 7 are corrupted, only a single portion of a particular user page may be lost. For example, if the pages on page line 1 are corrupted, then the second portion of P.sub.1 715 is corrupted, but the first, second, and fourth portions are not and as a result, the third portion may be reconstructed using the parity value.
McGlaughlin et al. discloses controlling the semiconductor memory device to program the parity data to a memory block different from a memory block including the weak page paragraph 0030 - The second level error detection circuitry can detect errors that are not correctable by the first level error detection, e.g., uncorrectable error correction code (UECC) errors, such as by determining that there are more than a threshold amount of correctable errors. Second level error detection circuitry can include RAID exclusive or (XOR) circuitry.; paragraph 0032 - In a number of embodiments, the second stripe map 122 can be used by second level error detection circuitry to perform a RAID read error recovery operation. A RAID read error recovery operation can be performed when an UECC error occurs and data from a bad page that is part of one or more stripes in memory devices 110-1, . . . , 110-N can be moved to different pages. A bad page can be a page where a UECC error occurs when performing a read operation. The RAID read error recovery operation can use the second stripe map 122 by locating the page identifier of the bad page in the second stripe map 122 and determine the stripes in memory devices 110-1, . . . , 110-N that included the bad page. The stripes that are identified by the second stripe map 122 as including the bad page can be updated so that the data from the bad page is recovered using parity data and the data is moved to a different page in memory devices 110-1, . . . , 110-N.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the data is moved to a different page in memory devices of McGlaughlin in the reconstructing using parity of Manganelli. A person of ordinary skill in the art would have been motivated to make the modification because the data is able to be used for future use.
As per claim 14, Manganelli et al. discloses wherein the memory block including the weak page includes single-level cells (SLCs) (paragraph 0042 - In some examples, a memory device, or a portion thereof, may be selectively operated in SLC mode).
Manganelli et al. fails to explicitly state the memory block different from the memory block.
Manganelli et al. does disclose in paragraph 0084 - The parity data stored in RAM or in the SLC 1000 may be used to recover a page of user data. Turning back to FIG. 7, if plane 1 is corrupted (as shown in FIG. 5), only a single portion of the P.sub.n data items may be corrupted by virtue of the failure on plane 1. The system may utilize the parity data to recover these portions. A.sub.n individual portion of the user data may be recoverable by applying an XOR operation on the remaining pages and the parity page…. Similarly, if a page line is corrupted as shown in FIG. 6, only a single portion of the user data page may be lost. For example, if any one of page lines 0-3 of FIG. 7 are corrupted, only a single portion of a particular user page may be lost. For example, if the pages on page line 1 are corrupted, then the second portion of P.sub.1 715 is corrupted, but the first, second, and fourth portions are not and as a result, the third portion may be reconstructed using the parity value.
McGlaughlin et al. discloses the memory block different from the memory block paragraph 0030 - The second level error detection circuitry can detect errors that are not correctable by the first level error detection, e.g., uncorrectable error correction code (UECC) errors, such as by determining that there are more than a threshold amount of correctable errors. Second level error detection circuitry can include RAID exclusive or (XOR) circuitry.; paragraph 0032 - In a number of embodiments, the second stripe map 122 can be used by second level error detection circuitry to perform a RAID read error recovery operation. A RAID read error recovery operation can be performed when an UECC error occurs and data from a bad page that is part of one or more stripes in memory devices 110-1, . . . , 110-N can be moved to different pages. A bad page can be a page where a UECC error occurs when performing a read operation. The RAID read error recovery operation can use the second stripe map 122 by locating the page identifier of the bad page in the second stripe map 122 and determine the stripes in memory devices 110-1, . . . , 110-N that included the bad page. The stripes that are identified by the second stripe map 122 as including the bad page can be updated so that the data from the bad page is recovered using parity data and the data is moved to a different page in memory devices 110-1, . . . , 110-N.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the data is moved to a different page in memory devices of McGlaughlin in the reconstructing using parity of Manganelli. A person of ordinary skill in the art would have been motivated to make the modification because the data is able to be used for future use.
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Manganelli et al. (USPN 20210335432A1) in view of Lee et al. (USPN 20140101519A1).
As per claim 16, Manganelli et al. fails to explicitly state wherein the semiconductor memory device is controlled to read the data programmed in the weak page again by changing a read voltage.
Manganelli et al. does disclose in paragraph 0040 - The array controller 135 can include an error correction code (ECC) component 140, which can include, among other things, an ECC engine or other circuitry configured to detect or correct errors associated with writing data to or reading data from one or more memory cells of the memory device 110 coupled to the memory controller 115. The memory controller 115 can be configured to actively detect and recover from error occurrences (e.g., bit errors, operation errors, etc.) associated with various operations or storage of data, while maintaining integrity of the data transferred between the host 105 and the memory device 110, or maintaining integrity of stored data (e.g., using redundant RAID storage, etc.), and can remove (e.g., retire) failing memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.
Lee et al. discloses wherein the semiconductor memory device is controlled to read the data programmed in the weak page again by changing a read voltage in paragraph 0126 - Where uncorrectable errors occur in at least one ECC unit, a read retry operation for re-reading data of the corresponding ECC unit is performed, and thus the level of the read voltage is changed (S34). The level of an optimal read voltage for each ECC unit is set in the memory system and the operation of changing the level of the read voltage may include an operation of selecting the level of the read voltage corresponding to the ECC unit in which uncorrectable error have occurred. Data of the first page is re-read by the level-changed read voltage (S35), and it is determined whether or not the ECC unit in which error detection/correction and error correction for the re-read data has failed exists.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include changing of read voltage to correct an error of McGlaughlin in the ECC engine to detect/correct errors of Manganelli. A person of ordinary skill in the art would have been motivated to make the modification because re-reading data by changing a read voltage is a method of correcting an error, as disclosed in paragraph 0126.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: ‘data recovery manager’ in claim 3.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claims disclose the limitation ‘data recovery manager’. The Examiner is unsure based on the specification as to what structure constitutes ‘data recovery manager’ such as software/hardware/firmware. Please clarify.
Claim Objections
Claim 3 is objected to because of the following informalities: ‘the data recovery manager’ should be: ‘a data recovery manager’. In addition, the Examiner believes that the ‘data recovery manager’ should be in the claims since this is the only claim with the ‘data recovery manager’ and it was removed in the parent application. Appropriate correction is required.
There is no prior art rejection for claims 3,4,10,11 because either no reason to combine with prior art found or no prior art could be found.
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/Yolanda L Wilson/ Primary Examiner, Art Unit 2113
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