Office Action Predictor
Last updated: April 16, 2026
Application No. 19/266,589

PHOTONIC COMMUNICATION PLATFORM

Non-Final OA §102§103§DP
Filed
Jul 11, 2025
Examiner
SMITH, CHAD
Art Unit
2874
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Lightmatter, INC.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
711 granted / 903 resolved
+10.7% vs TC avg
Strong +20% interview lift
Without
With
+20.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
31 currently pending
Career history
934
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
44.4%
+4.4% vs TC avg
§102
42.0%
+2.0% vs TC avg
§112
10.5%
-29.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 903 resolved cases

Office Action

§102 §103 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Allowable Subject Matter Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record, taken alone or in combination, fails to disclose or render obvious forming a first silicon nitride waveguide in the first photonic module using a fifth photomask; and subsequent to forming the first silicon nitride waveguide in the first photonic module, forming a second silicon nitride waveguide in the second photonic module using the fifth photomask. The closest relevant prior art of record, Seok et al. (U.S. PG Pub. # 2021/0191046 A1), teaches using germanium or silicon nitride (par. 00051) as the waveguide, but fails to teach or suggest using both materials to form waveguides. Thus, with no teaching from the prior art, and without the benefit of applicant's teachings, there is no motivation for one of ordinary skill in the art to combine/modify the prior art of record in a manner so as to create the claimed invention. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1, 3 and 4 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and 5 – 8 of U.S. Patent No. 12,092,866 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1 and 5 – 8 of U.S. Patent No. 12,092,866 B2 at least disclose or suggest all of the limitations of claims 1, 3 and 4 of the instant application. Claims 1, 5 and 6 of ‘866 teaches the method of claim 1 of the instant application, whereby the boundaries of ‘866 are inherently areas and patterning as claimed in claim 7 and 8 of ‘866 is inherently subsequent as claim 1 of ‘866 teaches a stepper and steppers pattern modules subsequently. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 11 and 14 – 17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Seok et al. (U.S. PG Pub. # 2021/0191046 A1). In Re claim 11, ‘046 teaches a method for fabricating a photonic system, comprising: using a stepper machine (pars. 0042, 0093) to lithographically pattern a semiconductor wafer (110) with a plurality of photonic modules (102) arranged in a two-dimensional scheme (fig. 1A), wherein patterning the semiconductor wafer comprises: forming a first photonic module (one of 102) by patterning a first area of the semiconductor wafer using a first photomask (pars. 0011, 0042), wherein the first photomask defines optical waveguides (116); subsequent to forming the first photonic module, forming a second photonic module by patterning a second area of the semiconductor wafer using the first photomask (pars. 0011, 0042, on another of 102); and subsequent to forming the second photonic module, forming a third photonic module by patterning a third area (pars. 0093) of the semiconductor wafer using the first photomask (pars. 0042, 0101), wherein the first area of the semiconductor wafer is adjacent to both the second and third areas of the semiconductor wafer such that, when formed, the first photonic module is optically coupled to the second photonic module in a first direction and to the third photonic module in a second direction perpendicular to the first direction (figs. 1A, 6, pars. 0048). In Re claim 14, ‘046 teaches forming a first germanium region (pars. 0051) in the first photonic module using a second photomask (mask layer 116 – 2, par. 0086); subsequent to forming the first germanium region in the first photonic module, forming a second germanium region in the second photonic module using the second photomask; and subsequent to forming the second germanium region in the second photonic module, forming a third germanium region in the third photonic module using the second photomask (par. 0048). In Re claim 15, ‘046 teaches wherein, when formed, the first photonic module comprises a first waveguide and the second photonic module comprises a second waveguide, wherein the first waveguide is coupled to the second waveguide (fig. 7). In Re claim 16, ‘046 wherein the first waveguide is physically connected to the second waveguide (fig. 7). In Re claim 17, ‘046 teaches wherein the first waveguide is separated from the second waveguide by a gap (interpreted as 116A as 602-1,1 to 116B of 602-1,3). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1 – 4, 6 – 10, 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Seok et al. (U.S. PG Pub. # 2021/0191046 A1) and evidenced by Seok et al. (U.S. PG Pub. # 2019/0153775 A1). In Re claims 1 – 3 and 9, ‘046 teaches a method for fabricating a photonic system, comprising: using a stepper machine (pars. 0042, 0093) to lithographically pattern a semiconductor wafer (110) with a plurality of photonic modules (102 or at least one switch and one bus waveguide 116), wherein patterning the semiconductor wafer comprises: forming a first photonic module (one of 102) by patterning a first area of the semiconductor wafer using a first photomask (pars. 0011, 0042), wherein the first photomask defines optical waveguides (116); subsequent to forming the first photonic module, forming a second photonic module by patterning a second area of the semiconductor wafer using the first photomask (pars. 0011, 0042, on another of 102), wherein the second area of the semiconductor wafer is adjacent to the first area of the semiconductor wafer such that, when formed, the first photonic module and the second photonic module are optically coupled to each other (par.0095). Furthermore, ‘046 teaches that actuators of the modules 102 are manufactured as disclosed in WO2018/49345 (par. 0073, and also published as U.S. PG Pub. # 2019/0153775 A1), whereby electrodes of actuators are patterned and then the electrodes are doped with ion implantation (pars. 0083 and 0084 of ‘775). ‘046 is silent to doping the first photonic module using a second photomask, wherein the second photomask defines doping regions; and subsequent to doping the first photonic module, doping the second photonic module using the second photomask; forming first metal pads in the first photonic module using a third photomask; and subsequent to forming the first metal pads in the first photonic module, forming second metal pads in the second photonic module using the third photomask, wherein the first and second metal pads are sized to bond to electronic chips; forming first metal traces in the first photonic module using a third photomask; and subsequent to forming the first metal traces in the first photonic module, forming second metal traces in the second photonic module using the third photomask; wherein doping the first photonic module comprises p-doping the first photonic module and doping the second photonic module comprises p-doping the second photonic module, wherein the method further comprises: n-doping the first photonic module using a third photomask, wherein the third photomask defines doping regions; and subsequent to n-doping the first photonic module, n-doping the second photonic module using the third photomask. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of ‘046 to have another mask of the reticle (par. 0040) to have a pattern to allow for forming of electrodes (aka metal pads or traces) by doping of electrode material and another mask of the reticle to have a pattern to allow for ion implantation of the electrodes of the actuators of ‘046 whereby the electrodes are doped with n and p type material to allow for more conductive electrodes whereby the process of the doping is as claimed, so as to allow for accurate doping of each region of a module thus allowing for more reliable modules as a person with ordinary skill has good reason to pursue the known options within his or her technical grasp. In Re claims 12 and 13, ‘046 teaches the method of claim 11 and that actuators of the modules 102 are manufactured as disclosed in WO2018/49345 (par. 0073, and also published as U.S. PG Pub. # 2019/0153775 A1), whereby electrodes of actuators are patterned and then the electrodes are doped with ion implantation (pars. 0083 and 0084 of ‘775). ‘046 is silent to a second photomask, wherein the second photomask defines doping regions; subsequent to doping the first photonic module, doping the second photonic module using the second photomask; and subsequent to doping the second photonic module, doping the third photonic module using the second photomask; wherein doping the first photonic module comprises p-doping the first photonic module, doping the second photonic module comprises p-doping the second photonic module, and doping the third photonic module comprises p-doping the third photonic module, wherein the method further comprises: n-doping the first photonic module using a third photomask, wherein the third photomask defines doping regions; subsequent to n-doping the first photonic module, n-doping the second photonic module using the third photomask; and10887290.1 subsequent to n-doping the second photonic module, n-doping the third photonic module using the third photomask It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of ‘046 to have a second mask of the reticle (par. 0040) to have a pattern to allow for forming of electrodes by doping of electrode material and a third mask of the reticle to have a pattern to allow for ion implantation of the electrodes of the actuators of ‘046 whereby the electrodes are doped with n and p type material to allow for more conductive electrodes whereby the process of the doping is as claimed so as to allow for accurate doping of each region of a module thus allowing for more reliable modules as a person with ordinary skill has good reason to pursue the known options within his or her technical grasp. In Re claim 4, ‘046 teaches forming another bus waveguide 116 (a vertical waveguide) of each module of germanium (0051), but is expressly silent to fourth mask as claimed. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of ‘046 to use a fourth mask to manufacture another crossing bus waveguide 116 so as to ensure accurate alignment by using a mask for each level as seen in figs. 3A and 3B to ensure optimum optical coupling as a person with ordinary skill has good reason to pursue the known options within his or her technical grasp. In Re claims 6 – 8 and 10, ‘046 teaches bus waveguides connecting as claimed (par. 0105, fig. 7) and that shunt waveguide of one module (fig. 3B) is gapped from bus waveguide of another module and a 2D scheme (fig. 6). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHAD SMITH whose telephone number is (571)270-1294. The examiner can normally be reached M-F 7:30 - 5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 1-571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHAD H SMITH/ Primary Examiner, Art Unit 2874
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Prosecution Timeline

Jul 11, 2025
Application Filed
Jan 16, 2026
Non-Final Rejection — §102, §103, §DP
Apr 06, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
99%
With Interview (+20.5%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 903 resolved cases by this examiner. Grant probability derived from career allow rate.

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