DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 3, 8, 10, 15, 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,360,893. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following analysis:
Instant application 19/267,756.
U.S. Patent 12,360,893.
1. A circuit device comprising: a first address translation circuit capable of: receiving a first address; determining, based on the first address, a first portion of a second address; and providing the first portion of the second address; and a second address translation circuit coupled to the first address translation circuit and capable of: determining, based on the first address, a second portion of the second address; and combining the first portion of the second address with the second portion of the second address; and providing the second address.
1.A method, comprising: receiving, from a primary device, a logical address; determining an address header based on the logical address; determining an offset value based on the address header; applying the offset value to a first portion of the logical address to create an offset address portion; generating a physical address that includes the address header and the offset address portion; accessing a physical resource using the physical address; and identifying, based on the address header, an offset module used to determine the offset value, wherein the offset module corresponds to the physical resource; and providing the address header to the identified offset module, wherein determining the address header, identifying the offset module, determining the offset value, and applying the offset value to the first portion of the logical address occurs within one clock cycle.
Claims 15, 20, and 27
3. The circuit device of claim 1, wherein the first address translation circuit is capable of determining, based on the first address, a security type.
3. The method of claim 1, wherein the logical address indicates a physical resource type, wherein determining the address header comprises determining the address header based on the physical resource type.
5. The method of claim 3, wherein the logical address further indicates a security type, wherein determining the address header comprises determining the address header based on the security type.
8. The circuit device of claim 1, wherein the determining of the first portion of the second address, the providing of the first portion of the second address, and the determining of the second portion of the second address are performed within one clock cycle.
7. The method of claim 1, wherein determining the address header and identifying the offset module occurs within a first edge of the one clock cycle, and wherein determining the offset value and applying the offset value to the first portion of the logical address occurs within a second edge of the one clock cycle.
10. A circuit device comprising: a processor device capable of providing a request that specifies a first address; a first address translation circuit coupled to the processor device; and a set of address translation circuits coupled to the first address translation circuit, wherein: the first address translation circuit is capable of: receiving the first address; determining, based on the first address, a first portion of a second address; selecting, based on the first address, a second address translation circuit from among the set of address translation circuits; and2 providing the first portion of the second address to the second address translation circuit; and the second address translation circuit is capable of: determining, based on the first address, a second portion of the second address; and combining the first portion of the second address with the second portion of the second address; and providing the second address.
27. An electronic circuit, comprising: a conversion circuit; and a plurality of offset circuits, each offset circuit of the plurality of offset circuits coupled to the conversion circuit; wherein the conversion circuit comprises: an interface device configured to receive a logical address from a primary device; and a first selector device configured to select a first offset circuit from the plurality of offset circuits based on the logical address and provide a first portion of the logical address to the first offset circuit; wherein each offset circuit of the plurality of offset circuits comprises: a storage device configured to store an offset value associated with a physical resource; and an adder device configured to add the offset value with the first portion of the logical address to generate an offset address portion; and wherein the electronic circuit is configured to provide a physical address that includes the offset address portion.
15. A method comprising: receiving a first request that specifies a first address; based on the first address: determining a first portion of a second address; selecting an address translation circuit from among a set of address translation circuits; and providing the first portion of the second address to the selected address translation circuit; determining, by the selected address translation circuit and based on the first address, a second portion of the second address; and combining the first portion of the second address with the second portion of the second address; and performing a memory transaction using the second address.
1.A method, comprising: receiving, from a primary device, a logical address; determining an address header based on the logical address; determining an offset value based on the address header; applying the offset value to a first portion of the logical address to create an offset address portion; generating a physical address that includes the address header and the offset address portion; accessing a physical resource using the physical address; and identifying, based on the address header, an offset module used to determine the offset value, wherein the offset module corresponds to the physical resource; and providing the address header to the identified offset module, wherein determining the address header, identifying the offset module, determining the offset value, and applying the offset value to the first portion of the logical address occurs within one clock cycle.
Claims 15, 20, and 27
16. The method of claim 15 further comprising, based on the first address, determining a security type.
3. The method of claim 1, wherein the logical address indicates a physical resource type, wherein determining the address header comprises determining the address header based on the physical resource type.
5. The method of claim 3, wherein the logical address further indicates a security type, wherein determining the address header comprises determining the address header based on the security type.
Allowable Subject Matter
Claims 1-20 are allowable if overcome the double patenting above.
Conclusion
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/KHOA D DOAN/Primary Examiner, Art Unit 2133
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