DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Foreign Priority
This application is a continuation of U.S. Patent Application No. 18/404,179 filed on 01/04/2024 that claims priority to Korean Patent Application No. 10-2023-0084176 filed in the Korean Intellectual Property Office on 06/29/2023. On 08/05/2025, an electronic copy of this document was received by the USPTO, and thus on the office action summary sheet examiner has checked off the box “all” certified copies have been received at this time.
Drawing Objection
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s), while no new matter should be entered:
Claims 1 and 18 each include first reference voltage generator including a first input terminal configured to receive the pixel drive voltage and a circuit drive voltage, however the figures do not depict a first of three input terminals that is configured to receive both the pixel drive voltage and a circuit drive voltage.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification Objection
The specification is objected to because the title is not descriptive. See MPEP 606.01 – “Where the title is not descriptive of the invention claimed, the examiner should require the substitution of a new title that is clearly indicative of the invention to which the claims are directed”. Correction is needed. Examiner suggests by way of example the following title: “DISPLAY DEVICE CONFIGURED TO GENERATE A DATA SIGNAL BASED ON A MAXIMUM GAMMA VOLTAGE AND A MINIMUM GAMMA VOLTAGE, DISPLAY SYSTEM, AND DRIVING METHOD OF DISPLAY DEVICE”.
Claim Rejections – 35 USC §112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 at line 16 includes “the ground voltage” that lacks antecedent basis. This grounds of rejection may be overcome, for example, by amending it to “a ground voltage”. Appropriate correction is required. This grounds of rejection applies to claims 2-10 that depend upon claim 1.
Claim 2 at line 16 includes “the light” that lacks antecedent basis. This grounds of rejection may be overcome, for example, by amending it to “light”. Appropriate correction is required.
Claim 5 at line 2 includes “the gate terminal of the second transistor” that lacks antecedent basis. This grounds of rejection may be overcome, for example, by amending it to “a gate terminal of the second transistor”. Appropriate correction is required.
Claim 16 at line 2 includes “the pixel” that lacks antecedent basis. This grounds of rejection may be overcome, for example, by amending it to “a pixel”. Appropriate correction is required.
Claim Rejections – 35 USC §102
7. The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102
that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public user, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11 and 13-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Pub. No. 2020/0211457 A1 to Kim et al. (“Kim”).
As to claim 11, Kim discloses a driving method of a display device (FIG. 1; ¶¶0035, 0041-0042), the method (FIG. 1; ¶¶0035, 0041-0042) comprising: applying an input voltage(INT_ELVDD)(FIG. 12; ¶0104) to a display driver IC(300)(FIG. 1; ¶¶0035, 0041); applying a pixel drive voltage(ELVDD)(FIGs. 1, 4A, 9 and 12; ¶0097) to the display driver IC(300)(FIG. 1; ¶¶0035, 0041) and a display panel(100)(FIG. 1: 221; ¶0097); generating, using the display driver IC(300)(FIG. 1; ¶¶0035, 0041), an initial voltage(Vo=ΔV*W)(FIG. 12; ¶¶0112-0113) based on the input voltage(INT_ELVDD)(FIG. 12; ¶¶0104, 0122) and the pixel drive voltage(ELVDD)(FIGs. 1, 4A, 9 and 12; ¶¶0097, 0112);
generating, using the display driver IC(300)(FIGs. 1, 12; ¶¶0035, 0041 includes a luminance compensator {FIGs. 1, 12: 114}), a maximum gamma voltage(VH)(FIGs. 5, 9, 12; ¶¶0043, 0108, 0112-0113, 0117) based on the initial voltage(Vo=ΔV*W)(FIG. 12; ¶¶0112-0113), the input voltage(INT_ELVDD)(FIG. 12; ¶¶0104, 0122), and the pixel drive voltage(ELVDD)(FIGs. 1, 4A, 9 and 12; ¶0097); generating, using the display driver IC(300)(FIGs. 1, 12; ¶¶0035, 0041 - display driver IC {FIG. 1: 300} includes a luminance compensator {FIGs. 1, 12: 114}), a minimum gamma voltage(VL)(FIGs. 5, 9, 12; ¶¶0043, 0108, 0112-0113, 0117) based on the initial voltage(Vo=ΔV*W)(FIG. 12; ¶¶0112-0113), the pixel drive voltage(ELVDD)(FIGs. 1, 4A, 9 and 12; ¶0097), and a ground voltage(GND symbol connected to amplifier providing VL)(FIG. 12; ¶0116); generating, using the display driver IC(300)(FIG. 1; ¶¶0035, 0041), a data signal(Vdata)(FIG. 4A; ¶¶0042, 0061, 0089, 0094) based on the maximum gamma voltage(VH)(FIGs. 4A, 5, 9, 12; ¶¶0042-0043, 0061, 0077-0078, 0080, 0083, 0108) and the minimum gamma voltage(VL)(FIGs. 4A, 5, 9; ¶¶0042-0043, 0061, 0077-0078, 0080, 0083, 0108); and displaying, using the display panel(100)(FIG. 1; ¶0097), an image based on the data signal(Vdata)(FIG. 4A; ¶¶0042, 0061, 0089, 0094), the maximum gamma voltage(VH)(FIGs. 4A, 5, 9, 12; ¶¶0042-0043, 0061, 0077-0078, 0080, 0083, 0108), and the minimum gamma voltage(VL)(FIGs. 4A, 5, 9; ¶¶0042-0043, 0061, 0077-0078, 0080, 0083, 0108).
As to claim 13, Kim discloses the driving method of the display device of claim 11, as applied above.
Kim further discloses wherein generating the data signal(Vdata)(FIG. 4A; ¶¶0042, 0061, 0089, 0094) includes: generating, using the display driver IC(300)(FIGs. 1, 12; ¶¶0035, 0041, 0043, 0075-0076, 0092, 0094 - display driver IC {FIG. 1: 300} includes a gamma compensated voltage generator {FIGs. 1, 5: 112} and a data driver {FIG. 6: 110} including a DAC {FIG. 6: 85} that uses gamma compensated voltages from the gamma compensated voltage generator {FIGs. 1, 5: 112} to create data signals), a plurality of gamma voltages(V191, V255)(FIG. 5; ¶0083) based on the maximum gamma voltage(VH)(FIGs. 4A, 5, 9; ¶¶0042-0043, 0061, 0077-0078, 0080, 0083, 0108) and the minimum gamma voltage(VL)(FIGs. 4A, 5, 9; ¶¶0042-0043, 0061, 0077-0078, 0080, 0083, 0108); and generating, using the display driver IC(300)(FIGs. 1, 12; ¶¶0035, 0041, 0043, 0075-0076, 0092, 0094 - display driver IC {FIG. 1: 300} includes a gamma compensated voltage generator {FIGs. 1, 5: 112} and a data driver {FIG. 6: 110} including a DAC {FIG. 6: 85} that uses gamma compensated voltages from the gamma compensated voltage generator {FIGs. 1, 5: 112} to create data signals), the data signal(Vdata)(FIG. 4A, 5: R51; ¶¶0042, 0061, 0089, 0094) based on the plurality of gamma voltages(V191, V255)(FIG. 5; ¶0083).
As to claim 14, Kim discloses the driving method of the display device of claim 13, as applied above.
Kim further discloses wherein the display driver IC(300)(FIGs. 1, 12; ¶¶0035, 0041, 0043, 0075-0076 - display driver IC {FIG. 1: 300} includes a gamma compensated voltage generator {FIGs. 1, 5: 112}) includes a gamma voltage generator(112)(FIGs. 1, 5; ¶¶0041, 0043) configured to generate a plurality of gamma voltages(V191, V255)(FIG. 5; ¶0083) based on the maximum gamma voltage(VH)(FIGs. 4A, 5, 9; ¶¶0042-0043, 0061, 0077-0078, 0080, 0083, 0108) and the minimum gamma voltage(VL)(FIGs. 4A, 5, 9; ¶¶0042-0043, 0061, 0077-0078, 0080, 0083, 0108),
wherein generating the plurality of gamma voltages(V191, V255)(FIG. 5; ¶0083) includes: generating, by the gamma voltage generator(112)(FIGs. 1, 5; ¶¶0041, 0043), the plurality of gamma voltages(V191, V255)(FIG. 5; ¶0083).
As to claim 15, Kim discloses the driving method of the display device of claim 13, as applied above.
Kim further discloses wherein the display driver IC includes(300)(FIGs. 1, 12; ¶¶0035, 0041, 0043, 0075-0076, 0092, 0094 - display driver IC {FIG. 1: 300} includes a gamma compensated voltage generator {FIGs. 1, 5: 112} and a data/source driver {FIG. 6: 110} including a DAC {FIG. 6: 85} that uses gamma compensated voltages from the gamma compensated voltage generator {FIGs. 1, 5: 112} to create data signals) a source driver(110)(FIG. 6; ¶¶0041-0042), wherein generating the data signal(Vdata)(FIG. 4A; ¶¶0042, 0061, 0089, 0094) includes: generating, by the source driver(110)(FIG. 6; ¶¶0041-0042), the data signal l(Vdata)(FIG. 4A; ¶¶0042, 0061, 0089, 0094) based on the plurality of gamma voltages(V191, V255)(FIG. 5; ¶0083 - R51 outputs gamma compensated voltages based on V191 and V255 one of which is used by the DAC {FIG. 6: 85} of the data/source driver {FIG. 6: 110} to create a data signal Vdata).
As to claim 16, Kim discloses the driving method of the display device of claim 11, as applied above.
Kim further discloses wherein the display panel(100)(FIG. 1: 221; ¶0097) includes the pixel(P)(FIGs. 1-2, 4A; ¶¶0013, 0036-0038) including a first transistor(DT)(FIG. 4A; ¶0057), the first transistor(DT)(FIG. 4A; ¶0057) including a source terminal(DT’s upper electrode)(FIG. 4A; ¶0057) to which the pixel drive voltage(DT’s upper electrode)(FIG. 4A; ¶0057) is configured to be applied (FIGs. 4A, 4B: ELVDD at DT’s upper electrode when EM(N) at VGL low; ¶¶0036, 0039, 0057), a gate terminal(DT’s gate electrode)(FIG. 4A; ¶0057) to which the data signal(Vdata)(FIG. 4A; ¶0061) is configured to be applied (FIG. 4A; Vdata applied to DT’s gate electrode; ¶¶0057, 0063, 0072), and a drain terminal(DT’s lower electrode)(FIG. 4A; ¶0057); and a light emitting diode(OLED)(FIG. 4A; ¶¶0013, 0057) configured to connect to the drain terminal(DT’s lower electrode)(FIG. 4A; ¶0057), wherein displaying the image based on the data signal(Vdata)(FIGs. 1, 4A: 100; ¶¶0042, 0061, 0089, 0094, 0097) includes: emitting, by the light emitting diode(OLED)(FIG. 4A; ¶¶0013, 0057-0058), light based on a drive current (¶0057) generated based on a voltage difference (¶¶0032, 0060) between the gate terminal(DT’s gate electrode)(FIG. 4A; ¶0057) and the source terminal(DT’s upper electrode)(FIG. 4A; ¶0057).
As to claim 17, Kim discloses the driving method of the display device of claim 11, as applied above.
Kim further discloses wherein generating the data signal(Vdata)(FIG. 4A; ¶¶0042, 0061, 0089, 0094) includes: generating the data signal(Vdata)(FIG. 4A; ¶¶0042, 0061, 0089, 0094) so as to have a variation corresponding to a variation in the pixel drive voltage(ELVDD)(FIGs. 1, 13; ¶¶0122-0128).
Allowable Subject Matter/Potentially Allowed Claims
9. Claims 12 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. As to claim 1-10, if the above grounds of rejection of these claims based on 35 U.S.C. 112(b) is overcome, then they would be allowed.
Reasons for Allowance
10. The following is examiner’s statement of reasons for allowance: the claimed invention is directed to:
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Independent claim 1 identifies the distinct features: “the first reference voltage generator(FIG. 1: 130) including a first input terminal(130’s terminal receiving PVDD) configured to receive the pixel drive voltage(FIG. 1: PVDD) and a circuit drive voltage1”, with all other limitations as claimed.
The closest prior art, U.S. Patent Pub. No. 2020/0211457 A1 to Kim et al. (“Kim”), either singularly or in combination, fails to anticipate or render obvious the above underlined features associated with other features of this claim.
As to claim 1, Kim discloses a display device (FIG. 1; ¶0035) comprising:
a pixel array(P)(FIGs. 1-2; ¶¶0036-0038) including a pixel(P)(FIGs. 1-2, 4A; ¶¶0013, 0036-0038), the pixel(P)(FIGs. 1-2, 4A; ¶¶0013, 0036-0038) including a light emitting diode(OLED)(FIG. 4A; ¶¶0013, 0057) and a first transistor(DT)(FIG. 4A; ¶0057), the first transistor(DT)(FIG. 4A; ¶0057) including:
a source terminal(DT’s upper electrode)(FIG. 4A; ¶0057) to which a pixel drive voltage(ELVDD)(FIGs. 4A, 4B: EM(N) at VGL low; ¶¶0036, 0039) is configured to be applied (FIGs. 4A, 4B: ELVDD at DT’s upper electrode when EM(N) at VGL low; ¶¶0036, 0039, 0057),
a gate terminal(DT’s gate electrode)(FIG. 4A; ¶0057) to which a data signal(Vdata)(FIG. 4A; ¶0061) is configured to be applied (FIG. 4A; Vdata applied to DT’s gate electrode; ¶¶0057, 0063, 0072), and a drain terminal(DT’s lower electrode)(FIG. 4A; ¶0057);
wherein the light emitting diode(OLED)(FIG. 4A; ¶¶0013, 0057) is configured to connect to the drain terminal(DT’s lower electrode)(FIG. 4A; ¶0057) and
a display driver integrated circuit (IC)(300)(FIG. 1; ¶¶0035, 0041) including a first reference voltage generator(20)(FIGs. 1, 9, 12; 114, 300; ¶¶0035, 0103, 0111) configured to generate a maximum gamma voltage(VH)(FIGs. 5, 9; ¶¶0043, 0108) and a second reference voltage generator(30)(FIGs. 1, 9; 114, 300; ¶¶0035, 0103, 0111) configured to generate a minimum gamma voltage(VL)(FIGs. 5, 9; ¶¶0043, 0109),
the first reference voltage generator(20)(FIGs. 1, 9, 12; 114, 300; ¶¶0035, 0103, 0111) including a first input terminal(20’s terminal receiving ΔV*W)(FIGs. 1, 9, 12; 114, 300; ¶¶0035, 0106, 0113) configured to receive ΔV*W(FIGs. 1, 9, 12; 114, 300; ¶¶0106, 0113), a second input terminal(20’s terminal receiving VCI*)(FIGs. 1, 9, 12; 114, 300; ¶¶0035, 0103, 0108, 0111) configured to receive the circuit drive voltage(VCI*)(FIGs. 9, 12; ¶¶0108, 0111), and a third input terminal(20’s terminal receiving ELVDD)(FIGs. 1, 9, 12; 114, 300; ¶¶0035, 0103, 0108, 0111) configured to receive the pixel drive voltage(ELVDD)(FIGs. 1, 9, 12: 20; 114, 300; ¶¶0035, 0103, 0108, 0111), and
the second reference voltage generator(30)(FIGs. 1, 9, 12; 114, 300; ¶¶0035, 0103, 0111) including a fourth input terminal(30’s terminal receiving VCI’)(FIGs. 1, 9, 12; 114, 300; ¶¶0035, 0103, 0108, 0111) configured to receive an initial voltage(VCI’)(FIGs. 9, 12; ¶¶0051, 0111), a fifth input terminal(30’s terminal receiving ELVDD)(FIGs. 1, 9, 12; 114, 300; ¶¶0035, 0103, 0108, 0111) configured to receive the pixel drive voltage(ELVDD)(FIGs. 1, 9, 12: 30; 114, 300; ¶¶0035, 0103, 0108, 0111), and a sixth input terminal(30’s terminal receiving grounding potential from ground symbol)(FIGs. 1, 9, 12; 114, 300; ¶¶0035, 0103, 0108, 0111) configured to receive the ground voltage(ground symbol)(FIG. 12; ¶0111),
wherein the display driver integrated circuit (IC)(300)(FIG. 1; ¶¶0035, 0041) is configured to generate the data signal(Vdata)(FIG. 4A; ¶¶0042, 0061) based on the maximum gamma voltage(VH)(FIGs. 4A, 5, 9; ¶¶0042-0043, 0061, 0077-0078, 0080, 0083, 0108) and the minimum gamma voltage(VL)(FIGs. 4A, 5, 9; ¶¶0042-0043, 0061, 0077-0078, 0080, 0083, 0109).
Kim does not disclose the above underlined limitations.
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Independent claim 12 identifies the distinct features: “the initial voltage(FIG. 2: VOGN) that is higher than the pixel drive voltage(FIG. 2: PVDD)”, with all other limitations as claimed.
The closest prior art, U.S. Patent Pub. No. 2020/0211457 A1 to Kim et al. (“Kim”), either singularly or in combination, fails to anticipate or render obvious the above underlined features associated with other features of this claim.
As to claim 12, Kim discloses the driving method of the display device of claim 11, as applied above.
Kim further discloses wherein generating the initial voltage(Vo=ΔV*W)(FIG. 12; ¶¶0112-0113) includes: generating, using the display driver IC(300)(FIGs. 1, 12; ¶¶0035, 0041 includes a luminance compensator {FIGs. 1, 12: 114}), the initial voltage(Vo=ΔV*W)(FIG. 12; ¶¶0054, 0112-0113) that is lower than the input voltage(INT_ELVDD)(FIG. 12; ¶¶0052, 0104, 0122) and higher than the pixel drive voltage(ELVDD)(FIGs. 1, 4A, 9 and 12; ¶0097).
Kim does not disclose the above underlined limitations.
Independent claim 18 identifies the distinct features: “a first reference voltage generator(FIG. 1: 130) including a first input terminal(130’s terminal receiving PVDD) configured to receive the pixel drive voltage(FIG. 1: PVDD) and the circuit drive voltage2”, with all other limitations as claimed.
The closest prior art, U.S. Patent Pub. No. 2020/0211457 A1 to Kim et al. (“Kim”), either singularly or in combination, fails to anticipate or render obvious the above underlined features associated with other features of this claim.
As to claim 18, Kim discloses the driving method of the display device of claim 11, as applied above.
Kim further discloses wherein the display driver IC(300)(FIGs. 1, 12; ¶¶0035, 0041 - display driver IC {FIG. 1: 300} includes a luminance compensator {FIGs. 1, 12: 114} including a first reference voltage generator {FIG. 12: 20}) includes a first reference voltage generator(20)(FIGs. 1, 9, 12; 114, 300; ¶¶0035, 0103, 0111) including a first input terminal(20’s terminal receiving ΔV*W)(FIGs. 1, 9, 12; 114, 300; ¶¶0035, 0106, 0113) configured to receive ΔV*W(FIGs. 1, 9, 12; 114, 300; ¶¶0106, 0113), a second input terminal(20’s terminal receiving VCI*)(FIGs. 1, 9, 12; 114, 300; ¶¶0035, 0103, 0108, 0111) configured to receive the circuit drive voltage(VCI*)(FIGs. 9, 12; ¶¶0108, 0111), and a third input terminal(VCI*)(FIGs. 9, 12; ¶¶0108, 0111) configured to receive the pixel drive voltage(ELVDD)(FIGs. 1, 9, 12: 20; 114, 300; ¶¶0035, 0103, 0108, 0111).
Kim does not disclose the above underlined limitations.
Other Relevant Prior Art
11. Other relevant prior art includes:
U.S. Patent Pub. No. 2010/0033514 A1 to Park et al.:
As to claim 11, Park discloses a driving method of a display device (FIG. 2: 100; ¶¶0027, 0029), the method (FIG. 2: 100; ¶¶0027, 0029) comprising: applying an input voltage(VCI)(FIGs. 2, 4; ¶0034) to a display driver IC (FIGs. 2, 4-5; ¶¶0018, 0034, 0048 - display driver IC includes a voltage generator {FIGs. 2, 4: 600} to which an input voltage VCI is applied); applying a pixel drive voltage(ELVDD)(FIGs. 1-2; ¶0034 - display driver IC includes a voltage generator {FIGs. 2, 4: 600} to which ELVDD is applied) to the display driver IC (FIGs. 2, 4, 5: 600, ELVDD; ¶¶0018, 0034, 0048, 0050) and a display panel(100)(FIG. 2: ELVDD; ¶0029); generating, using the display driver IC (FIGs. 2, 4, 5: 600; ¶¶0018, 0027, 0033-0034, 0048 - display driver IC includes a voltage generator {FIGs. 2, 4: 600} that generates an initial voltage {FIGs. 3-4: VHI} based on an input voltage {FIGs. 2, 4: VCI) and the pixel drive voltage {FIGs. 2, 4: ELVDD}), an initial voltage(VHI)(FIG. 4; ¶0036) based on the input voltage(VCI)(FIGs. 2, 4; ¶0034) and the pixel drive voltage(ELVDD)(FIGs. 1-2, 4; ¶0034); generating, using the display driver IC (FIGs. 2-5: 500, 600; ¶¶0018, 0033-0035, 0048, 0050 - display driver IC includes a gamma correction circuit {FIGs. 2-3: 500} and a voltage generator {FIGs. 2, 4: 600}), a maximum gamma voltage(V0)(FIG. 3; ¶0036) based on the initial voltage(VHI)(FIGs. 3-4; ¶0036), the input voltage(VCI)(FIGs. 2, 4; ¶0034), and the pixel drive voltage(ELVDD)(FIGs. 1-2, 4; ¶0034); generating, using the display driver IC (FIGs. 2-5: 500, 600; ¶¶0018, 0033-0035, 0048, 0050 - display driver IC includes a gamma correction circuit {FIGs. 2-3: 500} and a voltage generator {FIGs. 2, 4: 600}), a minimum gamma voltage(V63)(FIG. 3; ¶0036) based on the initial voltage(VHI)(FIGs. 3-4; ¶0036 - V63 is a minimum gamma voltage based on V0 being a maximum gamma voltage that is based on VHI), the pixel drive voltage(ELVDD)(FIGs. 1-2, 4: VHI is based on ELVDD; ¶0034), and a ground voltage(VLO or one of the ground terminals in FIG. 4)(FIG. 3; ¶¶0035, 0048); generating, using the display driver IC(200)(FIGs. 2, 5; ¶¶0030-0031, 0054-0056), a data signal (FIGs. 2, 5: 200; ¶¶0018, 0030-0031, 0054-0056) based on the maximum gamma voltage(V0)(FIG. 3; ¶0036) or the minimum gamma voltage(V63)(FIG. 3; ¶0036); and displaying, using the display panel(100)(FIG. 2: ELVDD; ¶0029), an image based on the data signal (¶¶0029-0030), the maximum gamma voltage(V0)(FIG. 3; ¶0036) or the minimum gamma voltage(V63)(FIG. 3; ¶0036).
Conclusion
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIRK W HERMANN whose telephone number is (571) 270-3891. The examiner can normally be reached on Monday-Friday, 9am-5pm, EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on (571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIRK W HERMANN/Primary Examiner, Art Unit 2623
1 As explained in the above section entitled “Drawing Objection”, this limitation is not shown in the figures.
2 As explained in the above section entitled “Drawing Objection”, this limitation is not shown in the figures.
Prosecution Insights