DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/14/2025 was filed on or after the effective filing date of the instant application on 07/14/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 12,363,252. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Regarding claim 1, the instant application claim 1 and the US patent claim 1 are both drawn to the same invention.
The claims differ in scope since the instant application claim 1 is broader in every aspect than the patent claim 1 and is therefore an obvious variant thereof.
Claim 1 of the instant application is anticipated by the patent claim 1 in that claim 1 of the patent contains all the limitations of claim 1 of the instant application. Claim 1 of the instant application therefore is not patently distinct from the earlier patent claim and as such is unpatentable for obvious-type double patenting.
Claim 2 corresponds to the patent claim 1.
Claims 3-4 correspond to the patent claim 2.
Claims 5-9 correspond to the patent claims 3-7 respectively.
Claims 10-11 correspond to the patent claim 8.
Claims 12-18 correspond to the patent claims 9-15 respectively.
Claim 19 corresponds to the patent claim 8.
Claims 20-21 correspond to the patent claim 16.
Claim 22 corresponds to the patent claim 17.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 7 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation "the transfer circuit" in line 7. There is insufficient antecedent basis for this limitation in the claim.
Claim 7 recites the limitation "the transfer circuit" in line 1 and line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 9 recites the limitation "the transfer circuit" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2010/0302214) in view of Chandra et al (US 2020/0364174).
Regarding claim 1, Kim discloses an electronic circuit (Figure 1) comprising:
a first communication interface;
a second communication interface;
a digital timing generator having an input coupled to the first communication interface, and a timing signal interface coupled to the second communication interface (Figure 2) and configurable to:
provide a first timing signal to the second communication interface responsive to a first mode selection; and receive a second timing signal from the second communication interface responsive to a second mode selection (¶ [0047]-[0058] and ¶ [0066] for providing and receiving data enable sync signals responsive to selections of a master mode and slaves mode).
Kim is silent about a reset synchronizer configurable to: receive a first reset signal responsive to the first mode selection; receive a second reset signal responsive to the second mode selection; and provide a synchronized reset signal responsive to the first reset signal or the second reset signal.
Chandra discloses a reset synchronizer (reset synchronizer 204 in Figure 2) configurable to: receive a first reset signal responsive to the first mode selection; receive a second reset signal responsive to the second mode selection; and provide a synchronized reset signal responsive to the first reset signal or the second reset signal (¶ [0027]-[0032]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim system to include a reset synchronizer as taught by Chandra, so to enhance a signal synchronizing process with a capability of resetting clock circuitry with the reset signal from the reset synchronizer.
Regarding claim 2, Kim in view of Chandra discloses the electronic circuit as discussed in the rejection of claim 1. The combined system further discloses a divider coupled to an output of the reset synchronizer (taught by Chandra; clock detection circuit 206 as a divider).
Regarding claim 9, Kim in view of Chandra discloses the electronic circuit as discussed in the rejection of claim 1. The combined system further discloses wherein the second communication interface includes a set of general programmable input/outputs (GPIOs), and the transfer circuit includes multi-chip synchronization circuitry (Kim’s Figures 1 and 13; and Chandra’s Figure 1) configured to: output a first reset signal and a first set of timing signals including the first timing signal via the set of GPIOs to another transfer circuit responsive to the first mode selection; and receive a second reset signal and a second set of timing signals from the other transfer circuit responsive to the second mode (taught by Chandra; Figure 2 and ¶ [0027]-[0032]).
Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2010/0302214) in view of Chandra et al (US 2020/0364174) as applied to claim 1 above, and further in view of Kuroki et al (US 2013/0155321).
Regarding claim 3, Kim in view of Chandra discloses the electronic circuit as discussed in the rejection of claim 1. The combined system further discloses a multiplexer having a first input, a second input, a control input, and an output (taught by Chandra; a multiplexer 408 in Figure 4), the first input of the multiplexer coupled to the timing signal interface of the digital timing generator, the second input of the multiplexer coupled to the second communication interface, the first input of the multiplexer configured to receive the first timing signal, and the second input of the multiplexer configured to receive the second timing signal (taught by Chandra; ¶ [0043]-[0048]).
The combined system is silent about a programmable delay line having a first input, a second input, and an output.
Kuroki discloses a video processing apparatus (Figures 1 and 5) comprising a programmable delay line (delay addition unit 115) having a first input, a second input, and an output; a multiplexer (selector unit 119) having a first input, a second input, a control input, and an output, the first input of the multiplexer coupled to the video timing signal interface of the digital timing generator (reference timing generation unit 108), the second input of the multiplexer coupled to the second communication interface, and the multiplexer configured to receive the first video timing signal at its first input and the second video timing signal at its second input (¶ [0023]-[0025]).
Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Kim in view of Chandra system with the teaching of Kuroki, so to enhance synchronization of image signals from multiple chip processing by taking into consideration a delay time of input signals to exactly match the output timings of the image signals.
Regarding claim 4, Kim in view of Chandra and further in view of Kuroki discloses the electronic circuit as discussed in the rejection of claim 3. The combined system further discloses a controller having a control output coupled to the control input of the multiplexer (taught by Kuroki; ¶ [0023]-[0025]), the controller configured to vary a mode signal at the control output responsive to the transfer circuit being used as a primary transfer circuit or a secondary transfer circuit (taught by Kuroki; Figures 3A-3B; ¶ [0036]-[0039]).
Regarding claim 5, Kim in view of Chandra discloses the electronic circuit as discussed in the rejection of claim 1. The combined system further discloses the digital timing generator is configurable to: provide a first set of timing signals to the second communication interface via the timing signal interface responsive to a first mode selection; and receive a second set of timing signals from the second communication interface via the timing signal interface responsive to a second mode selection (taught by Kim; Figures 1 and 13); wherein the transfer circuit further comprises: a multiplexers configured to select the first timing signal or the second timing signals responsive to a mode signal (taught by Chandra; ¶ [0043]-[0048]).
The combined system is silent about a set of multiplexers, the set of multiplexers configured to select the first set of timing signals or the second set of timing signals responsive to a mode signal; and a set of programmable delay lines configured to apply a delay to the first set of timing signals or the second set of timing signals selected by the set of multiplexers.
Kuroki discloses a set of multiplexers, the set of multiplexers configured to select the first set of video timing signals or the second set of video timing signals responsive to a mode signal; and a set of programmable delay lines configured to apply a delay to the first set of video timing signals or the second set of video timing signals selected by the set of multiplexers (Figures 1, 3A-3B and 4-5).
Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Kim in view of Chandra system with the teaching of Kuroki, so to enhance synchronization of image signals from multiple chip processing by taking into consideration a delay time of input signals to exactly match the output timings of the image signals.
Regarding claim 6, Kim in view of Chandra discloses the electronic circuit as discussed in the rejection of claim 1. The combined system further discloses to delay the first reset signal or the second reset signal received by the reset synchronizer (taught by Chandra; ¶ [0027]-[0041]), but is silent about a programmable delay line configured to delay the first reset signal or the second reset signal.
Kuroki discloses a programmable delay line configured to delay the received first reset signal or the second reset signal (Figures 1 and 5; and ¶ [0023]-[0025]).
Therefore, it would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Kim in view of Chandra system with the teaching of Kuroki, so to enhance synchronization of image signals from multiple chip processing by taking into consideration a delay time of input signals to exactly match the output timings of the image signals.
Allowable Subject Matter
Claims 7-8 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 10-22 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The arts of record either alone or in combination fails to particularly disclose or suggest the unique combination and arrangement of claimed elements recited in the claim 7, claim 10 and claim 20, when considering the claims as a whole.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GIGI L DUBASKY whose telephone number is (571)270-5686. The examiner can normally be reached M-F 9:00-5:00.
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/GIGI L DUBASKY/Primary Examiner, Art Unit 2421
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