DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication US2024/0007342A1 to Gupta et al.
As per claim 8, Gupta teaches a computing device comprising: one or more processors; and memory storing instructions that, when executed by the one or more processors, cause the computing device to perform: receive, based on a mapping of one or more components in a computer architecture, an ordered graph indicating one or more relationships between the one or more components (¶ 0068, wherein the knowledge graph comprises corresponding infrastructure components and relationships); determine, by a machine learning model trained to perform structural analysis on the ordered graph, one or more failure points associated with the one or more components (¶ 0232, wherein the model receives the knowledge graph and generates a causality graph); iteratively inject one or more error conditions into the one or more components, wherein the one or more error conditions comprise increased latency in communications between the one or more components; detect, based on the iteratively injecting the one or more error conditions, one or more downstream effects of the one or more error conditions, wherein the one or more downstream effects comprise increased latency in communications between a second set of one or more other components different from the first set of one or more components (¶ 0164-0166); revise, by the machine learning model and based on the one or more downstream effects, the one or more failure points (¶ 0235, wherein the model is revised with received prior data);
As per claim 9, Gupta teaches the computing device of claim 8, wherein the first set of one or more components comprise one or more of: hardware components, or software components (¶ 0056).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gupta in view of U.S. Patent Application Publication US2026/0142885A1 to Viccari et al.
As per claim 12, Gupta teaches the computing device of claim 8. Viccari teaches wherein the one or more error conditions comprise one or more of: downtime, bandwidth restrictions, error codes, judder, or excess traffic (¶ 0039). It would have been obvious to one of ordinary skill in the art to use the process of Viccari in the process of Gupta. One of ordinary skill in the art would have been motivated to use the process of Viccari in the process of Gupta because using the process of Viccari would have yielded the predictable result of collecting and analyzing software/network metrics from fault injection to predict an anomaly.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gupta in view of U.S. Patent Application Publication US2023/0087837A1 to Hwang et al.
As per claim 13, Gupta teaches the computing device of claim 8. Hwang teaches wherein the machine learning model comprises a Bayesian network model (¶ 0130, 0030). It would have been obvious to one of ordinary skill in the art to use the process of Hwang in the process of Gupta. One of ordinary skill in the art would have been motivated to use the process of Hwang in the process of Gupta because using the process of Hwang would have yielded the predictable result of analyzing software/network metrics in a learning model from fault injection to predict an anomaly.
Claim(s) 1-4, 7, 10-11, 14-17, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al. in view of U.S. Patent 11,507,447 to Ezrielev et al.
As per claim 1, Gupta teaches a method comprising: receiving, based on a mapping of one or more components in a computer architecture, an ordered graph indicating one or more relationships between the one or more components (¶ 0068, wherein the knowledge graph comprises corresponding infrastructure components and relationships); determining, by a machine learning model trained to perform structural analysis on the ordered graph, one or more failure points associated with the one or more components (¶ 0232, wherein the model receives the knowledge graph and generates a causality graph); iteratively injecting one or more error conditions into the one or more components, wherein the one or more error conditions comprise increased latency in communications between the one or more components; detecting, based on the iteratively injecting the one or more error conditions, one or more downstream effects of the one or more error conditions, wherein the one or more downstream effects comprise increased latency in communications between one or more other components (¶ 0164-0166); revising, by the machine learning model and based on the one or more downstream effects, the one or more failure points (¶ 0235, wherein the model is revised with received prior data); and presenting, using a display, a visual representation of the one or more failure points (¶ 0175). Gupta does not explicitly teach wherein the ordered graph comprises mapped metadata. Ezrielev teaches wherein the ordered graph comprises mapped metadata (column 5, lines 20-32). It would have been obvious to one of ordinary skill in the art to use the process of Ezrielev in the process of Gupta. One of ordinary skill in the art would have been motivated to use the process of Ezrielev in the process of Gupta because using the process of Ezrielev would have yielded the predictable result of collecting and analyzing software metrics to predict an anomaly.
As per claim 2, Gupta teaches the method of claim 1, wherein the one or more components comprise one or more of: hardware components, or software components (¶ 0056).
As per claim 3, Ezrielev teaches the method of claim 1, further comprising training the machine learning model based on historical component descriptions, wherein the historical component descriptions comprise: domain-specific language associated with the computer architecture; and labeled images of diagram components (column 4, lines 23-29).
As per claim 4, Ezrielev teaches the method of claim 1, further comprising training the machine learning model based on historical data associated with real-world failures (column 5, lines 3-15).
As per claim 7, Ezrielev teaches the method of claim 1, further comprising: determining, based on the one or more failure points, one or more remedial actions for the computer architecture; and performing, based on detecting a failure of a subset of the one or more components, the one or more remedial actions (column 5, lines 55-64).
As per claim 10, Ezrielev teaches the computing device of claim 8, wherein the machine learning model is trained based on: domain-specific language associated with the computer architecture; and labeled images of diagram components (column 4, lines 23-29).
As per claim 11, Ezrielev teaches the computing device of claim 8, wherein the machine learning model is trained based on historical data associated with real-world failures (column 5, lines 3-15).
As per claim 14, Ezrielev teaches the computing device of claim 8, instructions, when executed by the one or more processors, further cause the computing device to: determine, based on the one or more failure points, one or more remedial actions for the computer architecture; and perform, based on detecting a failure of a subset of the first set of one or more components, the one or more remedial actions (column 5, lines 55-64).
As per claim 15, Gupta teaches a non-transitory computer-readable medium storing computer instructions that, when executed by one or more processors, cause performance of actions comprising: receiving, based on a mapping of one or more components in a computer architecture, an ordered graph indicating one or more relationships between the one or more components; determining, by a machine learning model trained to perform structural analysis on the ordered graph, one or more failure points associated with the one or more components; iteratively injecting one or more error conditions into the one or more components; detecting, based on the iteratively injecting the one or more error conditions, one or more downstream effects of the one or more error conditions; revising, by the machine learning model and based on the one or more downstream effects, the one or more failure points (¶ 0068, 01640-166, 0232, 0235, see claim for mapping). Gupta does not explicitly teach wherein the ordered graph comprises mapped metadata and determining, based on the one or more failure points, one or more remedial actions for the computer architecture; and performing, based on detecting a failure of a subset of the one or more components, the one or more remedial actions. Ezrielev teaches wherein the ordered graph comprises mapped metadata (column 5, lines 20-32), and determining, based on the one or more failure points, one or more remedial actions for the computer architecture; and performing, based on detecting a failure of a subset of the one or more components, the one or more remedial actions (column 5, lines 55-64). It would have been obvious to one of ordinary skill in the art to use the process of Ezrielev in the process of Gupta. One of ordinary skill in the art would have been motivated to use the process of Ezrielev in the process of Gupta because using the process of Ezrielev would have yielded the predictable result of collecting and analyzing software metrics to predict an anomaly.
As per claim 16, Gupta teaches the non-transitory computer-readable medium storing computer instructions of claim 15, wherein the one or more components comprise one or more of: hardware components, or software components (¶ 0056).
As per claim 17, Ezrielev teaches the non-transitory computer-readable medium storing computer instructions of claim 15, when executed by the one or more processors, further cause performance of actions comprising: training the machine learning model based on one or more of: domain-specific language associated with the computer architecture, labeled images of diagram components, or historical data associated with real-world failures (column 4, lines 23-29; column 5, lines 3-15).
As per claim 20, Gupta teaches the non-transitory computer-readable medium storing computer instructions of claim 15, when executed by the one or more processors, further cause performance of actions comprising: presenting, using a display, a user interface indicating the one or more failure points (¶ 0175).
Claim(s) 5, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gupta in view of Ezrielev in view of Viccari.
As per claim 5, Gupta teaches the method of claim 1. Viccari teaches wherein the one or more error conditions comprise one or more of: downtime, bandwidth restrictions, error codes, judder, or excess traffic (¶ 0039). It would have been obvious to one of ordinary skill in the art to use the process of Viccari in the process of Gupta. One of ordinary skill in the art would have been motivated to use the process of Viccari in the process of Gupta because using the process of Viccari would have yielded the predictable result of collecting and analyzing software/network metrics from fault injection to predict an anomaly.
As per claim 18, Gupta teaches the non-transitory computer-readable medium storing computer instructions of claim 15. Viccari teaches wherein the one or more error conditions comprise one or more of: downtime, bandwidth restrictions, error codes, judder, or excess traffic (¶ 0039). It would have been obvious to one of ordinary skill in the art to use the process of Viccari in the process of Gupta. One of ordinary skill in the art would have been motivated to use the process of Viccari in the process of Gupta because using the process of Viccari would have yielded the predictable result of collecting and analyzing software/network metrics from fault injection to predict an anomaly.
Claim(s) 6, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gupta in view of Ezrielev in view of Hwang.
As per claim 6, Gupta teaches the method of claim 1. Hwang teaches wherein the machine learning model comprises a Bayesian network model (¶ 0130, 0030). It would have been obvious to one of ordinary skill in the art to use the process of Hwang in the process of Gupta. One of ordinary skill in the art would have been motivated to use the process of Hwang in the process of Gupta because using the process of Hwang would have yielded the predictable result of analyzing software/network metrics in a learning model from fault injection to predict an anomaly.
As per claim 19, Gupta teaches the non-transitory computer-readable medium storing computer instructions of claim 15. Hwang teaches wherein the machine learning model comprises a Bayesian network model (¶ 0130, 0030). It would have been obvious to one of ordinary skill in the art to use the process of Hwang in the process of Gupta. One of ordinary skill in the art would have been motivated to use the process of Hwang in the process of Gupta because using the process of Hwang would have yielded the predictable result of analyzing software/network metrics in a learning model from fault injection to predict an anomaly.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2022/0214935A1 to Choudhury et al.: Machine learning for incident prediction of a software application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER S MCCARTHY whose telephone number is (571)272-3651. The examiner can normally be reached Monday-Friday 8:30-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at (571)272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER S MCCARTHY/Primary Examiner, Art Unit 2113
Prosecution Insights