DETAILED ACTION
This Office Action, based on application 19/270,081 filed 15 July 2025, is filed responsive to the initial filing of the application. Claims 1-25, as originally filed, are currently pending and have been fully considered below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 25 November 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
The following claim(s) is/are objected to due to informalities:
Claim 8: “in received in” appears to have a typographical error.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-10 and 12-25 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception without significantly more. Patent Eligibility is determined as set forth under the 2019 Patent Eligibility Guidelines (see MPEP § 2106). The analysis of the claims in view of the guidelines are presented below.
Claim 1: Regarding Step 1, the claim is directed to a system (or machine/manufacture). Thus, the claim is directed to one of the four categories of invention.
Regarding Step 2A Prong 1, this part of the eligibility analysis evaluates whether the claim recites a judicial exception. The claim includes the following limitations:
A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
write, to a buffer of the memory system in response to performing a read operation for a logical address, an indication of the logical address and a read temperature, for the logical address, of the memory system during the read operation;
determine, in response to detecting an empty command queue for a host system and using the read temperature from the buffer, a cross temperature for the logical address, the cross temperature representative of a difference between the read temperature and a write temperature of the memory system during a write operation for the logical address; and
transmit an indication of the cross temperature for the logical address after determining the cross temperature using the read temperature from the buffer.
The underlined portions of Limitation (5) above broadly recite a process for calculating or determining a ‘cross temperature’ associated with a storage location in memory. The limitation includes detecting an empty command queue to which the Office asserts constitute making an observation of the contents of the command queue. The limitation further includes how the ‘cross temperature’ is determined which includes performing a simple subtraction calculation. While the claim as a whole does not recite how either the read temperature (before writing the read temperature to the buffer) or the write temperature is obtained, the Office asserts a person of ordinary skill in the art may do so by observing a reading from a thermometer or other temperature sensor. Enumerated groupings of abstract ideas include “Mental Processes (MPEP 2106.04(a)). The Office has determined that the actions of the underlined portions of Limitation (5) fall within the “Mental Processes” grouping of abstract ideas as the limitations can practically be performed in the human mind, including for example, observations, evaluations, judgements, and opinions (see MPEP 2106.04(a)(2)(III)). The Office has determined the claim recites a judicial exception requiring further analysis under Step 2A Prong 2.
Regarding Step 2A Prong 2, this part of the eligibility analysis evaluates whether the claim as a whole integrates the recited judicial exception into a practical application of the exception. This evaluation is performed by (a) identifying whether there are any additional elements recited in the claim beyond the judicial exception, and (b) evaluating those additional elements individually and in combination to determine whether the claim as a whole integrates the exception into a practical application. Besides the abstract idea of the claim, the claim further recites:
A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
write, to a buffer of the memory system in response to performing a read operation for a logical address, an indication of the logical address and a read temperature, for the logical address, of the memory system during the read operation;
determine, in response to detecting an empty command queue for a host system and using the read temperature from the buffer, a cross temperature for the logical address, the cross temperature representative of a difference between the read temperature and a write temperature of the memory system during a write operation for the logical address; and
transmit an indication of the cross temperature for the logical address after determining the cross temperature using the read temperature from the buffer.
The underlined portions of Limitations (2)-(4) and (6) above have been identified to recite additional elements beyond the judicial exception.
Limitations (2) and (3) further limit the claimed memory system to comprise structural elements including one or more memory devices and processing circuitry. The processing circuitry is limited to being configured to perform the functions of the identified abstract idea. The Office asserts the claimed system comprising structural elements are recited at a high-level of generality such that they merely comprise generic computing elements used to apply the identified abstract idea. Accordingly, the additional elements of one or more memory devices and processing circuitry do not integrate the abstract idea into a practical application because the structural components do not impose any meaningful limits on practicing the abstract idea (MPEP 2106.05(f)).
Limitation (4) further limit the claimed system to writing an association between a logical address and a read temperature in a buffer. The Office notes the claim as a whole is not further limited as to how the values of the logical address or read temperature are obtained. The Office asserts the limitation constitutes a pre-solution activity of gathering data for use in the claimed abstract idea as the limitation is merely directed to writing known information into memory which information is later recalled and used in the identified abstract idea of calculating the cross temperature. As such, Limitation (4) amounts to insignificant extra-solution activity as the limitation amounts to mere data gathering or data output to which the courts have determined to be insignificant extra-solution activity (MPEP 2106.05(g)).
Limitation (6) further limits the claimed system to sending the calculated cross temperature. The Office asserts the limitation constitutes a post-solution activity of gathering data for use in the claimed abstract idea as the limitation is merely directed to sending information determined when implementing the abstract idea to some other entity. As such, Limitation (6) amounts to insignificant extra-solution activity as the limitation amounts to mere data gathering or data output to which the courts have determined to be insignificant extra-solution activity (MPEP 2106.05(g)).
The Office notes the claim as a whole is merely directed to determining a cross temperature without further limiting the claims to using the determined value for any particular purpose. As such, the Office asserts the claim fails to recite any sort of improvement in the functioning of a computer because the determined value is not further used or relied upon for any particular purpose other than to be generated and reported.
As such, the claim does not include additional elements that integrate the judicial exception into a practical application requiring further analysis under Step 2B.
Regarding Step 2B, this part of the eligibility analysis evaluates the additional elements of the claim to determine whether they amount to an inventive concept. As noted above in conjunction with the analysis of Step 2A Prong 2, those additional elements have been identified.
Limitations (2) and (3) further limit the claimed system to comprise structural elements including one or more memory devices and processing circuitry. As noted in the analysis of the elements in conjunction with Step 2A Prong 2, the claimed system comprising structural elements are recited at a high-level of generality such that they merely comprise generic computing elements used to apply the identified abstract idea. Accordingly, the additional elements of one or more memory devices and processing circuitry do not add significantly more than the judicial exception because the structural components do not impose any meaningful limits on practicing the abstract idea (MPEP 2106.05(f)).
Limitation (4) further limit the claimed apparatus to writing data to a buffer. The courts have recognized, similar to the elements of the limitation, that computer functions including “storing and retrieving information in memory” are well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (MPEP 2106.05(d)(II)).
Limitation (6) further limits the claimed apparatus to transmitting the determined cross temperature. The courts have recognized, similar to the elements of the limitation, that computer functions including “receiving or transmitting data over a network” are well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (MPEP 2106.05(d)(II)).
As such, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception and thus are not patent eligible.
Claim 12:The claim recites the following limitations:
A host system, comprising:
one or more interfaces comprising one or more signal paths operable for communication with one or more memory systems; and
processing circuitry coupled with the one or more interfaces and configured to cause the host system to:
select a metric for a memory system of the one or more memory systems to use in collecting cross temperature information for logical addresses, wherein the cross temperature information for a logical address represents a difference between a read temperature of the memory system during a read operation for the logical address and a write temperature of the memory system during a write operation for the logical address;
transmit a command for the memory system to collect the cross temperature information for logical addresses in accordance with the metric, wherein the command indicates the metric;
transmit, in response to transmitting the command, a message requesting the cross temperature information collected by the memory system in accordance with the metric; and
receive, in response to transmitting the message, the cross temperature information collected by the memory system in accordance with the metric.
Similar to the analysis of Claim 1 above:
The claim is directed to a system (or machine/manufacture); thus, the claim is directed to one of the four categories of invention.
Limitation (4) recites a judicial exception.
The Office asserts the act of ‘select{ing}’ a metric constitutes making a choice or making a judgement; thus the limitation is directed to a “Mental Process” as reasoned in the analysis of Claim 1’s Limitation (5).
Limitations (2), (3), and (5) through (7) recite additional elements that fail to integrate the recited judicial exception into a practical application.
The Office asserts the claimed ‘one or more interfaces’ of Limitation (2) and processing circuitry of Limitation (3) are analyzed similar to Limitations (2) and (3) of Claim 1.
The Office asserts the claimed ‘transmit’ a command and message of Limitations (5) and (6) are analyzed similar to Limitation (6) of Claim 1.
The Office asserts the claimed “receive … the cross temperature information” is analyzed similar to Limitation (4) of Claim 1.
Limitations (2), (3), and (5) through (7) do not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Claim 20:The claim recites the following limitations:
A method, comprising:
writing, to a buffer of a memory system in response to performing a read operation for a logical address, an indication of the logical address and a read temperature, for the logical address, of the memory system during the read operation;
determining, in response to detecting an empty command queue for a host system and using the read temperature from the buffer, a cross temperature for the logical address, the cross temperature representative of a difference between the read temperature and a write temperature of the memory system during a write operation for the logical address; and
transmitting an indication of the cross temperature for the logical address after determining the cross temperature using the read temperature from the buffer
Similar to the analysis of Claim 1 above:
The claim is directed to a method (or process); thus, the claim is directed to one of the four categories of invention.
Limitation (3) recites a judicial exception.
Limitations (2) and (4) recite additional elements that fail to integrate the recited judicial exception into a practical application.
Limitations (2) and (4) do not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Claims 2 and 19
Claim 2 (and similarly Claim 19) recites a limitation beyond that recited in parent Claim 1; the limitation is not found to further the identified “Mental Process” in the parent claim. However, Claim 2 is further directed to a judicial exception due to the identified “Mental Process” of Claim 1. Claim 2 comprises additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
While Claim 2 further recite an additional element of receiving a command with the intended use of the command to collect temperature information and writing data to a buffer in response to receiving the command, the Office asserts the additional element fails to integrate the recited judicial exception into a practical application and the additional element is not sufficient to amount to significantly more than the judicial exception. The Office asserts the limitation amounts to insignificant extra-solution activity as the limitation amounts to mere data gathering or data output to which the courts have determined to be insignificant extra-solution activity (MPEP 2106.05(g)). Furthermore, the courts have recognized, similar to the elements of the limitation, that computer functions including “storing and retrieving information in memory” or “receiving or transmitting data over a network” are well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (MPEP 2106.05(d)(II)).
Claims 3 and 20
Beyond the analysis of Claim 1, the additional limitations incorporated into Claim 3 (and similarly Claim 20) have been found to further limit the identified abstract idea of the parent claim. Claim 3 is directed to first determining the read temperature that is limited to being written to a buffer in the parent claim including defining when the read temperature is determined. For similar reasons provided in the analysis of the limitations in conjunction with determining a cross temperature of Claim 1’s Limitation (5) above, the Office has determined that the additional limitations of the dependent claims fall within the “Mental Processes” grouping of abstract ideas as the limitations may practically be performed in the human mind, including for example, observations, evaluations, judgements, and opinions (MPEP 2106.04(a)(2)(III)). Claim 3 comprises additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
While Claim 3 further recite an additional element of writing data to a buffer in response to writing other data to the buffer, the Office asserts the additional element fails to integrate the recited judicial exception into a practical application and the additional element is not sufficient to amount to significantly more than the judicial exception. The Office asserts the limitation amounts to insignificant extra-solution activity as the limitation amounts to mere data gathering or data output to which the courts have determined to be insignificant extra-solution activity (MPEP 2106.05(g)). Furthermore, the courts have recognized, similar to the elements of the limitation, that computer functions including “storing and retrieving information in memory” are well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (MPEP 2106.05(d)(II)).
Claims 4 and 21
Claim 4 (and similarly Claim 21) recites a limitation beyond that recited in parent Claim 3; the limitation is not found to further the identified “Mental Process” in the parent claim. However, Claim 4 is further directed to a judicial exception due to the identified “Mental Process” of Claim 3. Claim 4 comprises additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
While Claim 4 further recite an additional element of sending and receiving the indication of the size of the buffer, the Office asserts the additional element fails to integrate the recited judicial exception into a practical application and the additional element is not sufficient to amount to significantly more than the judicial exception. The Office asserts the limitation amounts to insignificant extra-solution activity as the limitation amounts to mere data gathering or data output to which the courts have determined to be insignificant extra-solution activity (MPEP 2106.05(g)). Furthermore, the courts have recognized, similar to the elements of the limitation, that computer functions including “receiving or transmitting data over a network” are well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (MPEP 2106.05(d)(II)).
Claim 5
Beyond the analysis of Claim 3, the additional limitations incorporated into Claim 5 has been found to further limit the identified abstract idea of the parent claim. Claim 5 is directed to further defining Claim 3’s ‘determining a threshold quantity of logical addresses’ to include random generation of the threshold quantity (similar to making an opinion or judgement of the value). For similar reasons provided in the analysis of the limitations in conjunction with Claim 3 above, the Office has determined that the additional limitation of the dependent claim falls within the “Mental Processes” grouping of abstract ideas as the limitations may practically be performed in the human mind, including for example, observations, evaluations, judgements, and opinions (MPEP 2106.04(a)(2)(III)). The claims do not comprise any additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
Claims 6 and 22
Beyond the analysis of Claim 1, the additional limitations incorporated into Claim 6 (and similarly Claim 22) have been found to further limit the identified abstract idea of the parent claim. Claim 6 is directed to choosing which logical address is to be written to a buffer. Since the act of ‘selecting’ is equivalent to making a judgement or opinion, the Office has determined that the additional limitations of the dependent claims fall within the “Mental Processes” grouping of abstract ideas as the limitations may practically be performed in the human mind, including for example, observations, evaluations, judgements, and opinions (MPEP 2106.04(a)(2)(III)). Claim 6 comprises additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
While Claim 6 further recite an additional element of writing data to the buffer, the Office asserts the additional element fails to integrate the recited judicial exception into a practical application and the additional element is not sufficient to amount to significantly more than the judicial exception. The Office asserts the limitation amounts to insignificant extra-solution activity as the limitation amounts to mere data gathering or data output to which the courts have determined to be insignificant extra-solution activity (MPEP 2106.05(g)). Furthermore, the courts have recognized, similar to the elements of the limitation, that computer functions including “storing and retrieving information in memory” are well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (MPEP 2106.05(d)(II)).
Claim 7
Beyond the analysis of Claim 6, the additional limitations incorporated into Claim 7 have been found to further limit the identified abstract idea of the parent claim. Claim 7 is directed to choosing which logical addresses are to be written to a buffer. Since the act of ‘selecting’ is equivalent to making a judgement or opinion, the Office has determined that the additional limitations of the dependent claims fall within the “Mental Processes” grouping of abstract ideas as the limitations may practically be performed in the human mind, including for example, observations, evaluations, judgements, and opinions (MPEP 2106.04(a)(2)(III)). Claim 7 comprises additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
While Claim 7 further recite an additional element of receiving the indication of the quantity of logical addresses, the Office asserts the additional element fails to integrate the recited judicial exception into a practical application and the additional element is not sufficient to amount to significantly more than the judicial exception. The Office asserts the limitation amounts to insignificant extra-solution activity as the limitation amounts to mere data gathering or data output to which the courts have determined to be insignificant extra-solution activity (MPEP 2106.05(g)). Furthermore, the courts have recognized, similar to the elements of the limitation, that computer functions including “receiving or transmitting data over a network” are well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (MPEP 2106.05(d)(II)).
Claim 8
Claim 8 recites a limitation beyond that recited in parent Claim 7; the limitation is not found to further the identified “Mental Process” in the parent claim. However, Claim 8 is further directed to a judicial exception due to the identified “Mental Process” of Claim 7. Claim 8 comprises additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
While Claim 8 further recite an additional element of sending and receiving the indication of the size of the buffer, the Office asserts the additional element fails to integrate the recited judicial exception into a practical application and the additional element is not sufficient to amount to significantly more than the judicial exception. The Office asserts the limitation amounts to insignificant extra-solution activity as the limitation amounts to mere data gathering or data output to which the courts have determined to be insignificant extra-solution activity (MPEP 2106.05(g)). Furthermore, the courts have recognized, similar to the elements of the limitation, that computer functions including “receiving or transmitting data over a network” are well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (MPEP 2106.05(d)(II)).
Claims 9 and 24
Beyond the analysis of Claim 1, the additional limitations incorporated into Claim 9 (and similarly Claim 24) have been found to further limit the identified abstract idea of the parent claim. Claim 9 is directed to further limiting how the cross temperature is determined. Similar to determining the cross temperature of Claim 1’s Limitation (5), the Office has determined that the additional limitations of the dependent claims fall within the “Mental Processes” grouping of abstract ideas as the limitations may practically be performed in the human mind, including for example, observations, evaluations, judgements, and opinions (MPEP 2106.04(a)(2)(III)). Claim 9 comprises additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
While Claim 9 further recite an additional element of reading the write temperature from the non-volatile memory, the Office asserts the additional element fails to integrate the recited judicial exception into a practical application and the additional element is not sufficient to amount to significantly more than the judicial exception. The Office asserts the limitation amounts to insignificant extra-solution activity as the limitation amounts to mere data gathering or data output to which the courts have determined to be insignificant extra-solution activity (MPEP 2106.05(g)). Furthermore, the courts have recognized, similar to the elements of the limitation, that computer functions including “storing and retrieving information in memory” are well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (MPEP 2106.05(d)(II)).
Claims 10 and 25
Claim 10 (and similarly Claim 25) recites a limitation beyond that recited in parent Claim 1; the limitation is not found to further the identified “Mental Process” in the parent claim. However, Claim 10 is further directed to a judicial exception due to the identified “Mental Process” of Claim 1. Claim 10 comprises additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
While Claim 10 further recite an additional element of storing, reading, and transmitting cross temperature data, the Office asserts the additional element fails to integrate the recited judicial exception into a practical application and the additional element is not sufficient to amount to significantly more than the judicial exception. The Office asserts the limitation amounts to insignificant extra-solution activity as the limitation amounts to mere data gathering or data output to which the courts have determined to be insignificant extra-solution activity (MPEP 2106.05(g)). Furthermore, the courts have recognized, similar to the elements of the limitation, that computer functions including “storing and retrieving information in memory” or “receiving or transmitting data over a network” are well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (MPEP 2106.05(d)(II)).
Claim 13
Beyond the analysis of Claim 12, the additional limitations incorporated into Claim 13 have been found to further limit the identified abstract idea of the parent claim. Claim 13 is directed to limiting how the metric is chosen. Since the act of ‘selecting’ is equivalent to making a judgement or opinion, the Office has determined that the additional limitations of the dependent claims fall within the “Mental Processes” grouping of abstract ideas as the limitations may practically be performed in the human mind, including for example, observations, evaluations, judgements, and opinions (MPEP 2106.04(a)(2)(III)). Claim 13 comprises additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
While Claim 13 further recite an additional element of receiving the indication of the size of the buffer, the Office asserts the additional element fails to integrate the recited judicial exception into a practical application and the additional element is not sufficient to amount to significantly more than the judicial exception. The Office asserts the limitation amounts to insignificant extra-solution activity as the limitation amounts to mere data gathering or data output to which the courts have determined to be insignificant extra-solution activity (MPEP 2106.05(g)). Furthermore, the courts have recognized, similar to the elements of the limitation, that computer functions including “receiving or transmitting data over a network” are well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (MPEP 2106.05(d)(II)).
Claim 14
Beyond the analysis of Claim 12, the additional limitations incorporated into Claim 14 have been found to further limit the identified abstract idea of the parent claim. Claim 14 is directed to limiting the metric selected to be the quantity of logical addresses. Since the act of ‘selecting’ is equivalent to making a judgement or opinion, the Office has determined that the additional limitations of the dependent claims fall within the “Mental Processes” grouping of abstract ideas as the limitations may practically be performed in the human mind, including for example, observations, evaluations, judgements, and opinions (MPEP 2106.04(a)(2)(III)). Claim 14 comprises additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
While Claim 14 further recite an additional element of limiting the intended use of the command transmitted, the Office asserts the additional element fails to integrate the recited judicial exception into a practical application and the additional element is not sufficient to amount to significantly more than the judicial exception. The Office asserts the limitation amounts to insignificant extra-solution activity as the limitation amounts to mere data gathering or data output to which the courts have determined to be insignificant extra-solution activity (MPEP 2106.05(g)). Furthermore, the courts have recognized, similar to the elements of the limitation, that computer functions including “receiving or transmitting data over a network” are well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (MPEP 2106.05(d)(II)).
Claim 15
Beyond the analysis of Claim 12, the additional limitations incorporated into Claim 15 have been found to further limit the identified abstract idea of the parent claim. Claim 15 is directed to determining the second metric. Similar to the act of selecting the first metric of Claim 12’s Limitation (5), the Office has determined that the additional limitations of the dependent claims fall within the “Mental Processes” grouping of abstract ideas as the limitations may practically be performed in the human mind, including for example, observations, evaluations, judgements, and opinions (MPEP 2106.04(a)(2)(III)). Claim 15 comprises additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
While Claim 15 further recite an additional element of limiting the transmitted command to include certain data, the Office asserts the additional element fails to integrate the recited judicial exception into a practical application and the additional element is not sufficient to amount to significantly more than the judicial exception. The Office asserts the limitation amounts to insignificant extra-solution activity as the limitation amounts to mere data gathering or data output to which the courts have determined to be insignificant extra-solution activity (MPEP 2106.05(g)). Furthermore, the courts have recognized, similar to the elements of the limitation, that computer functions including “receiving or transmitting data over a network” are well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (MPEP 2106.05(d)(II)).
Claim 16
Beyond the analysis of Claim 15, the additional limitations incorporated into Claim 16 have been found to further limit the identified abstract idea of the parent claim. Claim 16 is directed to limiting how the second metric of the parent claim is determined. Similar to the act of selecting the first metric of Claim 12’s Limitation (5), the Office has determined that the additional limitations of the dependent claims fall within the “Mental Processes” grouping of abstract ideas as the limitations may practically be performed in the human mind, including for example, observations, evaluations, judgements, and opinions (MPEP 2106.04(a)(2)(III)). The claim does not comprise any additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
Claim 17
Beyond the analysis of Claim 15, the additional limitations incorporated into Claim 17 have been found to further limit the identified abstract idea of the parent claim. Claim 17 is directed to limiting how the second metric of the parent claim is determined. Similar to the act of selecting the first metric of Claim 12’s Limitation (5), the Office has determined that the additional limitations of the dependent claims fall within the “Mental Processes” grouping of abstract ideas as the limitations may practically be performed in the human mind, including for example, observations, evaluations, judgements, and opinions (MPEP 2106.04(a)(2)(III)). Claim 17 comprises additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
While Claim 17 further recite an additional element of receiving the indication, the Office asserts the additional element fails to integrate the recited judicial exception into a practical application and the additional element is not sufficient to amount to significantly more than the judicial exception. The Office asserts the limitation amounts to insignificant extra-solution activity as the limitation amounts to mere data gathering or data output to which the courts have determined to be insignificant extra-solution activity (MPEP 2106.05(g)). Furthermore, the courts have recognized, similar to the elements of the limitation, that computer functions including “receiving or transmitting data over a network” are well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (MPEP 2106.05(d)(II)).
Claim 23
Beyond the analysis of Claim 22, the additional limitations incorporated into Claim 23 have been found to further limit the identified abstract idea of the parent claim. Claim 23 is directed to choosing which logical addresses are to be written to the buffer. Since the act of ‘selecting’ is equivalent to making a judgement or opinion, the Office has determined that the additional limitations of the dependent claims fall within the “Mental Processes” grouping of abstract ideas as the limitations may practically be performed in the human mind, including for example, observations, evaluations, judgements, and opinions (MPEP 2106.04(a)(2)(III)). Claim 23 comprises additional elements requiring further analysis under Step 2A Prong 2 and Step 2B.
While Claim 23 further recite an additional element of sending the indication of a size of the buffer and receiving the indication of the quantity of logical addresses, the Office asserts the additional element fails to integrate the recited judicial exception into a practical application and the additional element is not sufficient to amount to significantly more than the judicial exception. The Office asserts the limitation amounts to insignificant extra-solution activity as the limitation amounts to mere data gathering or data output to which the courts have determined to be insignificant extra-solution activity (MPEP 2106.05(g)). Furthermore, the courts have recognized, similar to the elements of the limitation, that computer functions including “receiving or transmitting data over a network” are well-understood, routine, and conventional functions when they are claimed in a merely generic manner or as insignificant extra-solution activity (MPEP 2106.05(d)(II)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-10 and 19-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over MUCHHERLA et al (US PGPub 2023/0068702) in further view of MEKHANIK et al (US PGub 2022/0011967) and BUEB (US PGPub 2022/0057952).
With respect to Claim 1, MUCHHERLA discloses a memory system, comprising:
one or more memory devices (Fig 1A, Memory Device 130,140); and
processing circuitry (Fig 1A, Memory Sub-system Controller 115) coupled with the one or more memory devices and configured to cause the memory system to:
determine, in response to performing a read operation for a logical address, an indication of the logical address and a read temperature, for the logical address, of the memory system during the read operation (¶[0064] – “the control logic can determine a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to read the data is received. ¶[0034] – “In general, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. The memory sub-system controller 115 can be responsible for other operations such as … address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) that are associated with the memory devices 130.”);
determine, using the read temperature, a cross temperature for the logical address, the cross temperature representative of a difference between the read temperature and a write temperature of the memory system during a write operation for the logical address (Abstract – “the control logic determines a cross-temperature for the data based on the write temperature and a read temperature”); and
transmit an indication of the cross temperature for the logical address after determining the cross temperature using the read temperature from the buffer (Abstract – “determines, based on the cross-temperature and the program/erase cycle count, whether to perform a corrective action to calibrate a read voltage level to be applied to the memory array to read the data from the segment”).
MUCHHERLA may not explicitly disclose write, to a buffer of the memory system, an indication of the logical address and a temperature; and determine a cross temperature in response to detecting an empty command queue for a host system.
However, MEKHANIK discloses write, to a buffer of the memory system, an indication of the logical address and a temperature (¶[0122] – “The storage controller 104 may manage metadata that identifies logical addresses for which a logical erase block stores data … a storage controller 104 may store metadata … in a variety of locations, including … in volatile memory”; ¶[0123] – “the metadata includes a cross temperature for logical erase block”).
MUCHHERLA and MEKHANIK are analogous art because they are from the same field of endeavor of controlling access to memory based on temperature readings. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of MUCHHERLA and MEKHANIK before him or her, to modify the controller of MUCHHERLA to include storing temperature data as metadata as taught by MEKHANIK. A motivation for doing so would have been to track the metadata over time or to maintain a historical record (¶[0122]). Therefore, it would have been obvious to combine MUCHHERLA and MEKHANIK to obtain the invention as specified in the instant claims.
MUCHHERELA and MEKHANIK may not explicitly disclose determine a cross temperature in response to detecting an empty command queue for a host system.
However, BUEB discloses determine a cross temperature in response to detecting an empty command queue for a host system (¶[0014] – “When the memory system is idle (e.g. when the command queue is empty), the controller can determine the temperature of a memory device within the memory sub-system.”).
MUCHHERLA, MEKHANIK, and BUEB are analogous art because they are from the same field of endeavor of controlling access to memory based on temperature readings. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of MUCHHERLA, MEKHANIK, and BUEB before him or her, to modify the controller of the combination of MUCHHERLA and MEKHANIK to include calculating cross temperature data in response to detecting an empty command queue as taught by BUEB. A motivation for doing so would have been to defer performing the calculation until a time when the system is not under a processing load freeing processing resources for higher priority tasks. Therefore, it would have been obvious to combine MUCHHERLA, MEKHANIK, and BUEB to obtain the invention as specified in the instant claims.
With respect to Claim 18, MUCHHERLA discloses a method, comprising:
determining, in response to performing a read operation for a logical address, an indication of the logical address and a read temperature, for the logical address, of the memory system during the read operation (¶[0064] – “the control logic can determine a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to read the data is received. ¶[0034] – “In general, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. The memory sub-system controller 115 can be responsible for other operations such as … address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) that are associated with the memory devices 130.”);
determining, using the read temperature, a cross temperature for the logical address, the cross temperature representative of a difference between the read temperature and a write temperature of the memory system during a write operation for the logical address (Abstract – “the control logic determines a cross-temperature for the data based on the write temperature and a read temperature”); and
transmitting an indication of the cross temperature for the logical address after determining the cross temperature using the read temperature from the buffer (Abstract – “determines, based on the cross-temperature and the program/erase cycle count, whether to perform a corrective action to calibrate a read voltage level to be applied to the memory array to read the data from the segment”).
MUCHHERLA may not explicitly disclose writing, to a buffer of the memory system, an indication of the logical address and a temperature; and determining a cross temperature in response to detecting an empty command queue for a host system.
However, MEKHANIK discloses writing, to a buffer of the memory system, an indication of the logical address and a temperature (¶[0122] – “The storage controller 104 may manage metadata that identifies logical addresses for which a logical erase block stores data … a storage controller 104 may store metadata … in a variety of locations, including … in volatile memory”; ¶[0123] – “the metadata includes a cross temperature for logical erase block”).
MUCHHERLA and MEKHANIK are analogous art because they are from the same field of endeavor of controlling access to memory based on temperature readings. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of MUCHHERLA and MEKHANIK before him or her, to modify the controller of MUCHHERLA to include storing temperature data as metadata as taught by MEKHANIK. A motivation for doing so would have been to track the metadata over time or to maintain a historical record (¶[0122]). Therefore, it would have been obvious to combine MUCHHERLA and MEKHANIK to obtain the invention as specified in the instant claims.
MUCHHERELA and MEKHANIK may not explicitly disclose determining a cross temperature in response to detecting an empty command queue for a host system.
However, BUEB discloses determining a cross temperature in response to detecting an empty command queue for a host system (¶[0014] – “When the memory system is idle (e.g. when the command queue is empty), the controller can determine the temperature of a memory device within the memory sub-system.”).
MUCHHERLA, MEKHANIK, and BUEB are analogous art because they are from the same field of endeavor of controlling access to memory based on temperature readings. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of MUCHHERLA, MEKHANIK, and BUEB before him or her, to modify the controller of the combination of MUCHHERLA and MEKHANIK to include calculating cross temperature data in response to detecting an empty command queue as taught by BUEB. A motivation for doing so would have been to defer performing the calculation until a time when the system is not under a processing load freeing processing resources for higher priority tasks. Therefore, it would have been obvious to combine MUCHHERLA, MEKHANIK, and BUEB to obtain the invention as specified in the instant claims.
With respect to Claims 2 and 19, the combination of MUCHHERLA, MEKHANIK, and BUEB disclose the system/method of each respective parent claim.
MEKHANIK further discloses receiving a command for the memory system to collect cross temperature information for logical addresses (¶[0077] – “metadata 118 may be stored and maintained by a storage controller 104”; ¶[0137] – “the metadata includes one or more of a cross temperature for logical erase block”), wherein the indication of the logical address and the read temperature are written to the buffer in response to receiving the command (¶[0122] – “The storage controller 104 may manage metadata that identifies logical addresses for which a logical erase block stores data … a storage controller 104 may store metadata … in a variety of locations, including … in volatile memory”; ¶[0123] – “the metadata includes a cross temperature for logical erase block”).
With respect to Claims 3 and 20, the combination of MUCHHERLA, MEKHANIK, and BUEB disclose the system/method of each respective parent claim.
MEKHANIK further discloses wherein the logical address and the read temperature are written to the buffer after a second logical address and a second read temperature for the second logical address are written to the buffer (¶[0122] – “a storage controller 104 may associate metadata, also referred to as media characteristics, with one or more of the storage blocks (logical erase blocks, physical erase blocks, logical pages, and/or physical pages)”; ¶[0077] – “metadata 118 may be stored and maintained by a storage controller 104”; ¶[0137] – “the metadata includes one or more of a cross temperature for logical erase block”).
MUCHHERLA further discloses the method further comprising: determining the read temperature for the logical address in response to determining that a threshold quantity of logical addresses have been targeted for reading since receipt of a read command for the second logical address (¶[0019] – “When a read command is received at the memory device from either the memory sub-system controller or host system, the control logic on the memory device can identify the segment of the memory device to be read and determine whether the write temperature of the requested data is stored in the flag byte associated with that segment. If so, the control logic can determine the cross-temperature (i.e., a difference between the write temperature and the ambient temperature at the time when the read command is received) and a number of program/erase cycles associated with the segment. Depending on the embodiment, the number of program/erase cycles can be read from the flag byte or received in connection with the read command. In one embodiment, using the cross-temperature and the number of program/erase cycles as inputs, the control logic can determine a read voltage offset (e.g., from a look-up table or other data structure stored on the memory device). In one embodiment, the control logic can further determine whether the cross-temperature satisfies a threshold criterion (e.g., is greater than or equal to a threshold level), and if so determine whether the number of program/erase cycles satisfies a threshold criterion (e.g., is greater than or equal to a threshold level). If both the cross-temperature and the number of program/erase cycles satisfy the respective threshold criterions, the control logic can take corrective action to calibrate the read voltage offset before causing the read voltage to be applied to a memory array of the memory device to read the requested data”).
With respect to Claims 4 and 21, the combination of MUCHHERLA, MEKHANIK, and BUEB disclose the system/method of each respective parent claim.
MUCHHERLA further discloses transmitting an indication of a size of the buffer; and receiving an indication of the threshold quantity in response to transmitting an indication of the size of the buffer (¶[0037] – “For example, memory interface component 113 can send memory access commands corresponding to requests received from host system 120 to memory device 130, such as program commands, read commands, or other commands. In addition, memory interface component 113 can receive data from memory device 130, such as data retrieved in response to a read command or a confirmation that a program command was successfully performed”).
With respect to Claim 5, the combination of MUCHHERLA, MEKHANIK, and BUEB disclose the memory system of claim 3.
MUCHHERLA further discloses wherein the threshold quantity is randomly generated by the memory system (¶[0017] – “Still other memory devices attempt to reduce error rates by calibrating the read voltage level based on a number of program/erase cycles performed on a given segment (e.g., page or block) of the memory device. As the number of program/erase cycles can vary greatly per segment, such tracking can be complicated and require numerous expensive additional data structures to be maintained by the memory sub-system”).
With respect to Claims 6 and 22, the combination of MUCHHERLA, MEKHANIK, and BUEB disclose the system/method of each respective parent claim.
MEKHANIK further discloses wherein the logical address is included in a set of logical addresses selected for writing to the buffer, and wherein a respective read temperature for each logical address in the set of logical addresses is written to the buffer (¶[0122] – “The storage controller 104 may manage metadata that identifies logical addresses for which a logical erase block stores data … a storage controller 104 may store metadata … in a variety of locations, including … in volatile memory”; ¶[0123] – “the metadata includes a cross temperature for logical erase block”).
With respect to Claim 7, the combination of MUCHHERLA, MEKHANIK, and BUEB disclose the memory system of claim 6.
MEKHANIK further discloses wherein the processing circuitry is further configured to cause the memory system to: receive an indication of a quantity of logical addresses for which temperature information is to be collected, wherein the set of logical addresses is selected in accordance with the quantity (¶[0122] – “The storage controller 104 may manage metadata that identifies logical addresses for which a logical erase block stores data … a storage controller 104 may store metadata … in a variety of locations, including … in volatile memory”; ¶[0123] – “the metadata includes a cross temperature for logical erase block”).
With respect to Claim 8, the combination of MUCHHERLA, MEKHANIK, and BUEB disclose the memory system of claim 7.
MUCHHERLA further discloses wherein the processing circuitry is further configured to cause the memory system to: transmit an indication of a size of the buffer, wherein the indication of the quantity of logical addresses in received in response to transmitting an indication of the size of the buffer (¶[0037] – “For example, memory interface component 113 can send memory access commands corresponding to requests received from host system 120 to memory device 130, such as program commands, read commands, or other commands. In addition, memory interface component 113 can receive data from memory device 130, such as data retrieved in response to a read command or a confirmation that a program command was successfully performed”).
With respect to Claims 9 and 24, the combination of MUCHHERLA, MEKHANIK, and BUEB disclose the system/method of each respective parent claim.
BUEB further discloses reading the write temperature for the logical address from a non-volatile memory in response to detecting the empty command queue (¶[0014] – “When the memory system is idle (e.g. when the command queue is empty), the controller can determine the temperature of a memory device within the memory sub-system.”).
MUCHHERLA further discloses wherein the cross temperature is determined using the write temperature (Abstract – “the control logic determines a cross-temperature for the data based on the write temperature and a read temperature”).
With respect to Claims 10 and 25, the combination of MUCHHERLA, MEKHANIK, and BUEB disclose the system/method of each respective parent claim. further comprising:
MEKHANIK further discloses storing the cross temperature in a non-volatile memory of the memory system in response to determining the cross temperature (¶[0122] – “The storage controller 104 may manage metadata that identifies logical addresses for which a logical erase block stores data … a storage controller 104 may store metadata … in a variety of locations, including … in volatile memory”; ¶[0123] – “the metadata includes a cross temperature for logical erase block”); and
MUCHHERLA further discloses reading the cross temperature from the non-volatile memory in response to a message requesting the cross temperature, wherein the cross temperature is transmitted after reading the cross temperature from the non-volatile memory (¶[0037] – “For example, memory interface component 113 can send memory access commands corresponding to requests received from host system 120 to memory device 130, such as program commands, read commands, or other commands. In addition, memory interface component 113 can receive data from memory device 130, such as data retrieved in response to a read command or a confirmation that a program command was successfully performed”).
With respect to Claim 23, the combination of MUCHHERLA, MEKHANIK, and BUEB disclose the method of claim 22.
MUCHHERLA further discloses transmitting an indication of a size of the buffer (¶[0037] – “For example, memory interface component 113 can send memory access commands corresponding to requests received from host system 120 to memory device 130, such as program commands, read commands, or other commands. In addition, memory interface component 113 can receive data from memory device 130, such as data retrieved in response to a read command or a confirmation that a program command was successfully performed”).
MEKHANIK further discloses receiving, in response to transmitting an indication of the size of the buffer, an indication of a quantity of logical addresses for which temperature information is to be collected, wherein the set of logical addresses is selected in accordance with the quantity (¶[0122] – “The storage controller 104 may manage metadata that identifies logical addresses for which a logical erase block stores data … a storage controller 104 may store metadata … in a variety of locations, including … in volatile memory”; ¶[0123] – “the metadata includes a cross temperature for logical erase block”).
Claim(s) 12-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over MUCHHERLA.
With respect to Claim 12, MUCHHERLA discloses a host system, comprising:
one or more interfaces comprising one or more signal paths operable for communication with one or more memory systems (Fig 1A illustrates host system 120 coupled to memory sub-system 110); and
processing circuitry (Fig 1A, Memory Sub-system Controller 115) coupled with the one or more interfaces and configured to cause the host system to:
select a metric for a memory system of the one or more memory systems to use in collecting cross temperature information for logical addresses, wherein the cross temperature information for a logical address represents a difference between a read temperature of the memory system during a read operation for the logical address and a write temperature of the memory system during a write operation for the logical address (¶[0064] – “the control logic can determine a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to read the data is received. ¶[0034] – “In general, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. The memory sub-system controller 115 can be responsible for other operations such as … address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) that are associated with the memory devices 130.”. A ‘metric’ may be either read or write temperature or even the units for the measurement {e.g. Fahrenheit or Celsius});
MUCHHERLA may not explicitly disclose transmit a command for the memory system to collect the cross temperature information for logical addresses in accordance with the metric, wherein the command indicates the metric, transmit, in response to transmitting the command, a message requesting the cross temperature information collected by the memory system in accordance with the metric; and receive, in response to transmitting the message, the cross temperature information collected by the memory system in accordance with the metric.
However, MUCHHERLA states at ¶[0037] that “For example, memory interface component 113 can send memory access commands corresponding to requests received from host system 120 to memory device 130, such as program commands, read commands, or other commands. In addition, memory interface component 113 can receive data from memory device 130, such as data retrieved in response to a read command or a confirmation that a program command was successfully performed” which at least suggests MUCHHERLA may send and receive various commands to different entities of the memory sub-system to exchange information. As such, with the suggestions asserted by MUCHHERLA, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have taken into consideration MUCHHERLA’s explicit teachings and suggestions to have been able to modify MUCHHERLA’s explicit teachings such that commands and messages may be transmitted and respective information collected with a reasonable expectation of success. A motivation for doing so would have been to enable communication between components that control different aspects of the memory sub-system including a temperature sensor for gathering temperature readings and a memory sub-system controller for determining an action responsive to a temperature reading.
With respect to Claim 13, MUCHHERLA discloses the host system of claim 12.
MUCHHERLA further discloses wherein the processing circuitry is further configured to cause the host system to: receive an indication of a size of a buffer used by the memory system to collect the cross temperature information, wherein the metric is selected in accordance with the size of the buffer (¶[0037] – “For example, memory interface component 113 can send memory access commands corresponding to requests received from host system 120 to memory device 130, such as program commands, read commands, or other commands. In addition, memory interface component 113 can receive data from memory device 130, such as data retrieved in response to a read command or a confirmation that a program command was successfully performed”).
With respect to Claim 14, MUCHHERLA discloses the host system of claim 12.
MUCHHERLA further discloses wherein the metric comprises a quantity of logical addresses, and wherein the command is for the memory system to collect cross temperature information for at least one logical address for each set of logical addresses that is targeted for reading and that comprises the quantity (¶[0122] – “The storage controller 104 may manage metadata that identifies logical addresses for which a logical erase block stores data … a storage controller 104 may store metadata … in a variety of locations, including … in volatile memory”; ¶[0123] – “the metadata includes a cross temperature for logical erase block”).
With respect to Claim 15, MUCHHERLA discloses the host system of claim 12.
MUCHHERLA further discloses wherein the processing circuitry is further configured to cause the host system to: determine a second metric for the memory system to use in collecting cross temperature information for logical addresses, wherein the command indicates the second metric (¶[0064] – “the control logic can determine a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to read the data is received. ¶[0034] – “In general, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. The memory sub-system controller 115 can be responsible for other operations such as … address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) that are associated with the memory devices 130.”. A ‘metric’ may be either read or write temperature or even the units for the measurement {e.g. Fahrenheit or Celsius}).
With respect to Claim 16, MUCHHERLA discloses the host system of claim 15.
MUCHHERLA further discloses wherein the second metric comprises a quantity of logical addresses for which the memory system is to collect cross temperature information on a periodic basis (¶[0122] – “The storage controller 104 may manage metadata that identifies logical addresses for which a logical erase block stores data … a storage controller 104 may store metadata … in a variety of locations, including … in volatile memory”; ¶[0123] – “the metadata includes a cross temperature for logical erase block”).
With respect to Claim 17, MUCHHERLA discloses the host system of claim 15.
MUCHHERLA further discloses wherein the processing circuitry is further configured to cause the host system to: receive an indication of a size of a buffer used by the memory system to collect the cross temperature information, wherein the second metric is selected in accordance with the size of the buffer and in accordance with the metric (¶[0037] – “For example, memory interface component 113 can send memory access commands corresponding to requests received from host system 120 to memory device 130, such as program commands, read commands, or other commands. In addition, memory interface component 113 can receive data from memory device 130, such as data retrieved in response to a read command or a confirmation that a program command was successfully performed”).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over MUCHHERLA in further view of MEKHANIK, BUEB, and VASHI et al (US PGPub 2020/0211664).
With respect to Claim 11, the combination of MUCHHERLA, MEKHANIK, and BUEB disclose the memory system of claim 1.
MUCHHERLA, MEKHANIK, and BUEB may not explicitly disclose wherein the processing circuitry is further configured to cause the memory system to: trigger a refresh operation for a set of memory cells associated with the logical address in accordance with the cross temperature for the logical address.
However, VASHI discloses wherein the processing circuitry is further configured to cause the memory system to: trigger a refresh operation for a set of memory cells associated with the logical address in accordance with the cross temperature for the logical address (¶[0021] – “ if a sample page of a block of a memory device fails a scan and a cross temperature delta between write temperature and scan temperature of the page is within a certain threshold for a cross temperature delta, a refresh is triggered”).
MUCHHERLA, MEKHANIK, BUEB, and VASHI are analogous art because they are from the same field of endeavor of controlling access to memory based on temperature readings. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of MUCHHERLA, MEKHANIK, BUEB, and VASHI before him or her, to modify the controller of the combination of MUCHHERLA, MEKHANIK, and BUEB to include performing a refresh operation when a cross temperature meets a threshold as taught by VASHI. A motivation for doing so would have been to prevent unrecoverable errors in blocks and extend the life of the block of memory due to the blocks being subject to more bake if the block is not refreshed (¶[0022]). Therefore, it would have been obvious to combine MUCHHERLA, MEKHANIK, BUEB, and VASHI to obtain the invention as specified in the instant claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure teach related methods for cross temperature memory management.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T LOONAN whose telephone number is (571)272-6994. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC T LOONAN/Examiner, Art Unit 2137
Prosecution Insights