DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR 10-2022-0139380, filed on 10/26/2022.
Applicant’s claim for the benefit of a prior-filed application 18/301781 under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/15/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Preliminary Amendment
The preliminary amendment filed on 09/30/2025 was entered, claims 1-11 examined.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12386549, in view of Lamb (US 20150317248)
Instant application 19270088
U.S. Patent No. 12386549
1. A storage device comprising:
a memory including a plurality of first type memory blocks and a plurality of second type memory blocks;
and a controller configured to:
determine a write area including at least one first type memory block among the plurality of first type memory blocks,
determine to enter a power off state when receiving a power off request under a threshold condition,
add at least one target memory block selected from among the plurality of second type memory blocks to the write area,
store write data cached in a buffer of the controller to the write area before entering the power off state,
wherein the second type memory blocks operate at a higher speed than the first type memory blocks,
and wherein the controller is configured to determine that the threshold condition is satisfied when at least one of:
garbage collection is being executed for the memory,
a background operation other than the garbage collection is being executed for the memory, or a size of free space in the write area is less than or equal to a threshold value.
1. A storage device comprising:
a memory including a plurality of first type memory blocks and a plurality of second type memory blocks;
and a controller configured to:
determine a write buffer including at least one first type memory block among the plurality of first type memory blocks,
the write buffer temporarily storing write data,
when a power off request is received under a threshold condition,
add at least one target memory block selected from among the plurality of second type memory blocks to the write buffer,
wherein the second type memory blocks operate at a higher speed than the first type memory blocks,
and wherein the controller is configured to determine that the threshold condition is satisfied when
garbage collection is being executed for the memory.
Regarding Claim 1, Claim 1 of U.S. Patent No. 12386549 discloses all limitations except for the limitation store write data cached in a buffer of the controller to the write area before entering the power off state,
However, Lamb (US 20150317248) teaches store write data cached in a buffer of the controller to the write area before entering the power off state (Lamb FIG. 1 [0017] the storage controller 110 writes the host data to a write cache 135. [0018] The transfer logic 125 detects a loss of power to the storage controller 110 and upon power loss, copies any data still in the write cache 135 to non-volatile memory 155.)
U.S. Patent No. 12386549 and Lamb are analogous art because they are from the same field of endeavor of data protection. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of U.S. Patent No. 12386549 and Lamb to modify the U.S. Patent No. 12386549 storage controlling write buffer while processing power off request with Lamb’s teaching storing write data cached in controller buffer to write area upon power loss. The motivation for doing so would be to (Lamb [0001]) saving data upon loss of power…and carrying out this emergency data save procedure.
Claim 1 of instant application is unpatentable over claim 1 of U.S. Patent No. 12386549, in view of Lamb (US 20150317248).
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12386549, in view of Lamb (US 20150317248)
Instant application 19270088
U.S. Patent No. 12386549
2. The storage device according to claim 1,
wherein, when the threshold condition is satisfied, the controller is configured to set a throughput of an operation of storing the write data in the write area to be less than or equal to a threshold throughput.
4. The storage device according to claim 1,
wherein, when the threshold condition is satisfied, the controller is configured to set a throughput of an operation of storing write data in the write buffer to be less than or equal to a threshold throughput.
U.S. Patent No. 12386549 claim 4 discloses all limitations of instant claim 2.
Claim 2 of instant application is unpatentable over claim 1 of U.S. Patent No. 12386549, in view of Lamb (US 20150317248).
Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12386549, in view of Lamb (US 20150317248)
Instant application 19270088
U.S. Patent No. 12386549
3. The storage device according to claim 1,
wherein the controller is configured to select the at least one target memory block from at least one of a first memory area and a second memory area,
the first memory area including over-provisioning memory blocks among the second type memory blocks,
the second memory area including memory blocks allocated to store meta data among the second type memory blocks.
5 The storage device according to claim 1, wherein the controller is configured to select the at least one target memory block from at least one of a first memory area and a second memory area,
the first memory area including over-provisioning memory blocks among the second type memory blocks,
the second memory area including memory blocks allocated to store meta data among the second type memory blocks.
U.S. Patent No. 12386549 claim 5 discloses all limitations of instant claim 3.
Claim 3 of instant application is unpatentable over claim 1 of U.S. Patent No. 12386549, in view of Lamb (US 20150317248).
Claim 4 is rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12386549, in view of Lamb (US 20150317248)
Instant application 19270088
U.S. Patent No. 12386549
4. The storage device according to claim 3, wherein the controller is configured to:
select the at least one target memory block from the first memory area when a number of reserved memory blocks among the over-provisioning memory blocks is greater than or equal to a threshold number,
and select the at least one target memory block from the second memory area when the number of reserved memory blocks is less than the threshold number.
6. The storage device according to claim 5, wherein the controller is configured to:
select the at least one target memory block from the first memory area when a number of reserved memory blocks among the over-provisioning memory blocks is greater than or equal to a threshold number,
and select the at least one target memory block from the second memory area when the number of reserved memory blocks is less than the threshold number.
U.S. Patent No. 12386549 claim 6 discloses all limitations of instant claim 4.
Claim 4 of instant application is unpatentable over claim 1 of U.S. Patent No. 12386549, in view of Lamb (US 20150317248).
Claim 5 is rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12386549, in view of Lamb (US 20150317248)
Instant application 19270088
U.S. Patent No. 12386549
5. The storage device according to claim 4, wherein the at least one target memory block is selected from among the reserved memory blocks.
6. The storage device according to claim 5,
select the at least one target memory block from the second memory area when the number of reserved memory blocks is less than the threshold number
U.S. Patent No. 12386549 claim 6 discloses all limitations of instant claim 5.
Claim 5 of instant application is unpatentable over claim 1 of U.S. Patent No. 12386549, in view of Lamb (US 20150317248).
Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12386549, in view of Lamb (US 20150317248)
Instant application 19270088
U.S. Patent No. 12386549
6. The storage device according to claim 4,
wherein the at least one target memory block is selected from among the memory blocks
allocated to store meta data
5. The storage device according to claim 1,
wherein the controller is configured to select the at least one target memory block from at least one of a first memory area and a second memory area,
the first memory area including over-provisioning memory blocks among the second type memory blocks, the second memory area including memory blocks allocated to store meta data among the second type memory blocks.
U.S. Patent No. 12386549 claim 5 discloses all limitations of instant claim 6.
Claim 6 of instant application is unpatentable over claim 1 of U.S. Patent No. 12386549, in view of Lamb (US 20150317248).
Claim 7 is rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12386549, in view of Lamb (US 20150317248)
Instant application 19270088
U.S. Patent No. 12386549
7. The storage device according to claim 4,
wherein,
when a number of reserved memory blocks among the over-provisioning memory blocks is greater than or equal to the threshold number,
the at least one target memory block is selected from among the reserved memory blocks, and wherein, when the number of reserved memory blocks is less than the threshold number,
the at least one target memory block is selected from among the memory blocks allocated to store meta data.
6.The storage device according to claim 5, wherein the controller is configured to: select the at least one target memory block from the first memory area
when a number of reserved memory blocks among the over-provisioning memory blocks is greater than or equal to a threshold number,
and select the at least one target memory block from the second memory area when the number of reserved memory blocks is less than the threshold number.
5. the second memory area including memory blocks allocated to store meta data among the second type memory blocks
U.S. Patent No. 12386549 claim 5-6 discloses all limitations of instant claim 7.
Claim 7 of instant application is unpatentable over claim 1 of U.S. Patent No. 12386549, in view of Lamb (US 20150317248).
Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12386549, in view of Lamb (US 20150317248)
Instant application 19270088
U.S. Patent No. 12386549
8. The storage device according to claim 1,
wherein the controller is configured to
add the at least one target memory block to the write area
when storing the write data to the write area is delayed.
1. A storage device comprising:
wherein the controller is configured to
select the at least one target memory block from at least one of a first memory area and a second memory area,
add at least one target memory block selected from among the plurality of second type memory blocks to the write buffer,
and wherein the controller is configured to determine that the threshold condition is satisfied
when garbage collection is being executed for the memory.
(i.e., when garbage collection is being executed for the memory is an obvious condition when storing the write data to the write area is delayed because of the garbage collection is performed on the memory)
U.S. Patent No. 12386549 claim 1 discloses all limitations of instant claim 8.
Claim 8 of instant application is unpatentable over claim 1 of U.S. Patent No. 12386549, in view of Lamb (US 20150317248).
Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12386549, in view of Lamb (US 20150317248)
Instant application 19270088
U.S. Patent No. 12386549
9. A storage device comprising:
a memory including a plurality of first type memory blocks and a plurality of second type memory blocks;
and a controller configured to:
determine a write area including at least one first type memory block among the plurality of first type memory blocks,
determine to enter a power off state when receiving a power off request,
add at least one target memory block selected from among the plurality of second type memory blocks to the write area,
and store write data cached in a buffer of the controller to the write area before entering the power off state,
wherein the second type memory blocks operate at a higher speed than the first type memory blocks,
wherein entering the power off state
is determined based on whether storing the write data to the write area is delayed,
and wherein the at least one target memory block is added to the write area
when storing the write data to the write area is delayed.
1. A storage device comprising:
a memory including a plurality of first type memory blocks and a plurality of second type memory blocks;
and a controller configured to:
determine a write buffer including at least one first type memory block among the plurality of first type memory blocks,
the write buffer temporarily storing write data,
when a power off request is received under a threshold condition,
add at least one target memory block selected from among the plurality of second type memory blocks to the write buffer,
wherein the second type memory blocks operate at a higher speed than the first type memory blocks,
and wherein the controller is configured to
determine that the threshold condition is satisfied when garbage collection is being executed for the memory.
add at least one target memory block selected from among the plurality of second type memory blocks to the write buffer,
(i.e., when garbage collection is being executed for the memory is an obvious condition when storing the write data to the write area is delayed because of the garbage collection is performed on the memory)
Regarding Claim 9, Claim 1 of U.S. Patent No. 12386549 discloses all limitations except for the limitation and store write data cached in a buffer of the controller to the write area before entering the power off state,
However, Lamb (US 20150317248) teaches store write data cached in a buffer of the controller to the write area before entering the power off state (Lamb FIG. 1 [0017] the storage controller 110 writes the host data to a write cache 135. [0018] The transfer logic 125 detects a loss of power to the storage controller 110 and upon power loss, copies any data still in the write cache 135 to non-volatile memory 155.)
U.S. Patent No. 12386549 and Lamb are analogous art because they are from the same field of endeavor of data protection. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of U.S. Patent No. 12386549 and Lamb to modify the U.S. Patent No. 12386549 storage controlling write buffer while processing power off request with Lamb’s teaching storing write data cached in controller buffer to write area upon power loss. The motivation for doing so would be to (Lamb [0001]) saving data upon loss of power…and carrying out this emergency data save procedure.
Claim 9 of instant application is unpatentable over claim 1 of U.S. Patent No. 12386549, in view of Lamb (US 20150317248).
Claim 10 is rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12386549, in view of Lamb (US 20150317248)
Instant application 19270088
U.S. Patent No. 12386549
10. The storage device according to claim 9,
wherein the controller is configured to determine that storing the write data to the write area is delayed
when at least one of: garbage collection is being executed for the memory, a background operation other than the garbage collection is being executed for the memory, or a size of free space in the write area is less than or equal to a threshold value.
1. A storage device comprising:
and wherein the controller is configured to determine that the threshold condition is satisfied
when garbage collection is being executed for the memory.
(i.e., when garbage collection is being executed for the memory is an obvious condition when storing the write data to the write area is delayed because of the garbage collection is performed on the memory)
U.S. Patent No. 12386549 claim 1 discloses all limitations of instant claim 10.
Claim 10 of instant application is unpatentable over claim 1 of U.S. Patent No. 12386549, in view of Lamb (US 20150317248).
Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over U.S. Patent No. 12386549, in view of Lamb (US 20150317248)
Instant application 19270088
U.S. Patent No. 12386549
11. The storage device according to claim 9,
wherein, when storing the write data to the write area is delayed, the controller is configured to set a throughput of an operation of storing the write data to the write area to be less than or equal to a threshold throughput.
.
4. The storage device according to claim 1,
wherein, when the threshold condition is satisfied, the controller is configured to set a throughput of an operation of storing write data in the write buffer to be less than or equal to a threshold throughput.
U.S. Patent No. 12386549 claim 4 discloses all limitations of instant claim 11.
Claim 11 of instant application is unpatentable over claim 1 of U.S. Patent No. 12386549, in view of Lamb (US 20150317248).
Allowable Subject Matter
Claim 3-7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Also, they would be allowable contingent on overcoming double patenting rejection.
REASONS FOR ALLOWANCE
For claim 3, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 3 depends.
For claim 4, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 4 depends. Additionally, claim 4 is allowable based on dependency from claim 3.
For claim 5, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 5 depends. Additionally, claim 5 is allowable based on dependency from claim 4.
For claim 6, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 6 depends. Additionally, claim 6 is allowable based on dependency from claim 4.
For claim 7, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 7 depends. Additionally, claim 7 is allowable based on dependency from claim 4.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son (US 20230236765), in view of Lee (US 20200042243).
Regarding Claim 1, Son teaches
A storage device comprising: (Son [0023] FIG. 1, a storage device 100)
a memory including a plurality of first type memory blocks and a plurality of second type memory blocks; (Son [0038] the user memory block of the user memory 121a may be implemented in a first type, and the PLP memory block of the PLP memory 121b may be implemented in a second type. The first type may refer to a type appropriate for managing a large amount of data. The second type may refer to a type appropriate for high reliability and fast write. [0039] The second-type memory block may be implemented with a single level cell (SLC) storing one bit.)
and a controller configured to: determine a write area including at least one first type memory block among the plurality of first type memory blocks, (Son [0038] the user memory block of the user memory 121a may be implemented in a first type [0039] the first-type memory block may be implemented with one of cells, which store a plurality of bits, such as a multi-level cell (MLC) storing 2 bits, a triple level cell storing 3 bits, and a quadruple level cell (QLC) storing 4 bits.)
determine to enter a power off state when receiving a power off request under a threshold condition, (Son [0037] When a power-off request is generated while the write request is processed, the PLP memory 121b may store data present in the buffer memory 111a instead of the user memory 121a.)
add at least one target memory block selected from among the plurality of second type memory blocks to the write area, (Son [0037] When a power-off request is generated while the write request is processed, the PLP memory 121b may store data present in the buffer memory 111a instead of the user memory 121a.) (i.e., store data in the PLP memory is effectively add second type memory block to the write area)
store write data cached in a buffer of the controller to the write area before entering the power off state, (Son [0037] The power-off request may be used to request pre-processing for the purpose of preventing the loss of data before the power supply to the storage device 100 is interrupted (or blocked). [0043] The storage controller 110 may include a volatile memory device 111 [0046] The volatile memory device 111 may include the buffer memory 111a. [0029] The buffer memory 111a may temporarily store data received from the host 11 and/or may temporarily store data received from the non-volatile memory device 120.) (i.e., data cached in volatile buffer of the controller is stored in non-volatile memory device before power off)
wherein the second type memory blocks operate at a higher speed than the first type memory blocks, (Son [0038] The second type may refer to a type appropriate for high reliability and fast write. [0039] The second-type memory block may be implemented with a single level cell (SLC) storing one bit. [0039] the first-type memory block may be implemented with one of cells, which store a plurality of bits, such as a multi-level cell (MLC) storing 2 bits, a triple level cell storing 3 bits, and a quadruple level cell (QLC) storing 4 bits.) (i.e., second type memory block implemented with SLC operate at a higher speed than first type memory block implemented with MLC/QLC)
and wherein the controller is configured to determine that the threshold condition is satisfied when at least one of: garbage collection is being executed for the memory, a background operation other than the garbage collection is being executed for the memory, (Son [0004] As a large over provisioning (OP) region is allocated for frequent garbage collection, wear leveling, and bad block management, an available storage capacity of the storage device may be decreased)(i.e., wear leveling is a background operation other than the garbage collection)
or a size of free space in the write area is less than or equal to a threshold value.
Son does not teach determine to enter a power off state when receiving a power off request under a threshold condition, and wherein the controller is configured to determine that the threshold condition is satisfied when at least one of: garbage collection is being executed for the memory, a background operation other than the garbage collection is being executed for the memory, or a size of free space in the write area is less than or equal to a threshold value.
However, Lee teaches under a threshold condition, and wherein the controller is configured to determine that the threshold condition is satisfied when at least one of: garbage collection is being executed for the memory, a background operation other than the garbage collection is being executed for the memory, (Lee [0052] the memory system 110 can move a large amount of data during wear leveling or garbage collection. [0052] a power issue may arise in the process of moving a large amount of data. A large amount of data may not be transferred to the second memory block 40_2 due to internal or external factors such as sudden power-off (SPO) in which the powersupply is interrupted)
Son and Lee are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Son and Lee to modify Son‘s power-off with Lee’s teaching of garbage collection and wear leveling as a threshold/delay condition. The motivation for doing so would be the need to prevent data loss when power-off under threshold/delay condition because (Lee [0052]) memory system can move a large amount of data during wear leveling or garbage collection.
Regarding Claim 8, Son and Lee teach
The storage device according to claim 1, wherein the controller is configured to add the at least one target memory block to the write area when storing the write data to the write area is delayed. (Son [0004] As a large over provisioning (OP) region is allocated for frequent garbage collection, wear leveling, and bad block management, an available storage capacity of the storage device may be decreased [0037] When a power-off request is generated while the write request is processed, the PLP memory 121b may store data present in the buffer memory 111a instead of the user memory 121a.) (i.e., store data in the PLP memory is effectively add second type memory block to the write area. when performing garbage collection, wear leveling and bad block management, an available storage capacity is decreased, therefore storing the write data to the write area is delayed, adding memory block to the write area can improve performance)
Regarding Claim 9, Son teaches
A storage device comprising: (Son [0023] FIG. 1, a storage device 100)
a memory including a plurality of first type memory blocks and a plurality of second type memory blocks; (Son [0038] the user memory block of the user memory 121a may be implemented in a first type, and the PLP memory block of the PLP memory 121b may be implemented in a second type. The first type may refer to a type appropriate for managing a large amount of data. The second type may refer to a type appropriate for high reliability and fast write. [0039] The second-type memory block may be implemented with a single level cell (SLC) storing one bit.)
and a controller configured to: determine a write area including at least one first type memory block among the plurality of first type memory blocks, (Son [0038] the user memory block of the user memory 121a may be implemented in a first type [0039] the first-type memory block may be implemented with one of cells, which store a plurality of bits, such as a multi-level cell (MLC) storing 2 bits, a triple level cell storing 3 bits, and a quadruple level cell (QLC) storing 4 bits.)
determine to enter a power off state when receiving a power off request (Son [0037] When a power-off request is generated while the write request is processed, the PLP memory 121b may store data present in the buffer memory 111a instead of the user memory 121a.)
add at least one target memory block selected from among the plurality of second type memory blocks to the write area, (Son [0037] When a power-off request is generated while the write request is processed, the PLP memory 121b may store data present in the buffer memory 111a instead of the user memory 121a.) (i.e., store data in the PLP memory is effectively add second type memory block to the write area)
and store write data cached in a buffer of the controller to the write area before entering the power off state, (Son [0037] The power-off request may be used to request pre-processing for the purpose of preventing the loss of data before the power supply to the storage device 100 is interrupted (or blocked). [0043] The storage controller 110 may include a volatile memory device 111 [0046] The volatile memory device 111 may include the buffer memory 111a. [0029] The buffer memory 111a may temporarily store data received from the host 11 and/or may temporarily store data received from the non-volatile memory device 120.) (i.e., data cached in volatile buffer of the controller is stored in non-volatile memory device before power off)
wherein the second type memory blocks operate at a higher speed than the first type memory blocks, (Son [0038] The second type may refer to a type appropriate for high reliability and fast write. [0039] The second-type memory block may be implemented with a single level cell (SLC) storing one bit. [0039] the first-type memory block may be implemented with one of cells, which store a plurality of bits, such as a multi-level cell (MLC) storing 2 bits, a triple level cell storing 3 bits, and a quadruple level cell (QLC) storing 4 bits.) (i.e., second type memory block implemented with SLC operate at a higher speed than first type memory block implemented with MLC/QLC)
wherein entering the power off state is determined based on whether storing the write data to the write area is delayed, and wherein the at least one target memory block is added to the write area when storing the write data to the write area is delayed. (Son [0004] As a large over provisioning (OP) region is allocated for frequent garbage collection, wear leveling, and bad block management, an available storage capacity of the storage device may be decreased) (i.e., when performing garbage collection, wear leveling and bad block management, an available storage capacity is decreased, therefore storing the write data to the write area is delayed, adding memory block to the write area can improve performance)
Son does not teach wherein entering the power off state is determined based on whether storing the write data to the write area is delayed, and wherein the at least one target memory block is added to the write area when storing the write data to the write area is delayed.
However, Lee teaches wherein entering the power off state is determined based on whether storing the write data to the write area is delayed, and wherein the at least one target memory block is added to the write area when storing the write data to the write area is delayed.
(Lee [0052] the memory system 110 can move a large amount of data during wear leveling or garbage collection. [0052] a power issue may arise in the process of moving a large amount of data. A large amount of data may not be transferred to the second memory block 40_2 due to internal or external factors such as sudden power-off (SPO) in which the powersupply is interrupted)
Son and Lee are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Son and Lee to modify Son‘s power-off with Lee’s teaching of garbage collection and wear leveling as a threshold/delay condition. The motivation for doing so would be the need to prevent data loss when power-off under threshold/delay condition because (Lee [0052]) memory system can move a large amount of data during wear leveling or garbage collection.
Regarding Claim 10, Son and Lee teach
The storage device according to claim 9, wherein the controller is configured to determine that storing the write data to the write area is delayed when at least one of: garbage collection is being executed for the memory, a background operation other than the garbage collection is being executed for the memory, (Son [0004] As a large over provisioning (OP) region is allocated for frequent garbage collection, wear leveling, and bad block management, an available storage capacity of the storage device may be decreased) (i.e., when performing garbage collection, wear leveling and bad block management, an available storage capacity is decreased, therefore storing the write data to the write area is delayed)
or a size of free space in the write area is less than or equal to a threshold value.
Claim(s) 2, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son (US 20230236765), in view of Lee (US 20200042243), further in view of Reuter (US 20230281120).
Regarding Claim 2, Son and Lee teach
Son-Lee teaches when the threshold condition is satisfied (Lee [0052] the memory system 110 can move a large amount of data during wear leveling or garbage collection.)
Son-Lee does not teach wherein, when the threshold condition is satisfied, the controller is configured to set a throughput of an operation of storing the write data in the write area to be less than or equal to a threshold throughput.
However, Reuter teaches wherein, when the threshold condition is satisfied, the controller is configured to set a throughput of an operation of storing the write data in the write area to be less than or equal to a threshold throughput. (Reuter [0012] providing throttle logic in the storage device to program a host interface of the storage device to throttle accepting writes …during intensive garbage collection) (i.e. throttle accepting writes is set a throughput of storing the write data in the write area to be less than or equal to a threshold throughput)
Son, Lee and Reuter are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Son, Lee and Reuter to modify Son-Lee‘s power-off under the condition of performing garbage collection and wear leveling as a threshold/delay with Reuter’s teaching of throttling accepting writes during intensive garbage collection. The motivation for doing so would be that (Reuter [0011]) if writes are not regulated, then garbage collection may not free up pages at a sufficiently fast rate to provide pages for the rate at which writes are received.
Regarding Claim 11, Son and Lee teach
Son-Lee teaches when storing the write data to the write area is delayed (Son [0004] As a large over provisioning (OP) region is allocated for frequent garbage collection, wear leveling, and bad block management, an available storage capacity of the storage device may be decreased) (i.e., when performing garbage collection, wear leveling and bad block management, an available storage capacity is decreased, therefore storing the write data to the write area is delayed, adding memory block to the write area can improve performance).
Son-Lee does not teach wherein, when storing the write data to the write area is delayed, the controller is configured to set a throughput of an operation of storing the write data to the write area to be less than or equal to a threshold throughput.
However, Reuter teaches wherein, when storing the write data to the write area is delayed, the controller is configured to set a throughput of an operation of storing the write data to the write area to be less than or equal to a threshold throughput.
(Reuter [0012] providing throttle logic in the storage device to program a host interface of the storage device to throttle accepting writes …during intensive garbage collection) (i.e. throttle accepting writes is set a throughput of storing the write data in the write area to be less than or equal to a threshold throughput)
Son, Lee and Reuter are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Son, Lee and Reuter to modify Son-Lee‘s power-off under the condition of performing garbage collection and wear leveling as a threshold/delay with Reuter’s teaching of throttling accepting writes during intensive garbage collection. The motivation for doing so would be that (Reuter [0011]) if writes are not regulated, then garbage collection may not free up pages at a sufficiently fast rate to provide pages for the rate at which writes are received.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Kowles (US 20200201761) teaches power loss protection in memory sub-systems.
Conclusion
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/WEI MA/Examiner, Art Unit 2135
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