Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is a response to an application filed on 07/15/2025 in which claims 1-20 are pending and ready for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 4-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP2012064677A (hereinafter JP677) in view of JP2004014547A (hereinafter JP547) further in view of JP2006245182A (hereinafter JP182).
As to claim 1, JP677 discloses a semiconductor unit (Fig 1, 1) comprising:
a semiconductor device (Fig 1, 20) including:
a transistor chip (Fig 1, IGPT element 2a) having a rectangular shape, the transistor chip including:
a first electrode pad (Fig 1, collector electrode of 2a) and a control pad (Fig 6, gate pad of symbol G) formed on a front surface thereof; and
a second electrode pad (Fig 1, emitter electrode of 2a) formed on a rear surface thereof (see parag [0028-29]), the transistor chip configured to perform ON/OFF operation between the first electrode pad and the second electrode pad in response to a voltage applied to the control pad (see parags [0027-0028]), the semiconductor device further including:
a first terminal (Fig 1, 4p) electrically connected to the first electrode pad; a second terminal (Fig 1, 4u) electrically connected to the second electrode pad; and
a control terminal (Fig 1, gate terminal 5) electrically connected to the control pad;
a controller (Fig 5, 7, control circuit board) electrically connected to the control terminal and configured to control the transistor chip.
JP677 does not disclose: a resistor provided between the control terminal and the controller. However, JP547 discloses a resistor (Fig 1, RG) provided between the control terminal and the controller. It would have been obvious to one skilled in the art before the effective filing date of the invention to modify the control terminal of JP677 to include the resistor as taught by JP547 in order to limit the current going through the control terminal.
The combination of JP677 and JP547 does not disclose: wherein the first electrode pad is separated into two regions at a center of the front surface of the transistor chip, and
a temperature-sensing diode is disposed between the two regions. However, JP182 discloses the first electrode pad is separated into two regions at a center of the front surface of the transistor chip, and a temperature-sensing diode is disposed between the two regions (see Figs 1-5, parags [0013-0028], the second electrode pad is separated into two regions (emitter electrode 1PE1A and emitter electrode 1PE1B) at the center of the surface of the transistor chip, and the temperature sensor 12 is arranged between the two regions). It would have been obvious to one skilled in the art before the effective filing date of the invention to modify the electrode pad of JP677 and JP547 to be separated into two regions at a center of the front surface of the transistor chip, and a temperature-sensing diode is disposed between the two regions as taught by JP182 in order to provide the semiconductor device of which the diameter of an aluminum wire is not determined by chip size of a power semiconductor element.
As to claim 2, the combination of JP677, JP547 and JP182 discloses the semiconductor unit according to claim 1, wherein the controller is configured to turn off the transistor chip when a current flowing through the transistor chip becomes greater than or equal to a threshold value (JP677, parag [0024], discloses “takes out and measures a part of the emitter current using the sense emitter 5d”, and it is well-known in the semiconductor field, when the measured current flowing through the chip is an overcurrent equal to or higher than the threshold value, the controller will turn off the transistor chip).
As to claim 4, the combination of JP677, JP547 and JP182 discloses the semiconductor unit according to claim 1, wherein the transistor chip is an IGBT (JP677, Fig 1, IGBT element 2a), the first electrode pad is a collector electrode, and the second electrode pad is an emitter electrode.
As to claim 5, the combination of JP677, JP547 and JP182 does not disclose the semiconductor unit according to claim 1, wherein the transistor chip is a MOSFET formed of a silicon carbide (SiC) semiconductor substrate,the first electrode pad is a source electrode, and the second electrode pad is a drain electrode. However, it would have been obvious to one skilled in the art before the effective filing date of the invention to modify the transistor of JP677, JP547 and JP182 to become the MOSFET in order to obtain fast switching, high efficiency and low power consumption, and this involves only routine skills in the art.
As to claim 6, the combination of JP677, JP547 and JP182 discloses the semiconductor unit according to claim 1, wherein the front surface of the transistor chip includes: a gate electrode pad (JP677, gate pad of symbol “G” in Fig 6 connected to the gate terminal 5c), an anode electrode pad (JP677, anode pad of symbol “A” in Fig 6 connected to anode terminal 5a) electrically connected to an anode of the temperature-sensing diode (Fig 1, 2c), and a cathode electrode pad (cathode pad of symbol “K” in Fig 6 connected to cathode terminal 5b) electrically connected to a cathode of the temperature-sensing diode (Fig 1, 2c), and the gate electrode pad, the anode electrode pad, and the cathode electrode pad are arranged along one side of the transistor chip (JP677, see Fig 6, G, A, K are arranged along one side of the surface of the transistor chip).
As to claim 7, the combination of JP677, JP547 and JP182 discloses the semiconductor unit according to claim 6, wherein the transistor chip has a cutaway portion formed such that the first electrode pad is recessed in a direction orthogonal to an arrangement direction of the two regions in a plan view of the transistor chip, and the gate electrode pad, the anode electrode pad, and the cathode electrode pad are disposed in the cutaway portion (JP182, see Figs 3-5, the second electrode pad 1PE1 is recessed in a direction orthogonal to the arrangement direction of the two regions (1PE1A, 1PE1B) in a plan view of the transistor chip).
As to claim 8, the combination of JP677, JP547 and JP182 discloses the semiconductor unit according to claim 1, wherein the controller (JP677, see Fig 5, 7) further includes a temperature detection circuit (a circuit that measures the forward current of the temperature sensing diode 2c) configured to detect a temperature of the transistor chip based on a signal from the temperature-sensing diode (JP677, Fig 1, 2c), and when the signal detected by the temperature detection circuit becomes greater than or equal to a threshold value, the controller supplies a current reduction signal to the control terminal of the transistor chip (JP677, see parag [0024]).
As to claim 9, the combination of JP677, JP547 and JP182 discloses the semiconductor unit according to claim 1, wherein the transistor chip is one of a plurality of transistor chips, the semiconductor unit comprising the plurality of transistor chips connected in parallel with each other (JP677, see Fig 1, 20a, 20b, 20c, 20d, 20e, 20f).
As to claim 10, the combination of JP677, JP547 and JP182 discloses the semiconductor unit according to claim 9, wherein each of the plurality of transistor chips includes the temperature-sensing diode (JP677, see Fig 1, 2c).
As to claim 11, the combination of JP677, JP547 and JP182 discloses the semiconductor unit according to claim 10, wherein the controller includes a plurality of temperature detection circuits, each of the temperature detection circuits receives a signal from the respective temperature-sensing diode of the plurality of transistor chips (Fig 1, 20a-20f), and when at least one of the signals corresponding to the detected temperatures detected by the plurality of temperature detection circuits becomes greater than or equal to a threshold value, the controller supplies a current reduction signal to each control terminal of the plurality of transistor chips (see parag [0025]).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP2012064677A (hereinafter JP677) in view of JP2004014547A (hereinafter JP547) further in view of JP2006245182A (hereinafter JP182) and further in view of Osada et al (hereinafter Osada) (US 2009/0073753 A1).
As to claim 3, the combination of JP677, JP547 and JP182 does not disclose the semiconductor unit according to claim 1, wherein the resistance value of the resistor is greater than or equal to 100. However, Osada discloses the resistance value of the resistor is greater than or equal to 100 (see parag [0094]). It would have been obvious to one skilled in the art before the effective filing date of the invention to modify the semiconductor device of JP677, JP547 and JP182 to have the resistance value of the resistor is greater than or equal to 100 as taught by Osada in order to effectively control the flow of electric current in the semiconductor device.
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP2012064677A (hereinafter JP677) in view of JP2004014547A (hereinafter JP547) further in view of JP2006245182A (hereinafter JP182) and further in view of JP2008206345 A (hereinafter JP345).
As to claim 12, the combination of JP677, JP547 and JP182 does not disclose a battery unit comprising: the semiconductor unit according to claim 1; and a battery electrically connected to the first terminal. However, JP345 discloses a battery unit (Fig 4, 52, battery) comprising: the semiconductor unit according to claim 1; and a battery electrically connected to the first terminal (Fig 1, battery 52 connected to the terminal of semiconductor module 2). It would have been obvious to one skilled in the art before the effective filing date of the invention to modify the semiconductor device of JP677, JP547 and JP182 to include the battery as taught by JP345 in order provide DC power for the device.
As to claim 13, the combination of JP677, JP547, JP182 and JP345 discloses a vehicle comprising: the battery unit (JP345, Fig 4, 52) according to claim 12; an inverter circuit (JP345, Fig 4, 11) electrically connected to the second terminal; and a motor (JP345, Fig 4, 51) driven by the inverter circuit.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP2012064677A (hereinafter JP677) as modified by JP2004014547A (hereinafter JP547) in view of JP2006245182A (hereinafter JP182) further in view of JP2008206345 A (hereinafter JP345) and further in view of JP2009044914A (hereinafter JP914).
As to claim 14, the combination of JP677, JP547, JP182 and JP345 does not disclose the vehicle according to claim 13, further comprising a mechanical relay connected in parallel with the semiconductor unit between the battery and the inverter circuit. However, JP914 discloses a mechanical relay (Fig 1, SMR1) connected in parallel with the semiconductor unit (Fig 1, 15) between the battery (Fig 1, 10) and the inverter circuit (Fig 1, 41). It would have been obvious to one skilled in the art before the effective filing date of the invention to modify the semiconductor device of JP677, JP547, JP182 and JP345 to include the relay as taught by JP914 in order to prevent damage to the motor controller due to inrush current when the power is turned on.
1. Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP2012064677A (hereinafter JP677) as modified by JP2004014547A (hereinafter JP547).
As to claim 16, JP677 discloses the semiconductor unit according to claim 15, a diode (Fig 1, 2b) connected in antiparallel to the transistor chip. JP677 does not disclose a current limiting resistor electrically connected to the control terminal. However, JP547 discloses a resistor (Fig 1, RG) provided between the control terminal and the controller. It would have been obvious to one skilled in the art before the effective filing date of the invention to modify the control terminal of JP677 to include the resistor as taught by JP547 in order to limit the current going through the control terminal.
2. Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP2012064677A (hereinafter JP677) in view of JP2006245182A (hereinafter JP182).
As to claim 17, JP677 does not disclose the semiconductor unit according to claim 15, wherein the first electrode pad is separated into two regions at a center of the front surface of the transistor chip, a temperature-sensing diode is disposed between the two regions, the transistor chip has a cutaway portion formed such that the first electrode pad is recessed in a direction orthogonal to an arrangement direction of the two regions in a plan view of the transistor chip, and the control pad, the third electrode pad, and the fourth electrode pad are disposed in the cutaway portion. However, JP182 discloses wherein the first electrode pad is separated into two regions at a center of the front surface of the transistor chip, a temperature-sensing diode is disposed between the two regions, the transistor chip has a cutaway portion formed such that the first electrode pad is recessed in a direction orthogonal to an arrangement direction of the two regions in a plan view of the transistor chip, and the control pad, the third electrode pad, and the fourth electrode pad are disposed in the cutaway portion (see Figs 3-5, the second electrode pad 1PE1 is recessed in a direction orthogonal to the arrangement direction of the two regions (1PE1A, 1PE1B) in a plan view of the transistor chip). It would have been obvious to one skilled in the art before the effective filing date of the invention to modify the device of JP677 to include the teachings as taught by JP182 in order to provide the semiconductor device of which the diameter of an aluminum wire is not determined by chip size of a power semiconductor element.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP2012064677A (hereinafter JP677).
As to claim 18, JP677 does not disclose the semiconductor unit according to claim 15, wherein the transistor chip is a MOSFET formed of a silicon carbide (SiC) semiconductor substrate, the first electrode pad is a source electrode, and the second electrode pad is a drain electrode. However, it would have been obvious to one skilled in the art before the effective filing date of the invention to modify the transistor of JP677 to become the MOSFET in order to obtain fast switching, high efficiency and low power consumption, and this involves only routine skills in the art.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP2012064677A (hereinafter JP677).
As to claim 15, JP677 discloses a semiconductor unit (Fig 1, 1) comprising:
a semiconductor device (Fig 1, 20) including:
a transistor chip (Fig 1, IGPT 2a) having a rectangular shape, the transistor chip including:
a first terminal (Fig 1, 4p); a second terminal (Fig 1, 4u); a control terminal (Fig 1, 5); a first electrode pad (Fig 1, collector electrode) formed on a front surface thereof and electrically connected to the first terminal; a control pad (Fig 6, gate pad of symbol G) formed on the front surface thereof and electrically connected to the control terminal; and a second electrode pad (Fig 6, emitter electrode of symbol E) formed on a rear surface thereof and electrically connected to the second terminal, the transistor chip configured to perform ON/OFF operation between the first electrode pad and the second electrode pad in response to a voltage applied to the control pad (see parags [0027-0028]); a controller (Fig 5, 7, control board) electrically connected to the control terminal and configured to control the ON/OFF operation between the first and second electrode pads, wherein the transistor chip (Fig 1, 2a) further includes a third electrode pad (Fig 6, anode pad of symbol A) and a fourth electrode pad (Fig 6, cathode pad of symbol K) connected to a temperature-sensing diode (Fig 1, 2c), and the control pad, the third electrode pad, and the fourth electrode pad are arranged along one side of the transistor chip (see Fig 6, A, G K are arranged in one side of the chip).
As to claim 19, JP677 discloses a semiconductor device (Fig 1, 1) comprising:
an insulation substrate (Fig 1, 6); a plurality of wiring portions (Fig 1, parag [0043], wire bonding) disposed on the insulation substrate; a transistor chip (Fig 1, IGBT element 2a) disposed on one of the plurality of wiring portions; and a sealing resin (Fig 3, 3) sealing the insulation substrate, the plurality of wiring portions, and the transistor chip; wherein the transistor chip includes: a first electrode pad (Fig 1, collector electrode of 2a) and a control pad (Fig 6, gate pad of symbol G) formed on a front surface thereof; and a second electrode pad (Fig 1, emitter electrode of 2a) formed on a rear surface thereof and connected to one of the plurality of wiring portions (Fig 1, wire bonding), the transistor chip being configured to perform ON/OFF operation between the first and second electrode pads in response to a voltage applied to the control pad(see parags [0027-0028]), the semiconductor device further comprising a first terminal (Fig 1, 4p) connected to the first electrode pad, a second terminal (Fig 1, 4u) connected to the second electrode pad, and a control terminal (Fig 1, gate terminal 5) connected to the control pad (Fig 6, gate pad of symbol G), the transistor chip further includes a third electrode pad (Fig 6, anode pad of symbol A) and a fourth electrode pad (Fig 6, cathode pad of symbol K) connected to a temperature-sensing diode (FIG 1, 2c), and the control pad, the third electrode pad, and the fourth electrode pad are arranged along one side of the transistor chip (Fig 6, A, G, K are arranged on one side of the chip).
As to claim 20, JP677 discloses the semiconductor device according to claim 19, wherein the control terminal (Fig 1, 5) is one of a plurality of control terminals connected respectively to the control pad (Fig 6, gate pad of symbol G), the third electrode pad (Fig 6, A), and the fourth electrode pad (Fig 6, K), end portions of the plurality of control terminals within the sealing resin (Fig 3, 3) are disposed to face one side of the transistor chip (Fig 1, 20) on which the control pad, the third electrode pad, and the fourth electrode pad are arranged (Fig 6, A, K, G are arranged on one side).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2017/0033035 A1; US 2020/0013703 A1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUC M PHAM whose telephone number is (571)272-5026. The examiner can normally be reached 10:00 am - 6:00 pm, Monday to Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kim, Taelor can be reached at 571-270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DUC M PHAM/
Examiner, Art Unit 2836 September 14, 2026
/TAELOR KIM/Supervisory Patent Examiner, Art Unit 2836
Prosecution Insights