CTNF 19/270,957 CTNF 87848 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 21-23 and 25-35 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-16 of U.S. Patent No. 12,400,618 . Although the claims at issue are not identical, they are not patentably distinct from each other because claims at issue are anticipated by claims of U.S. Patent No. 12,400,618 . The present application US Patent No. 12,400,618 Claim 21: A graphics processing unit comprising: a display subsystem comprising reserved memory; and circuitry configured to: detect a connection of a second display device to the display subsystem while a first display device remains active; store pixel data to the reserved memory; configure timings for the second display device while maintaining resources allocated to the first display device; output the pixel data from the reserved memory to the second display device during reallocation of resources within the display subsystem to enable framebuffer output to the second display device; and transition the second display device from displaying the pixel data to displaying framebuffer data following the reallocation of resources. Claim 1: An apparatus comprising: a graphics processor device including circuitry configured to: detect a connection of a second display device to a display subsystem of the graphics processor while a first display device of the graphics subsystem is active; write pre-determined pixel data to a reserved portion of memory associated with the display subsystem; configure timings for the second display device while resources allocated to the first display device remain available to the first display device; display the pre-determined pixel data from the reserved portion of the memory on the second display device during reallocation of the resources of the display subsystem to enable output framebuffer data to the second display device; and transition the second display device from the display of the pixel data in the reserved portion of the memory to the display of the framebuffer data after resources of the display subsystem are reallocated. Claim 22 Claims 2 and 3 Claim 23 Claim 4 Claim 25 Claim 5 Claim 26 Claim 6 Claim 27 Claim 7 Claim 28 Claim 8 Claim 29 Claim 9 Claim 30 Claim 10 Claim 31: A method comprising: detecting a connection of a second display device to a display subsystem while a first display device remains active; storing pixel data in reserved memory within the display subsystem; configuring timings for the second display device while maintaining resources allocated to the first display device; outputting the pixel data from the reserved memory to the second display device during reallocation of resources within the display subsystem to enable framebuffer output to the second display device; and transitioning the second display device from displaying the pixel data to displaying framebuffer data following the reallocation of resources. Claim 11: A method comprising: detecting a connection of a second display device to a display subsystem of a graphics processor while a first display device of the graphics subsystem is active; writing pre-determined pixel data to a reserved portion of memory associated with the display subsystem; configuring timings for the second display device while resources allocated to the first display device remain available to the first display device; displaying the pre-determined pixel data from the reserved portion of the memory on the second display device during reallocation of the resources of the display subsystem to enable output framebuffer data to the second display device; and transitioning the second display device from the display of the pixel data in the reserved portion of the memory to the display of the framebuffer data after resources of the display subsystem are reallocated. Claim 32 Claims 12 and 13 Claim 33 Claim 14 Claim 34 Claim 15 Claim 35 Claim 16 08-36 AIA Claim s 24 and 36-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-3, 5, and 9 of U.S. Patent No. 12,400,618 in view of Mathuriya et al. (US Pub. 2024/0402908 A1) . The present application US Patent No. 12,400,618 Claim 36: A graphics processing system comprising: an active base die including a level 4 (LA) cache; a plurality of chiplets coupled with the active base die, the plurality of chiplets including a compute die comprising processing elements for graphics operations and a system die providing system-level functionality; and a display subsystem communicatively coupled to the active base die, the display subsystem comprising reserved memory and circuitry configured to detect a connection of a second display device while a first display device remains active, wherein the circuitry within the display subsystem is further configured to store pixel data in the reserved memory, configure timings for the second display device while maintaining resources allocated to the first display device, output the pixel data from the reserved memory to the second display device during reallocation of resources, and transition the second display device from displaying the pixel data to displaying framebuffer data following the reallocation of resources. Claim 1: An apparatus comprising: a graphics processor device including circuitry configured to: detect a connection of a second display device to a display subsystem of the graphics processor while a first display device of the graphics subsystem is active; write pre-determined pixel data to a reserved portion of memory associated with the display subsystem; configure timings for the second display device while resources allocated to the first display device remain available to the first display device; display the pre-determined pixel data from the reserved portion of the memory on the second display device during reallocation of the resources of the display subsystem to enable output framebuffer data to the second display device; and transition the second display device from the display of the pixel data in the reserved portion of the memory to the display of the framebuffer data after resources of the display subsystem are reallocated. Claim 37 Claims 2 and 3 Claim 39 Claim 9 Claim 40 Claim 5 Regarding claim 24, Claim 1 of the US Patent No. 12,400,618 does not recite an active base die including a level 4 (L4) cache and a plurality of chiplets coupled with the active base die, the plurality of chiplets including a compute die comprising processing elements for graphics operations . Mathuriya teaches an active base die including a level 4 (L4) cache (Fig.1, Mathuriya discloses a graphic processing system 100. In particular, Fig.35, the graphic processing system comprises a substrate 3402 on which coherent cache or buffer (e.g., 2301-1 and 2301-2) is disposed. Para. [0153 and 0203], coherent cache is L4 cache) and a plurality of chiplets coupled with the active base die, the plurality of chiplets including a compute die comprising processing elements for graphics operations (Fig.35, para. [0084], compute dies 2002-1/2002-2). It would have been obvious to one of ordinary skill in the art to modify the system recited in claim 1 of the US Patent No. 12,400,618 to include the graphic processing system as taught by Mathuriya. The motivation would have been in order to improve performance of the system (Mathuriya, para. [0062 and 0066]). Regarding claim 36; claim 1 of the US Patent No. 12,400,618 does not recite a graphic processing system comprising an active base die including a level 4 (LA) cache; a plurality of chiplets coupled with the active base die, the plurality of chiplets including a compute die comprising processing elements for graphics operations and a system die providing system-level functionality; and a display subsystem communicatively coupled to the active base die . Mathuriya teaches a graphic processing system comprising an active base die including a level 4 (LA) cache (Fig.1, Mathuriya discloses a graphic processing system 100. In particular, Fig.35, the graphic processing system comprises a substrate 3402 on which coherent cache or buffer (e.g., 2301-1 and 2301-2) is disposed. Para. [0153 and 0203], coherent cache is L4 cache) ; a plurality of chiplets coupled with the active base die (Fig.35, chiplets 2002-1 and 2002-2 are coupled with the substrate 3402 vis the coherent cache) , the plurality of chiplets including a compute die (Fig.35, compute die 2002-1/2002-2) comprising processing elements for graphics operations (para. [0084]) and a system die (memory I/O die 2007, Fig.35) providing system-level functionality (para. [0181], the memory I/O 2007-1 may include SERDES, Very Short Reach (VSR), compute express link (CXL), peripheral component interconnect express (PCIe), DDR, low power DDR (LPDDR), graphics DDR (GDDR), open coherent accelerator processor interface (openCAPI) compliant I/O, MIPI, Advance Interface Bus (AIB), Embedded multi-die interconnect bridge (EMIB), or any suitable interface.) ; and a display subsystem communicatively coupled to the active base die (Fig.46, para. [0238], a display subsystem 4609 is connected to the processor 4605). It would have been obvious to one of ordinary skill in the art to modify the system recited in claim 1 of the US Patent No. 12,400,618 to include the graphic processing system as taught by Mathuriya. The motivation would have been in order to improve performance of the system (Mathuriya, para. [0062 and 0066]). Regarding claim 38; claim 1 of the US Patent No. 12,400,618 does not recite an interconnect fabric couples the active base die, the compute die, and the system die . Mathuriya teaches an interconnect fabric couples the active base die, the compute die, and the system die (para. [0094, 0136, and 0139], an interconnect fabric couples the components of the graphic processing system). It would have been obvious to one of ordinary skill in the art to modify the system recited in claim 1 of the US Patent No. 12,400,618 to include the interconnect fabric to connect components of the graphic processing system as taught by Mathuriya. The motivation would have been in order to reduce hardware cost . Claim Objections 07-29-01 AIA Claim s 37-40 are objected to because of the following informalities: Claims 37-40 contain multiple large spaces between adjacent words . Appropriate correction is required. Allowable Subject Matter Claims 21-40 would be allowed if overcoming the non-statutory double patenting. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Prior art fails to teach “store pixel data to the reserved memory; configure timings for the second display device while maintaining resources allocated to the first display device; output the pixel data from the reserved memory to the second display device during reallocation of resources within the display subsystem to enable framebuffer output to the second display device; and transition the second display device from displaying the pixel data to displaying framebuffer data following the reallocation of resources” as recited in claims 21 and 31 . Prior art fails to teach “the circuitry within the display subsystem is further configured to store pixel data in the reserved memory, configure timings for the second display device while maintaining resources allocated to the first display device, output the pixel data from the reserved memory to the second display device during reallocation of resources, and transition the second display device from displaying the pixel data to displaying framebuffer data following the reallocation of resources” as recited in claim 36 . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Qing et al. (US Pub. 2020/0356255 A1) discloses a method of switching between monitors and display screens. In particular, a host may be connected to a first display and a second display. The host comprises a controller, a memory, and at least one parameter module for receiving physiological parameters sensed by a sensor and processing the physiological parameters. The controller is configured for determining whether the second display is connected according to the indication signals output from the second interface circuit, detecting whether a display screen switching instruction is received once connection to the second display is detected, reading the corresponding display file from the memory according to configuration parameters of the second display if the display screen switching instruction is received, acquiring data of the physiological parameters from the parameter module according to the display file and generating frame data for representing pixel values of pixels on a display interface, and outputting the frame data to the second display to display physiological data. Inquiries Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN H TRUONG whose telephone number is (571)270-1630. The examiner can normally be reached M-F: 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NGUYEN H TRUONG/Examiner, Art Unit 2623 /CHANH D NGUYEN/Supervisory Patent Examiner, Art Unit 2623 Application/Control Number: 19/270,957 Page 2 Art Unit: 2623 Application/Control Number: 19/270,957 Page 3 Art Unit: 2623 Application/Control Number: 19/270,957 Page 4 Art Unit: 2623 Application/Control Number: 19/270,957 Page 5 Art Unit: 2623 Application/Control Number: 19/270,957 Page 6 Art Unit: 2623 Application/Control Number: 19/270,957 Page 7 Art Unit: 2623 Application/Control Number: 19/270,957 Page 8 Art Unit: 2623 Application/Control Number: 19/270,957 Page 9 Art Unit: 2623 Application/Control Number: 19/270,957 Page 10 Art Unit: 2623 Application/Control Number: 19/270,957 Page 11 Art Unit: 2623 Application/Control Number: 19/270,957 Page 12 Art Unit: 2623 Application/Control Number: 19/270,957 Page 13 Art Unit: 2623 Application/Control Number: 19/270,957 Page 14 Art Unit: 2623 Application/Control Number: 19/270,957 Page 15 Art Unit: 2623 Application/Control Number: 19/270,957 Page 16 Art Unit: 2623 Application/Control Number: 19/270,957 Page 17 Art Unit: 2623 Application/Control Number: 19/270,957 Page 18 Art Unit: 2623 Application/Control Number: 19/270,957 Page 19 Art Unit: 2623 Application/Control Number: 19/270,957 Page 20 Art Unit: 2623
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