DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
Claims 11,13,18, 20-24, and 25-28 are non-provisionally rejected on the ground of obviousness-type nonstatutory double patenting as being unpatentable over claims 21,24-25,28-29, and 32 of Application No 18349386 which is now US patent numbers 12399734. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the copending application disclose the function and structure of the claims of the instant application to those having ordinary skill in the art.
Regarding claim 11 of the instant application
8/8/2025 – 19271039 – claim 11
5/20/2022 – US Patent 12399734 – claim 21
An apparatus comprising:processing circuitry to copy context data from one or more processing resources to a shared memory; and initiate a preemption process.
An apparatus comprising:processing circuitry coupled to a first memory, the processing circuitry having processing resources such that the first memory is shared by the processing resources, the processing circuitry to upload context data associated with the processing resources from the first memory to a second memory and restore the first memory, wherein the first memory is independent of and separate from the second memory and coupled to a high-bandwidth communication fabric, wherein the context data is uploaded from the first memory into a local memory, wherein upon uploading the context data from the first memory into the local memory, a signal is generated to indicate that a context preemption process is complete, wherein when the context preemption process is initiated, execution of an existing context on the one or more processing resources is terminated,and wherein the processing circuitry is further to copy context state data from the existing context to the first memory in parallel with executing a context on one or more of the processing resources, wherein the first memory is restored.
Corresponding method claim 21 is rejected similarly as claim 11 above.
Corresponding product claim 25 is rejected similarly as claim 11 above.
Regarding claim 13 of the instant application
8/8/2025 – 19271039 – claim 13
5/20/2022 – US Patent 12399734 – claim 21
The apparatus of claim 11, wherein the processing circuitry is further to stop the execution of an existing context on a first set of processing resources save the context data from the existing context executing on the first processing resources to a first shared memory; generate a signal to indicate that a context preemption process is complete; upload the context data from the first shared memory to a local memory; and restore the first shared memory.
An apparatus comprising:processing circuitry coupled to a first memory, the processing circuitry having processing resources such that the first memory is shared by the processing resources, the processing circuitry to upload context data associated with the processing resources from the first memory to a second memory and restore the first memory, wherein the first memory is independent of and separate from the second memory and coupled to a high-bandwidth communication fabric, wherein the context data is uploaded from the first memory into a local memory, wherein upon uploading the context data from the first memory into the local memory, a signal is generated to indicate that a context preemption process is complete, wherein when the context preemption process is initiated, execution of an existing context on the one or more processing resources is terminated,and wherein the processing circuitry is further to copy context state data from the existing context to the first memory in parallel with executing a context on one or more of the processing resources, wherein the first memory is restored.
Corresponding method claim 22 is rejected similarly as claim 13 above.
Corresponding product claim 26 is rejected similarly as claim 13 above.
Regarding claim 18 of the instant application
8/8/2025 – 19271039 – claim 18
5/20/2022 – US Patent 12399734 – claim 21
The apparatus of claim 13 wherein the first set of processing resources is coupled to the first shared memory via a high-bandwidth communication fabric.
An apparatus comprising:processing circuitry coupled to a first memory, the processing circuitry having processing resources such that the first memory is shared by the processing resources, the processing circuitry to upload context data associated with the processing resources from the first memory to a second memory and restore the first memory, wherein the first memory is independent of and separate from the second memory and coupled to a high-bandwidth communication fabric, wherein the context data is uploaded from the first memory into a local memory, wherein upon uploading the context data from the first memory into the local memory, a signal is generated to indicate that a context preemption process is complete, wherein when the context preemption process is initiated, execution of an existing context on the one or more processing resources is terminated,and wherein the processing circuitry is further to copy context state data from the existing context to the first memory in parallel with executing a context on one or more of the processing resources, wherein the first memory is restored.
Corresponding method claim 23 is rejected similarly as claim 18 above
Corresponding product claim 27 is rejected similarly as claim 18 above
Regarding claim 20 of the instant application
8/8/2025 – 19271039 – claim 20
5/20/2022 – US Patent 12399734 – claim 24
The apparatus of claim 11, wherein the processing circuitry is coupled to a memory, the processing circuitry comprises one or more of graphics processing circuitry or application processing circuitry
The apparatus of claim 21, wherein the processing circuitry comprises one or more of graphics processing circuity or application processing circuitry
Corresponding method claim 24 is rejected similarly as claim 20 above.
Corresponding product claim 28 is rejected similarly as claim 20 above.
This application is also similarly rejected based on the other connected/parent cases which include Applications numbers: 18349386(As mapped above), 17561427, 16869223, and 1547702. An Electronic Terminal Disclaimer (TD) can help overcome the double patenting rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11,20,21,24,25, and 28 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 20120324473 A1; McKenney; Paul E. (hereinafter McKenney).
Regarding claim 11, McKenney teaches An apparatus comprising:processing circuitry to copy context data from one or more processing resources to a shared memory; (McKenney [0002] The present disclosure relates to computer systems and methods in which data resources are shared ...mechanism known as "read-copy update" in a computing environment wherein the data consumers are subject to being preempted while referencing shared data.[0007] FIGS. 1A-1D … updaters that delete, insert or modify data elements …allocating new memory for B', copying the contents of B to B', modifying B' as needed, updating the pointer from A to B so that it points to B', and releasing the lock. In current versions of the Linux.RTM. kernel, pointer updates performed by updaters can be implemented using the rcu_assign_pointer( ) primitive... [0032] FIG. 8 is a block diagram showing an example RCU preempt control block [0059] updates, the processors 4 of FIGS. 4 and 5 are programmed from instructions stored in the memory 8 (or elsewhere) to implement a read-copy update (RCU) subsystem 20 as part of their processor functions. FIG. 4 illustrates a single RCU subsystem executing on the lone processor 4. In FIG. 5, reference numbers 20.sub.1, 20.sub.2 . . . 20.sub.n represent individual RCU instances that may periodically execute on the several processors 4.sub.1, 4.sub.2 . . . 4.sub.n. Any given processor 4 in FIGS. 4 and 5 may also periodically execute a read operation (reader) 21. Each reader 21 runs from program instructions stored in the memory 8 (or elsewhere) in order to periodically perform read operations on the set of shared data 16 stored in the shared memory 8 (or elsewhere). FIG. 4 illustrates a single reader 21 executing on the lone processor 4. In FIG. 5, reference numerals 21.sub.1, 21.sub.2 . . . 21.sub.n illustrate individual reader instances that may periodically execute on the several processors 4.sub.1, 4.sub.2 . . . 4.sub.n. Such read operations will typically be performed far more often than updates, this being one of the premises underlying the use of read-copy update. Moreover, it is possible for several of the readers 21 to maintain simultaneous references to one of the shared data elements 16 while an updater 18 updates the same data element. The updaters 18 and the readers 21 are further assumed to be preemptible and the systems 2 and 2A may, for example, support real-time operations [71-80] further elaborate on the matter [FIG.5 in conjunction FIG.6] shows An apparatus with processing circuitry to copy context data from one or more processing resources to a shared memory) and initiate a preemption process. (McKenney [0032] FIG. 8 is a block diagram showing an example RCU preempt control block that may be used to perform grace period processing in accordance with the present disclosure;[0050] FIGS. 25A-25D are block diagrams showing the modified multiprocessor RCU preempt control block of FIG. 24 and information that may be tracked thereby; [0059] updates the same data element. The updaters 18 and the readers 21 are further assumed to be preemptible and the systems 2 and 2A may, for example, support real-time operations.[0062] Turning now to FIG. 6, example components of the RCU subsystem 20 are shown. These components include several RCU subsystem data structures 30, namely, an RCU control block 32, an RCU preempt control block 34, and several RCU-specific fields 36 in each reader's task structure (e.g., a task_struct data structure in the Linux.RTM. kernel). The components of the RCU subsystem 20 also include several RCU subsystem support functions 40, namely, an RCU reader API (Application Programming Interface) 42, an RCU updater...[0071] the RCU preempt control block 34 may be coded in software using the following C programming language declaration:...[71-80] further elaborate on the matter [FIG.6 & 12] show system which can initiate a preemption process)
Corresponding method claim 21 is rejected similarly as claim 11 above.
Corresponding product claim 25 is rejected similarly as claim 11 above. Additional Limitations: computer readable medium capable of reading and executing instructions (McKenney [0058] Each CPU device embodied by any given processor 4 of FIGS. 4 and 5 is operable to execute program instruction logic under the control of a software program stored in the memory 8 (or elsewhere). The memory 8 may comprise any type of tangible storage medium capable of storing data in computer readable form..[0118] Example data storage media for storing such program instructions are shown by reference numerals 8 (memory) and 10 (cache) of the uniprocessor system 2 of FIG. 4 and the multiprocessor system 2A of FIG. 5. The systems 2 and 2A may further include one or more secondary (or tertiary) storage devices (not shown) that could store the program instructions between system reboots. A further example of media that may be used to store the program instructions is shown by reference numeral 300 in FIG. 27.[0117] program product in which programming logic is provided by one or more machine-useable storage media for use in controlling a data processing system to perform the required functions. Example embodiments of a data processing system and machine implemented method were previously described in connection with FIGS. 4-26B. With respect to a computer program product, digitally encoded program instructions may be stored on one or more computer-readable data storage media for use in controlling a computer or other digital machine or device to perform the required functions. [100-116] elaborate on the matter [FIG.4 & 6] shows computer readable medium capable of reading and executing instructions)
Regarding claim 20, McKenney teaches The apparatus of claim 11, wherein the processing circuitry is coupled to a memory, the processing circuitry comprises one or more of graphics processing circuitry or application processing circuitry (McKenney [0062] Turning now to FIG. 6, example components of the RCU subsystem 20 are shown. These components include several RCU subsystem data structures 30, namely, an RCU control block 32, an RCU preempt control block 34, and several RCU-specific fields 36 in each reader's task structure (e.g., a task_struct data structure in the Linux.RTM. kernel). The components of the RCU subsystem 20 also include several RCU subsystem support functions 40, namely, an RCU reader API (Application Programming Interface) 42, an RCU updater API 44, an RCU grace period invocation API 46 and a set of grace period detection and callback processing functions 48.[0118] Example data storage media for storing such program instructions are shown by reference numerals 8 (memory) and 10 (cache) of the uniprocessor system 2 of FIG. 4 and the multiprocessor system 2A of FIG. 5. The systems 2 and 2A may further include one or more secondary (or tertiary) storage devices (not shown) that could store the program instructions between system reboots. A further example of media that may be used to store the program instructions is shown by reference numeral 300 in FIG. 27. The media 300 are illustrated as being portable optical storage disks of the type that are conventionally used for commercial software sales, such as compact disk-read only memory (CD-ROM) disks, compact disk-read/write (CD-R/W) disks, and digital versatile disks (DVDs). Such media can store the program instructions either alone or in conjunction with an operating system or other software product that incorporates the required functionality. The data storage media could also be provided by portable magnetic storage media (such as floppy disks, flash memory sticks, etc.), or magnetic storage media combined with drive systems (e.g. disk drives). As is the case with the memory 8 and the cache 10 of FIGS. 4 and 5, the storage media may be incorporated in data processing platforms that have integrated random access memory (RAM), read-only memory (ROM) or other semiconductor or solid state memory. More broadly, the storage media could comprise any electronic, magnetic, optical, infrared, semiconductor system or apparatus or device, or any other tangible entity representing a machine, manufacture or composition of matter that can contain, store, communicate, or transport the program instructions for use by or in connection with an instruction execution system, apparatus or device, such as a computer. [100-116] elaborate on the matter [FIG.4 & 6] show wherein the processing circuitry is coupled to a memory, the processing circuitry comprises one or more of graphics processing circuitry or application processing circuitry)
Corresponding method claim 24 is rejected similarly as claim 20 above.
Corresponding product claim 28 is rejected similarly as claim 20 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 13,18,22,23,26, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over US 20120324473 A1; McKenney; Paul E. (hereinafter McKenney) in view of US 20060190942 A1; Inoue; Keisuke et al. (hereinafter Inoue)
Regarding claim 13, McKenney teaches The apparatus of claim 11, wherein the processing circuitry is further to stop the execution of an existing context on a first set of processing resources save the context data from the existing context executing on the first processing resources to a first shared memory; (McKenney [0055] According to the example embodiments, the blocked-task data structure utilizes a single doubly linked list of tasks to optimally track blocked readers and their relationships to asynchronous grace periods, expedited grace periods, and priority boosting. Intelligent list insertion and pointers are used to segregate the blocked task list [0071] In an example embodiment, the RCU preempt control block 34 may be coded in software using the following C programming language declaration ... TABLE-US-00003 struct rcu_preempt_ctrlblk { struct rcu_ctrlblk /* curtail: ->next ptr of last CB for GP. */ rcb; struct rcu_head **nexttail; /* Tasks blocked in a preemptible RCU */ /* read-side critical section while a */ /* preemptible-RCU grace period is in */ /* progress must wait for a later grace */ /* period. This pointer points to the */ /* ->next pointer of the last callback that */ /* must wait for a later grace period, or */ /* to &->rcb.rcucblist if there is no */ /* such task. */ struct list_head blkd_tasks; /* Tasks blocked in RCU read-side critical */ /* section. Tasks are placed at the head */ /* of this list and age towards the tail. */ struct list_head *gp_tasks; /* Pointer to the first task blocking the */ /* current grace period, or NULL if there */ /* is no such task. */ struct list_head *exp_tasks; /* Pointer to first task blocking the */ /* current expedited grace period, or NULL */ /* if there is no such task. If there */ /* is no current expedited grace period, */ /* then there cannot be any such task. */ u8 gpnum; /* Current grace period. */ u8 gpcpu; /* Last grace period blocked by the CPU. */ u8 completed; /* Last grace period completed. */ }; ...[0084] In FIG. 10K, the blocked-tasks list comprises task T5... [101-109] further elaborate [FIG.10K & 12] shows wherein the processing circuitry is further to stop the execution of an existing context on a first set of processing resources save the context data from the existing context executing on the first processing resources to a first shared memory) generate a signal to indicate that a context preemption process is complete; (McKenney [0070] ended because one or more readers 21 may have been preempted within their RCU read-side critical sections. Instead, the processor quiescent state may be thought of as marking the beginning of the end of the current grace period. A multiprocessor alternative to the gpcpu field 34H is described in more detail below in connection with FIG. 24. The ninth field 34I, labeled "completed," indicates the number of the asynchronous grace period that has most recently completed. The condition where completed=gpnum signifies that there is no grace period in progress.[0094] end of the grace period by setting the completed field 34I equal to the gpnum field 34G in the RCU preempt control block 34. Block 88 advances the pending callbacks (if any) for callback processing, setting the donetail pointer 32B equal to the curtail pointer 32C in the RCU control block 32, and the setting the curtail pointer 32C equal to the nexttail pointer 34B in the RCU preempt control block 34. In block 90, a check is made whether there are any further blocked readers in the blocked-tasks list or any running readers. If not, this means that the next grace period (the one following the current grace period) can also be ended, and any callbacks associated with that grace period may also be advanced for callback processing. Block 92 performs the callback advancement by setting the donetail pointer 32B equal to the RCU nexttail pointer 34B. Following block 92, or if block 90 determines that the next grace period cannot yet be ended, block 94 checks whether there are any callbacks on the donelist that need to be processed. If there are, callback processing is initiated in block 96 (e.g., by performing actions that invoke the process callbacks component 48F) [FIG.12 &15] shows generate a signal to indicate that a context preemption process is complete) McKenney lacks explicitly and orderly teaching upload the context data from the first shared memory to a local memory; and restore the first shared memory. However Inoue teaches upload the context data from the first shared memory to a local memory; (Inoue [0073] In a preferred embodiment, the local memory 250 contains 256 kilobytes of storage, and the capacity of registers 252 is 128.times.128 bits. It is noted that the processor tasks 110 are not executed using the shared memory 214. Rather, the tasks 110 are copied into the local memory 250 of a given sub-processing unit 208 and executed locally.[0077] Turning again to the various processor tasks management features of the present invention, and with reference to FIG. 2, it is preferable that the sub-processing units 102 utilize a task table in order to determine which of the processor tasks 110 should be copied from the shared memory 106 and into one of the local memories of the SPUs 102 for execution. In this regard, reference is now made to FIG. 5, which is a conceptual illustration of a task table 280 that may be utilized in accordance with various aspects of the present invention. The task table 280 is preferably stored in the shared memory 106 (the details of how the task table 280 is initialized will be discussed later). [0084] In accordance with various aspects of the present invention, the sub-processing units 102 maintain and modify the task table 280 and the task queue 282 during execution of the software application. In this regard, reference is now made to FIGS. 8-10, which are flow diagrams illustrating a process flow that is suitable for achieving one or more desirable features of the present invention. At action 300, a particular sub-processing unit 102 is called to initiate the copying of a processor task 110 from the shared memory 106 to the local memory thereof. At action 302, the sub-processing unit 102 locks and copies the task queue 282 into its local memory.[0101] With reference to FIGS. 15-16, an alternative approach is illustrated in accordance with further aspects of the present invention. In this scenario, task B may be copied from the shared memory 106 to the local memory of the sub-processing unit 102 prior to copying task A from the local memory to the shared memory 106. In this regard, the sub-processing unit 102 may execute task A, while at the same time taking steps to identify and retrieve task B from the shared memory 106. This may entail copying the task table 280 and the task queue 282 from the shared memory 106 to the local memory of the sub-processing unit 102A and using same to identify the next READY task, i.e., task B. At the yield point, the kernel of the sub-processing unit 102A copies task A from the local memory to the shared memory [102-110] elaborate on the matter) and restore the first shared memory. (Inoue [0087] At action 320 (FIG. 10), the next processor task 110 (e.g., the processor task associated with task table entry T8) is copied by the sub-processing unit 102 from the shared memory 106 to the local memory thereof. At action 322, the sub-processing unit 120 preferably restores and/or updates registers thereof (e.g., with any data associated with the new processor task) for use in executing the new processor task 110. Finally, at action 324, the new processor task 110 is executed by the sub-processing unit 102.[0100] Reference is now made to FIGS. 13-14, which illustrate certain preemption features in accordance with certain aspects of the present invention. As discussed above, a processor task in the RUNNING state (e.g., task A) may be preempted or otherwise yield to another processor task in the READY state (e.g., task B). As illustrated in FIGS. 13 and 14, task A is being executed on the sub-processing unit 102 up to the point of the yield. At that point, the kernel of the SPU operates to copy task A back to the shared memory 106 (saving task A). Thereafter, task B is copied from the shared memory 106 to the local memory of the SPU (restoring task B). The SPU then executes task B. While this technique enjoys relatively high performance with reference to the amount of local memory utilization and high bandwidth, there is task execution latency from the point of the yield to the execution of task B that is not optimized.) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to take all prior methods and make the addition of Inoue in order to create a more capable migration and preemption process in a more efficient manner (Inoue [AB.] Methods and apparatus for migrating and distributing processor tasks on a plurality of multi-processing systems distributed over a network. The multi-processing system includes at least one broadband entity, each broadband entity including a plurality of processing units and synergistic processing units, as well as a shared memory. Tasks from one broadband entity are bundled, migrated and processed remotely on other broadband entities to efficiently use processing resources, and then returned to the migrating broadband entity for completion or continued processing.[0003] Real-time, multimedia applications are becoming increasingly important. These applications require extremely fast processing speeds, such as many thousands of megabits of data per second. While single processing units are capable of fast processing speeds, they cannot generally match the processing speeds of multi-processor architectures. Indeed, in multi-processor systems, a plurality of sub-processors can operate in parallel (or at least in concert) to achieve desired processing results.[0004] Moreover, multi-processor architectures are of valuable but limited scalability. Larger scales of efficiency can be achieved by grouping multiple multi-processor systems together over a network for distributed processing at speeds exceeding those of each multi-processor system running alone.[0101] With reference to FIGS. 15-16, an alternative approach is illustrated in accordance with further aspects of the present invention. In this scenario, task B may be copied from the shared memory 106 to the local memory of the sub-processing unit 102 prior to copying task A from the local memory to the shared memory 106. In this regard, the sub-processing unit 102 may execute task A, while at the same time taking steps to identify and retrieve task B from the shared memory 106. This may entail copying the task table 280 and the task queue 282 from the shared memory 106 to the local memory of the sub-processing unit 102A and using same to identify the next READY task, i.e., task B. At the yield point, the kernel of the sub-processing unit 102A copies task A from the local memory to the shared memory 106, which may entail modifying the task table 280 and the task queue 282 as described hereinabove. Thereafter, the sub-processing unit 102 may take up the execution of task B. This technique significantly reduces the latency between the yield and the execution of task B as compared with the technique illustrated in FIGS. 13-14.)
Corresponding method claim 22 is rejected similarly as claim 13 above.
Corresponding product claim 26 is rejected similarly as claim 13 above.
Regarding claim 18, McKenney and Inoue teach The apparatus of claim 13 wherein the first set of processing resources is coupled to the first shared memory via a high-bandwidth communication fabric. (Inoue [0067] The basic processing module is a processor element (PE). As shown in FIG. 3, the PE 200 comprises an I/O interface 202, a processing unit (PU) 204, a direct memory access controller (DMAC) 206, and a plurality of sub-processing units 208, namely, sub-processing unit 208A, sub-processing unit 208B, sub-processing unit 208C, and sub-processing unit 208D. A local (or internal) PE bus 212 transmits data and applications among the PU 204, the sub-processing units 208, the DMAC 206, and a memory interface 210. The local PE bus 212 can have, e.g., a conventional architecture or can be implemented as a packet switch network. Implementation as a packet switch network, while requiring more hardware, increases available bandwidth.[0069] The PE 200 is closely associated with a dynamic random access memory (DRAM) 214 through a high bandwidth memory connection 216. The DRAM 214 functions as the main (or shared) memory for the PE 200. Although the DRAM 214 preferably is a dynamic random access memory, the DRAM 214 could be implemented using other means, e.g., as a static random access memory (SRAM), a magnetic random access memory (MRAM), an optical memory, a holographic memory, etc. The DMAC 206 and the memory interface 210 facilitate the transfer of data between the DRAM 214 and the sub-processing units 208 and the PU 204 of the PE 200. It is noted that the DMAC 206 and/or the memory interface 210 may be integrally or separately disposed with respect to the sub-processing units 208 and the PU 204. Indeed, instead of a separate configuration as shown, the DMAC 206 function and/or the memory interface 210 function may be integral with one or more (preferably all) of the sub-processing units 208 and the PU 204.[0100] Reference is now made to FIGS. 13-14, which illustrate certain preemption features in accordance with certain aspects of the present invention. As discussed above, a processor task in the RUNNING state (e.g., task A) may be preempted or otherwise yield to another processor task in the READY state (e.g., task B). As illustrated in FIGS. 13 and 14, task A is being executed on the sub-processing unit 102 up to the point of the yield. At that point, the kernel of the SPU operates to copy task A back to the shared memory 106 (saving task A). Thereafter, task B is copied from the shared memory 106 to the local memory of the SPU (restoring task B). The SPU then executes task B. While this technique enjoys relatively high performance with reference to the amount of local memory utilization and high bandwidth, there is task execution latency from the point of the yield to the execution of task B that is not optimized. [FIG.33 & 41] shows corresponding visual)
Corresponding method claim 23 is rejected similarly as claim 18 above.
Corresponding product claim 27 is rejected similarly as claim 18 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARYAN D TOUGHIRY whose telephone number is (571)272-5212. The examiner can normally be reached Monday - Friday, 9 am - 5 pm.
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/ARYAN D TOUGHIRY/Examiner, Art Unit 2165
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