Prosecution Insights
Last updated: July 17, 2026
Application No. 19/271,185

COMMAND TABLE GENERATOR FOR A MEMORY DEVICE

Non-Final OA §102§103§112
Filed
Jul 16, 2025
Priority
Dec 16, 2022 — IN 202241072872 +1 more
Examiner
SIMONETTI, NICHOLAS J
Art Unit
Tech Center
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
359 granted / 467 resolved
+16.9% vs TC avg
Moderate +13% lift
Without
With
+13.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
13 currently pending
Career history
492
Total Applications
across all art units

Statute-Specific Performance

§101
1.6%
-38.4% vs TC avg
§103
84.9%
+44.9% vs TC avg
§102
10.8%
-29.2% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 467 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. In this case, the claims recite the following: Claim 1: “one or more components configured to:… obtain… receive… modify…,” wherein Claims 2-8, 11 and 13 recite further component “configured to...” functionality. Claim 18: “means for obtaining a command table… means for receiving an indication of a command… means for modifying the command table…” Claim 19: “means for generating display information...” Claim 20: “means for maintaining a mapping…” The corresponding structure for performing the above-recited functions can be found in at least Paragraphs [0027]-[0028], [0037]-[0038], [0092], [0104], [0114] and [0123]. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claim 4 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 4 recites, “wherein the one or more components, to modify the command table, are configured to: include the sequence in the array,” whereas Claim 1 from which it depends already recites, “modify the command table to cause the array of the units of data to include the sequence”. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3-5, 7-8, 10, 13-14, 16 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gaddam (US PGPUB 2021/0200472). With regard to Claim 1, Gaddam teaches a device, comprising: one or more components configured to ([0030] “The memory sub-system controller 115 can also include command overlap circuitry 106. The command overlap circuitry 106 can identify commands, received by the memory sub-system 110, that are addressed to a same LB of the memory device 130 and/or the memory device 140, among other possible memory devices.”): obtain a command table associated with a memory device ([0039] “The command overlap circuitry 206 includes a command table 222.”), wherein the command table indicates one or more commands via respective sequences of one or more units of data from an array of units of data ([0041] “The command table 222 can identify an order in which the commands 221 are received. The command table 222 can also store metadata of the commands 221. For example, the command table 222 can store a namespace, a starting LB, and/or an ending LB for each of the commands 221,” wherein the “starting LB [logical block]” and “ending LB” indicate the “respective sequences of one or more units of data.” [0037] “the command overlap circuitry 106 can utilize multiple data structures to store the commands received from the host system 120,” wherein the “data structure(s)” for implementing the “command table” comprise memory having an array or storage locations, i.e. the “array of units of data”.); receive an indication of a command to be added to the command table ([0040] “The command overlap circuitry 206 can receive commands 221 from a system host 120 of FIG. 1... The commands 221 can be added to the command table 222. The commands can also be provided to the overlap check circuitry 223.”), wherein the command indicates a sequence of one or more units of data ([003] “A command can comprise metadata. The command's metadata can include a namespace, a starting LB, and/or an ending LB, among other types of metadata.”); and modify the command table to cause the array of the units of data to include the sequence ([0061] “the newly received command 221 can be added to the command table 222.”). With regard to Claim 3, Gaddam teaches the device of claim 1, wherein the one or more components, to modify the command table, are configured to: identify the sequence in the array and store an indication identifying the sequence ([0041] “The command table 222 can identify an order in which the commands 221 are received. The command table 222 can also store metadata of the commands 221. For example, the command table 222 can store a namespace, a starting LB, and/or an ending LB for each of the commands 221.”). With regard to Claim 4, Gaddam teaches the device of claim 1, wherein the one or more components, to modify the command table, are configured to: include the sequence in the array ([0061] “the newly received command 221 can be added to the command table 222.”). With regard to Claim 5, Gaddam teaches the device of claim 1, wherein the one or more components are further configured to: store an indication of a location of the command in the array ([0041] “The command table 222 can identify an order in which the commands 221 are received. The command table 222 can also store metadata of the commands 221. For example, the command table 222 can store a namespace, a starting LB, and/or an ending LB for each of the commands 221.”). With regard to Claim 7, Gaddam teaches the device of claim 1, wherein the one or more components are further configured to: modify the command table to remove an indication of a second command ([0047] “the overlap check circuitry 223 can delete the marked commands from the command table 222 responsive to storing the marked command in the FIFO memory 224. In other instances, the overlap check circuitry 223 can delete the marked commands from the command table 222 responsive to the marked commands being executed (e.g., the marked commands being completed).”). With regard to Claim 8, Gaddam teaches the device of claim 1, wherein the one or more components are further configured to: provide, to a controller of the memory device, an indication of the command table ([0054] “The commands 226 retrieved by the marked entry scanning circuitry 225 from the FIFO memory 224 can be provided to the processor 117 (e.g., memory sub-system CPU) in FIG. 1. The marked entry scanning circuitry 225 can provide a single command 226 to the processor at a time. The overlap check circuitry 223 can refrain from storing additional commands from the command table 222 to the FIFO memory 224 until the processor executes the command provided by the marked entry scanning circuitry 225,” wherein the “processor 117” is the “controller”.). With regard to Claim 10, Gaddam teaches the device of claim 1, wherein the array of the units of data is a smallest array that includes the sequence and the respective sequences ([0040] “The command overlap circuitry 206 can receive commands 221 from a system host 120 of FIG. 1. In various examples, the commands 221 can be NVMe commands. The commands 221 can be added to the command table 222.” [0041] “The command table 222 can identify an order in which the commands 221 are received. The command table 222 can also store metadata of the commands 221. For example, the command table 222 can store a namespace, a starting LB, and/or an ending LB for each of the commands 221.” [0046] “The overlap check circuitry 223 can mark the commands that overlap with the identified command. The overlap check circuitry 223 can also mark the identified command. The commands that overlap can be marked in the command table 222. For example, each entry in the command table 222 can correspond to a command and can include fields for a namespace, a starting LB, and ending LB, and/or a marked field, among other possible fields,” wherein the size of the array is kept as small as possible by not storing duplicate overlapping commands.). With regard to Claim 13, Gaddam teaches the device of claim 1, wherein the one or more components are further configured to: receive input of a logical command that includes multiple commands defined for the memory device ([0010] “The host system can send access requests (e.g., write command, read command) to the memory sub-system, such as to store data on a memory device at the memory sub-system.” [0027] “the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130 and/or the memory devices 140.” [0041] “the command table 222 can store a namespace, a starting LB, and/or an ending LB for each of the commands 221,” wherein the command received from the host, i.e. the “logical command,” may be addressed to a range of logical block addresses (LBA) and as such effectively comprises the “multiple commands defined for the memory device”.). With regard to Claim 14, Gaddam teaches a method, comprising: obtaining, by a device, a command table associated with a memory device ([0039] “The command overlap circuitry 206 includes a command table 222.”), wherein the command table indicates one or more commands via respective sequences of one or more units of data from an array of units of data ([0041] “The command table 222 can identify an order in which the commands 221 are received. The command table 222 can also store metadata of the commands 221. For example, the command table 222 can store a namespace, a starting LB, and/or an ending LB for each of the commands 221,” wherein the “starting LB [logical block]” and “ending LB” indicate the “respective sequences of one or more units of data.” [0037] “the command overlap circuitry 106 can utilize multiple data structures to store the commands received from the host system 120,” wherein the “data structure(s)” for implementing the “command table” comprise memory having an array or storage locations, i.e. the “array of units of data”.); receiving, by the device, an indication of a modification associated with a command that indicates a sequence of one or more units of data; and modifying, by the device, the command table based on ([003] “A command can comprise metadata. The command's metadata can include a namespace, a starting LB, and/or an ending LB, among other types of metadata.” [0040] “The command overlap circuitry 206 can receive commands 221 from a system host 120 of FIG. 1... The commands 221 can be added to the command table 222. The commands can also be provided to the overlap check circuitry 223.”): adding an indication of the sequence to the array of units of data table ([0061] “the newly received command 221 can be added to the command table 222.” [0041] “The command table 222 can identify an order in which the commands 221 are received. The command table 222 can also store metadata of the commands 221. For example, the command table 222 can store a namespace, a starting LB, and/or an ending LB for each of the commands 221.”), or removing an indication of the sequence from the array of units of data ([0047] “the overlap check circuitry 223 can delete the marked commands from the command table 222 responsive to storing the marked command in the FIFO memory 224. In other instances, the overlap check circuitry 223 can delete the marked commands from the command table 222 responsive to the marked commands being executed (e.g., the marked commands being completed).”). With regard to Claim 16, Gaddam teaches the method of claim 14, further comprising: determining whether a start or an end of at least one sequence, of the respective sequences, includes at least one unit of data in common with the sequence ([0032] “Commands can be described as overlapping if namespaces match and one of the LB [logical block] from one command is between starting LB and ending LB of the other command. For example, a first command can overlap with a second command when the first command and the second command have a same staring LB and/or a same ending LB. In various examples, a first command and a second command can also overlap when at least a portion of the LB corresponding to each of the first command and the second command overlap. For example, the first command and the second command can overlap when a starting LB of the second command is greater than the starting LB of the first command but smaller than the ending LB of the first command. The first command and the second command can also overlap when the ending LB of the second command is greater than the starting LB of the first command but smaller than the ending LB of the first command. The first command and the second command can overlap when the starting LB of the second command is smaller than the starting LB of the first command and the ending LB of the second command is greater than the ending LB of the first command.”). With regard to Claim 18, this claim is equivalent in scope to Claim 1 rejected above, merely having a different independent claim type, and as such Claim 18 is rejected under the same grounds and for the same reasons as discussed above with regard to Claim 1. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Gaddam as applied to Claim 1 above, and further in view of Ohta et al. (US PGPUB 2001/0011323). With regard to claim 2, Gaddam teaches all the limitations of claim 1 as described above. Gaddam does not teach the rearranging of the array of data units as described in claim 2. Ohta teaches wherein the one or more components, to modify the command table, are configured to: rearrange the array of the units of data to a modified order ([0043] “The write data corresponding to the write command... is stored in the write buffer 5 by a write buffer storage unit 9.” [0053] “FIGS. 4A and 4B illustrate an example of processing overlapping write data with a disk device in accordance with embodiments of the present invention.” [0059] “if a new write command is input having write data corresponding to the disk medium start address B and disk medium end address C (where A<B<C<D), then, as shown in FIG. 4B, the data region 40 is overwritten with the new write command data. More particularly, the new write command data is overwritten in the data region 40-2 within data region 40, ranging from the disk medium address B to the disk medium address C,” see for example Figures 4A and 4B.). Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the device as disclosed by Gaddam with the rearranging of the array of data units as taught by Ohta for purposes of “providing a read/write processing device and method for a recording medium that efficiently reorders write commands and eliminates overlapping data” (Ohta [0011]). Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Gaddam as applied to Claim 1 above, and further in view of Bent et al. (US PGPUB 2020/0125493). With regard to claim 6, Gaddam teaches all the limitations of claim 1 as described above. Gaddam does not teach the modification of the array to indicate repetitive information as described in claim 6. Bent teaches wherein the one or more components are further configured to: modify the array of the units of data to indicate a quantity of repetitions associated with the sequence ([0047] “FIG. 5 illustrates an exemplary structure of a pattern index entry 500. As shown in FIG. 5, the exemplary pattern index entry 500 comprises a chunk identifier (id) used to locate the data dropping file corresponding to the pattern; a logical field indicating a logical offset pattern unit, discussed below; a length[ ] array of pattern units representing lengths; and a physical[ ] an array of pattern units representing physical offsets. One logical offset pattern may map to many length and physical offset patterns. In an exemplary notation, a logical offset pattern unit can be expressed as [i,(d[0], d[1], . . . ){circumflex over ( )}r], where i is the first element of the original sequence; d[ ] (delta) is a repeating part of an array containing the distances of any two consecutive elements in the original sequence; and r is a number of repetitions. For example, (5, 7, 10, 12, 15) can be represented as [5, (2, 3){circumflex over ( )}2].”). Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the device as disclosed by Gaddam with the modification of the array to indicate repetitive information as taught by Bent for purposes of “reducing the latency as well as the other overheads by using efficient pattern detection and compact pattern descriptions to reduce the amount of PLFS index information, resulting in a compression factor of several orders of magnitude for exemplary applications” (Bent [0040]). Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Gaddam as applied to Claim 1 above, and further in view of McVay (US PGPUB 2017/0116139). With regard to claim 9, Gaddam teaches all the limitations of claim 1 as described above. Gaddam does not teach the unit of data including double words as described in claim 9. McVay teaches wherein the one or more units of data include one or more double words (DWORDs). ([0015] “The host controller 102 may be a memory controller 102... the host controller 102 may be operating under the NVMe protocol, which may provide numerous output and input submission queues.” [0008] “the Non-Volatile Memory Express (NVMe) protocol defines a 64 byte Submission Queue Entry (SQE), which may also be referred to as an NVMe packet structure, for providing command, address, and data from a host to an SSD. Per the protocol... the remaining four DWords (12-15, specifically) may be user defined for providing data and/or memory address information.”). Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the device as disclosed by Gaddam with the unit of data including double words as taught by McVay in order to “provide... a high bandwidth interface between the host system and the SSD” (McVay [0009]). Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Gaddam as applied to Claim 14 above, and further in view of Ramarao (US Patent 8,832,034). With regard to claim 15, Gaddam teaches all the limitations of claim 14 as described above. Gaddam does not teach the determination regarding the composition of the sequence as described in claim 15. Ramarao teaches further comprising: determining whether the sequence is representable by arranging two or more existing sequences, of the respective sequences, to form the sequence (Col. 3 ll. 39-47: “to search the dictionary for a given segment of input data volume X (also referred to herein as an input string), the de-duplication engine 200 selects an offset-staggered set of search handles within the data segment as shown at 207 and compares each search handle in turn (i.e., iteratively compares the search handles) with the contents of the handle dictionary (shown at 209) until either a matching handle is detected or all the search-handles are determined to miss (i.e., have no match within) the handle dictionary,” see also Fig. 2 showing the steps comprising De-Duplication Engine 200.). Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the method as disclosed by Gaddam with the determination regarding the composition of the sequence as taught by Ramarao such that “improved data reduction may be achieved” (Ramarao Col. 3 ln. 12). Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Gaddam as applied to Claim 14 above, and further in view of Zhang et al. (US PGPUB 2014/0244599). With regard to claim 17, Gaddam teaches all the limitations of claim 14 as described above. Gaddam does not teach the removal of data from the array as described in claim 17. Zhang teaches further comprising: determining at least one unit of data, to remove from the array, that is not included in any other sequence associated with commands in the command table ([0061] “FIG. 5 is a flowchart diagram illustrating one embodiment of a method for removing a data object from the deduplication storage.” [0066] “For each data segment of the container, if the deduplication software 50 determines that the segment is no longer needed (e.g., no longer referenced by any data object) then the deduplication software 50 may delete the segment from the storage pool of the deduplication storage system, which may include reclaiming the storage space taken by that segment (block 487),” wherein the “storage pool” is equivalent to the claimed “array”.). Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the method as disclosed by Gaddam with the removal of data from the array as taught by Zhang in order to “reclaim or free the storage space that was allocated to them so that it becomes available to be re-allocated for other purposes” (Zhang [0063]). Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Gaddam as applied to Claim 18 above, and further in view of Esaka et al. (US PGPUB 2023/0070397). With regard to claim 20, Gaddam teaches all the limitations of claim 18 as described above. Gaddam does not teach the command mapping information as described in claim 20. Esaka teaches further comprising: means for maintaining a mapping between respective identifiers of the one or more commands and corresponding index values, associated with the array, of the one or more commands ([0144] “the write control module 123 adds, to the write management table 63, an entry that includes a command ID, an LBA, a data length, and a data pointer which are designated in the write command,” wherein the “data pointer” is the “index value”.). Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the method as disclosed by Gaddam with the command mapping information as taught by Esaka for purposes of “managing the operation of the memory system” (Esaka [0095]). Allowable Subject Matter Claims 11-12 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The above mentioned claims have been indicated as reciting allowable subject matter due to the inclusion of a novel method and system for managing a memory device command table. The prior art references teach various methods and systems for managing a memory device command table, but nowhere does any of the prior art disclose a method or system for managing a memory device command table which includes the specific set of steps disclosed in Applicant’s Claims 11 and 12, particularly with regard to the follow claim limitations: Claim 11: “wherein the one or more components are further configured to: generate a user interface that includes an input option for indicating commands, from a command database, to be configured for the memory device.” Claim 12: “wherein the command table is associated with a non-binary format and the device is associated with a user interface configured to enable input of commands using binary data.” Claim 19: “further comprising: means for generating display information by converting information associated with the command table from a first format to a second format associated with a user interface.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is as follows: Livne et al. (US PGPUB 2020/0326869) discloses a memory system including a memory controller configured to reduce the amount of duplicate data by performing half-match deduplication. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J SIMONETTI whose telephone number is (571)270-7702. The examiner can normally be reached Monday-Thursday 10AM-6PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached at (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NICHOLAS J SIMONETTI/Primary Examiner, Art Unit 2137 June 24, 2026
Read full office action

Prosecution Timeline

Jul 16, 2025
Application Filed
Jun 29, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
90%
With Interview (+13.1%)
3y 1m (~2y 1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 467 resolved cases by this examiner. Grant probability derived from career allowance rate.

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