Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) filed on 11/10/2025 has/have been considered by the Examiner and made of record in the application file.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12,386,702 in view of Porterfield (US 20120311381 A1).
As to claim 1, 12,386,702 teaches a memory sub-system comprising:
a memory device (see claim 1); and
one or more processing devices, operatively coupled with the memory device (see claim 1), the one or more processing devices to perform operations comprising:
detecting a failure exhibited by a set of memory cells of the memory device (see claim 1, detec);
determining whether a subset of memory cells of the set of memory cells satisfies a first threshold condition (see claim 1’s 2nd and 3rd determining steps, disclosing determining whether the recovery indicator corresponding to a subset of cells satisfies a threshold condition)
responsive to determining that the subset of memory cells satisfies the first threshold condition, selecting a first data recovery operation (claim 1); and
causing the first data recovery operation to be performed on the set of memory cells (claim 1).
12,386,702 does not explicitly teach the selection of the first data recovery operation is from a set of data recovery operations
However, Porterfield teaches operations (see paragraph 0072, disclosing counting the number of bit errors and if the number of bit errors detected is above a threshold initiating error recovery using RAID and that if it is below the threshold, the data is corrected by an error correction component (the examiner interprets these two recovery methods as corresponding to the set of data recovery operations)).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine the 12,386,702 with the methods of Porterfield because it provides data integrity and reduces manufacturing testing (see paragraphs 0013-0014).
As to claim 2, see claim 2 of 12,386,702.
As to claim 3, see claim 4 of 12,386,702.
As to claim 4, see claim 5 of 12,386,702.
As to claim 5, see claim 5 of 12,386,702.
As to claim 6, see claim 6 of 12,386,702.
As to claim 7, see claim 8 of 12,386,702.
As to claims 8-14, they are rejected on grounds corresponding to above rejected claims 1-7 because they are substantially equivalent.
As to claims 15, 16, 18, 19, and 20 they are rejected on grounds corresponding to above rejected claims 1, 2, 5, 6, and 7 because they are substantially equivalent.
As to claim 17, see claim 4 of 12,386,702.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Porterfield in view of Zhang (US 12038805 B1).
As to claim 1, Porterfield teaches a memory sub-system comprising:
a memory device (see fig. 1); and
one or more processing devices, operatively coupled with the memory device (see fig. 1), the one or more processing devices to perform operations comprising:
detecting a failure exhibited by a set of memory cells of the memory device (see paragraph 0072, disclosing detecting bit errors in read data);
determining whether a subset of memory cells of the set of memory cells satisfies a first threshold condition (see paragraph 0072, disclosing counting the number of bit errors and if the number of bit errors detected is above a threshold initiating error recovery using RAID; the examiner interprets a block can have multiple cells (see paragraph 0005) an the bits with errors can be associated with cells in the block (subset that has errors))
responsive to determining that the subset of memory cells satisfies the first threshold condition, selecting a first data recovery operation from a set of data recovery operations (see paragraph 0072, disclosing counting the number of bit errors and if the number of bit errors detected is above a threshold initiating error recovery using RAID and that if it is below the threshold, the data is corrected by an error correction component (the examiner interprets these two recovery methods as corresponding to the set of data recovery operations)); and
causing the first data recovery operation to be performed on the set of memory cells (see paragraph 0072, disclosing counting the number of bit errors and if the number of bit errors detected is above a threshold initiating error recovery using RAID).
Porterfield does not explicitly teach the determining is based on a read level voltage corresponding to a per-cell memory density of the memory device;
However, Porterfield teaches that the determination is done with a read of the memory cells and Zhang teaches that a read is done by using a read voltage level used as a threshold for reading memory cells (see col. 9, lines 3-44) and that cells can have different densities (see fig. 4 and corresponding text).
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine the Porterfield with the methods of Zhang because it allows for reading and determination and correction of errors in reading data (see col 9, liens 2-55).
As to claim 2, the reference(s) teach(es) claim 1 as detailed above. It/they further teach(es) the first data recovery operation comprises performing a redundant array of independent disks (RAID) recovery operation on the set of memory cells (see Porterfield paragraph 0072, disclosing counting the number of bit errors and if the number of bit errors detected is above a threshold initiating error recovery using RAID).
As to claim 3, the reference(s) teach(es) claim 1 as detailed above. It/they further teach(es) the threshold condition comprises a check failed bit (CFBit) count (see Porterfield paragraph 0072, disclosing counting the number of bit errors).
As to claim 4, the reference(s) teach(es) claim 1 as detailed above. It/they further teach(es) the threshold condition comprises a check failed byte (CFByte) count (see Porterfield paragraphs 0022and 0072, disclosing counting the number of bit errors when reading a block and that a block can be made of bytes; the examiner interprets that the count of bit errors for a block may correspond to a check failed byte count because this term is described in detail and may refer to a count that is merely associated with blocks made up of bytes).
As to claim 5, the reference(s) teach(es) claim 1 as detailed above. It/they further teach(es) the read level voltage corresponds to a threshold voltage of a highest programmed bit of a first page type of a plurality of page types of the memory device, wherein the plurality of page types corresponds to the per-cell memory density of the set of memory cells of the memory device (see Fig. 4 and associated text and col. 9, lines 1-44, disclosing slc, mlc, tlc, etc. types of cells and suggesting that a memory device can have multiple types and how a read voltage is used to read the different levels of bits in a particular type; also see figs. 2-6 and corresponding text disclosing the multiple page types MSB, LSB, etc. of each type of cell and that cells make up pages; the examiner interprets that the page types could refer to th different types of pages made up of different types of cells or the page types indicating the significance of the bits that are read).
As to claim 6, the reference(s) teach(es) claim 1 as detailed above. It/they further teach(es) responsive to determining that the subset of memory cells does not satisfy the first threshold condition, causing a read error handling (REH) recovery operation to be performed on the set of memory cells operations (see Porterfield paragraph 0072, disclosing counting the number of bit errors and if the number of bit errors detected is above a threshold initiating error recovery using RAID and that if it is below the threshold, the data is corrected by an error correction component).
As to claim 7, the reference(s) teach(es) claim 1 as detailed above. It/they do not explicitly teach that the threshold condition is defined during production of the memory device.
However, the examiner takes official notice that values can be set during production such as in a firmware by the manufacturer.
It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine the references with defining a threshold during production because it allows the manufacturer to choose the threshold value desired for the best performance and prevent it from being altered by others.
As to claims 8-14, they are rejected on grounds corresponding to above rejected claims 1-7 because they are substantially equivalent.
As to claims 15, 16, 18, 19, and 20 they are rejected on grounds corresponding to above rejected claims 1, 2, 5, 6, and 7because they are substantially equivalent.
As to claim 17, the reference(s) teach(es) claim 1 as detailed above. It/they further teach(es) the threshold condition comprises at least one of a check failed bit (CFBit) count or a check failed byte (CFByte) count (see Porterfield paragraph 0072, disclosing counting the number of bit errors).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON B BRYAN whose telephone number is (571)270-7091. The examiner can normally be reached Mon-Fri, 8-5 First Friday off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at 5712720631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON B BRYAN/Primary Examiner, Art Unit 2114
Prosecution Insights