Prosecution Insights
Last updated: October 04, 2026
Application No. 19/272,000

STORAGE MANAGEMENT METHOD AND STORAGE MANAGEMENT DEVICE

Non-Final OA §112
Filed
Jul 17, 2025
Priority
Sep 27, 2024 — CN 202411364282.3
Examiner
KHAN, MASUD K
Art Unit
2132
Tech Center
2100 — Computer Architecture & Software
Assignee
SigmaStar Technology Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
1y 1m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
398 granted / 455 resolved
+32.5% vs TC avg
Moderate +7% lift
Without
With
+6.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
21 currently pending
Career history
483
Total Applications
across all art units

Statute-Specific Performance

§101
2.4%
-37.6% vs TC avg
§103
63.5%
+23.5% vs TC avg
§102
16.7%
-23.3% vs TC avg
§112
11.1%
-28.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 455 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 8 recites the limitation "obtaining a write instruction which comprises a logical identification code; identifying a status flag recorded in the logical identification code in the write request;". There is insufficient antecedent basis for this limitation in the claim recites “obtaining a write instruction,” but then refers to the logical identification code “in the write request.” “Write request” lacks antecedent basis. This is likely correctable by replacing “write request” with “write instruction” throughout each claim, or by initially reciting “obtaining a write request.” Claim 17 is rejected for the same reason. Allowable Subject Matter The following is an examiner’s statement of reasons for allowance: Independent claim 1 recites the following allowable subject matter: "generating a first logical identification code mapped to the first logical sub-block to record, in the first logical identification code, a status flag of the first type corresponding to a first value, a logical sub-block number of the first logical sub-block and a logical block number of the first logical block; generating a second logical identification code mapped to the second logical block to record, in the second logical identification code, a status flag of the second type corresponding to a second value, a predetermined logical sub- block number and a logical block number of the second logical block." The claimed subject matter is allowable over Shatsky et al. (US 2023/0273877 A1), Roberts (US 2022/0342568 A1), Chandrashekar et al. (US 2017/0168936 A1), and Leppard (US 2011/0093664 A1), either alone or in any combination. In particular, none of the references teaches or suggests generating two different logical identification codes having the claimed distinct mappings and respective field contents. The claims require generating a first logical identification code mapped to a first logical sub-block, where that first code records: (1) a status flag of a first type corresponding to a first value, (2) the logical sub-block number of the particular first logical sub-block, and (3) the logical block number of the associated first logical block. The claims further require generating a second logical identification code mapped to a second logical block, where that second code records: (1) a status flag of a second type corresponding to a second value, (2) a predetermined logical sub-block number, and (3) the logical block number of the second logical block. The cited references may generally concern storage management, logical addressing, metadata, block information, or identification of storage units. However, the references do not disclose the claimed differentiated encoding scheme in which the format and meaning of a logical identification code depend on whether the code is mapped to a logical sub-block or to a logical block. More specifically, the references do not teach using a first status-flag type and first value to identify a code that includes an actual logical sub-block number, while using a different status-flag type and second value to identify a code associated with a logical block and containing a predetermined logical sub-block number in place of an actual sub-block number. Further, the references do not teach or suggest that the predetermined logical sub-block number in the second logical identification code serves as a deliberate indicator of the logical-block-level mapping, as distinguished from the first logical identification code that identifies a particular logical sub-block. Thus, the cited art fails to disclose or render obvious the claimed coordinated use of: (i) different status-flag types and values, (ii) different code-to-logical-unit mappings, and (iii) an actual versus predetermined logical sub-block number within the respective logical identification codes. No teaching, suggestion, or articulated reasoning in the cited references would have led one of ordinary skill in the art to modify the references to arrive at this particular dual-format logical identification-code arrangement. Accordingly, the claims are allowable over Shatsky et al., Roberts, Chandrashekar et al., and Leppard. Therefore, claim 1 and its dependent claims 2-7 and 9 are considered allowable. Independent claim 10 recites the same allowable subject matter. Under the same rationale of allowance of claim 1, claim 10 and its dependent claims 11-16 and 18 are considered allowable. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MASUD K KHAN/Primary Examiner, Art Unit 2132
Read full office action

Prosecution Timeline

Jul 17, 2025
Application Filed
Aug 04, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12743377
PARALLEL PROCESSING ARCHITECTURE WITH BLOCK MOVE SUPPORT
2y 1m to grant Granted Sep 22, 2026
Patent 12737301
SOFTWARE INTERFACE TO XPU ADDRESS TRANSLATION CACHE
4y 0m to grant Granted Sep 15, 2026
Patent 12730726
Disaster Recovery Using Virtual Storage Systems
2y 1m to grant Granted Sep 08, 2026
Patent 12730733
METHOD AND APPARATUS FOR PERFORMING PERIODIC TASK
2y 1m to grant Granted Sep 08, 2026
Patent 12724556
MEMORY SYSTEM FOR STORING META DATA AND OPERATING METHOD THEREOF
4y 11m to grant Granted Sep 01, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
94%
With Interview (+6.8%)
2y 4m (~1y 1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 455 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month