DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claims 1-18 & 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "a first calibration control signal to maintain a duty cycle of the first calibration control signal at a target duty cycle" in lines 3-4. It is unclear how the calibration control signal maintains a target duty cycle utilizing itself. The claim as written is unclear and requires clarification. For examination purposes, examiner has interpreted “to maintain a duty cycle of the first calibration control signal” to read “to maintain a duty cycle of a calibration clock signal”. Accordingly, “a calibration clock signal” as recited in lines 5-6 is interpreted to read “the calibration clock signal”.
Further, the limitation “a first feedback clock signal” recited in lines 19-20 is unclear. A “first feedback clock signal” was previously introduced in line 18. It is unclear if the limitation is introducing an additional feedback clock signal or referring to the aforementioned feedback clock signal. Further clarification is necessary.
By virtue of their dependency on claim 1, claims 2-18 are also rejected.
Claim 20 recites the limitation "a first calibration control signal to maintain the duty cycle of the first calibration control signal at a target duty cycle" in lines 4-5. It is unclear how the calibration control signal maintains a target duty cycle utilizing itself. The claim as written is unclear and requires clarification. Further, “the duty cycle” lacks antecedent basis. For examination purposes, examiner has interpreted “to maintain the duty cycle of the first calibration control signal” to read “to maintain a duty cycle of a calibration clock signal”.
Allowable Subject Matter
Claims 1-18 & 20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 19 is allowed.
Regarding claim 1, as best understood based on the 35 U.S.C. 112(b) rejection made above, Megawer et al. (US 12,231,132 B2), hereinafter Megawer discloses, in figure 9 & 15, a clock duty cycle calibration circuit comprising:
a duty cycle calibration cell (306) configured to perform a first duty cycle calibration processing on an input clock signal according to a first calibration control signal to maintain a duty cycle of a calibration clock signal at a target duty cycle (Col. 11, Lines 22-26, “if the clock duty cycle of the PLL 300 deviates from a desired duty cycle (e.g., a desired duty cycle of 25%, 50%, 75%, or any other desirable duty cycle target). To prevent or mitigate this reference transient, duty cycle calibration circuitry 306 may be implemented”…306 maintains desired duty cycle);
a signal frequency multiplier cell (302) configured to perform frequency multiplication processing on the calibration clock signal to acquire a corresponding frequency-multiplied clock signal (Col. 11, Lines 17-19, “frequency doubling circuitry 302 outputs a higher frequency reference signal 304, which has a frequency greater than that of the reference clock signal 104”), a first edge of the frequency-multiplied clock signal is aligned with the first edge of the calibration clock signal (see figure 15, leading edge of frequency multiplied clock signal, REF, is aligned with the leading edge of the calibration clock signal, REF CLK), and the frequency of the frequency-multiplied clock signal is a multiple of the frequency of the calibration clock signal (Col. 11, Line 17, “frequency doubling circuitry 302”);
a phase-locked loop cell (PLL loop 300) configured to:
perform a first phase-locked processing on the frequency-multiplied clock signal to acquire a first oscillating clock signal (Col. 8, Lines 29-30, “voltage-controller oscillator 118”…acquires a first oscillating clock signal based on the frequency multiplied clock signal REF); and
perform a first frequency division processing on the first oscillating clock signal to acquire a first feedback clock signal (divider 122 processes the output of the VCO 118 to acquire the feedback clock signal 106).
Fu (US 2019/0007036 A1) discloses, in figure 3, 4, & 5, a delay matching cell (303 comprising DL3, DL4) configured to perform delay matching processing on the calibration clock signal to acquire a delay-matched clock signal (Para [0051], “delay units DL3 and DL4 perform delay operations on the clock signal based on the input control signal, to gradually increase delay values till that the rising edge of the square wave of the clock signal at point C is aligned with the rising edge of the square wave of the clock signal at point A”), a first edge of the delay-matched clock signal is aligned with a first edge of the calibration clock signal (leading edge matched signals, see figure 5 step 1), and the delay-matched clock signal has the same duty cycle as the first calibration control signal (Para [0051], “duty cycle of 50% is used for description”).
However, none of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claim:
wherein, when the phase-locked loop cell is in a first locked state, a first edge of the first feedback clock signal is aligned with the first edge of the frequency-multiplied clock signal, and the first feedback clock signal has the same frequency as the frequency-multiplied clock signal; and
a calibration control cell configured to, when the phase-locked loop cell is in the first locked state, perform a first sampling processing on the delay-matched clock signal using the first feedback clock signal to acquire a first sampled signal; and generate the first calibration control signal according to the first sampled signal.
Regarding claim 19, Megawer discloses, in figure 9 & 15, a clock duty cycle calibration method comprising:
performing a first duty cycle calibration processing (306) on an input clock signal according to the first calibration control signal to maintain the duty cycle of the calibration clock signal at a target duty cycle (Col. 11, Lines 22-26, “if the clock duty cycle of the PLL 300 deviates from a desired duty cycle (e.g., a desired duty cycle of 25%, 50%, 75%, or any other desirable duty cycle target). To prevent or mitigate this reference transient, duty cycle calibration circuitry 306 may be implemented”…306 maintains desired duty cycle);
performing frequency multiplication processing (302) on the calibration clock signal to acquire a corresponding frequency-multiplied clock signal (Col. 11, Lines 17-19, “frequency doubling circuitry 302 outputs a higher frequency reference signal 304, which has a frequency greater than that of the reference clock signal 104”), a first edge of the frequency-multiplied clock signal is aligned with the first edge of the calibration clock signal (see figure 15, leading edge of frequency multiplied clock signal, REF, is aligned with the leading edge of the calibration clock signal, REF CLK), and the frequency of the frequency-multiplied clock signal is a multiple of the frequency of the calibration clock signal (Col. 11, Line 17, “frequency doubling circuitry 302”);
performing a first phase-locked processing (PLL loop 300) on the frequency-multiplied clock signal to acquire a first oscillating clock signal (Col. 8, Lines 29-30, “voltage-controller oscillator 118”…acquires a first oscillating clock signal based on the frequency multiplied clock signal REF); and
performing a first frequency division processing on the first oscillating clock signal to acquire a first feedback clock signal (divider 122 processes the output of the VCO 118 to acquire the feedback clock signal 106).
Fu discloses, in figure 3, 4, & 5, performing delay matching processing (303 comprising DL3, DL4) on a calibration clock signal to acquire a delay-matched clock signal (Para [0051], “delay units DL3 and DL4 perform delay operations on the clock signal based on the input control signal, to gradually increase delay values till that the rising edge of the square wave of the clock signal at point C is aligned with the rising edge of the square wave of the clock signal at point A”), a first edge of the delay-matched clock signal is aligned with a first edge of the calibration clock signal (leading edge matched signals, see figure 5 step 1), and the delay-matched clock signal has the same duty cycle as the first calibration control signal (Para [0051], “duty cycle of 50% is used for description”).
However, none of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claim:
wherein when a phase-locked loop cell is in a first locked state, a first edge of a first feedback clock signal is aligned with the first edge of the frequency-multiplied clock signal, and the first feedback clock signal has the same frequency as the frequency-multiplied clock signal; and
wherein when the phase-locked loop cell is in the first locked state, using the first feedback clock signal to perform sampling processing on the delay-matched clock signal to acquire a first sampled signal; and generating the first calibration control signal according to the first sampled signal.
Regarding claim 20, as best understood based on the 35 U.S.C. 112(b) rejection made above, Megawer discloses, in figure 9 & 15, a clock multiplier circuit comprising a clock duty cycle calibration circuit that includes:
a duty cycle calibration cell (306) configured to perform a first duty cycle calibration processing on an input clock signal according to a first calibration control signal to maintain a duty cycle of a calibration clock signal at a target duty cycle (Col. 11, Lines 22-26, “if the clock duty cycle of the PLL 300 deviates from a desired duty cycle (e.g., a desired duty cycle of 25%, 50%, 75%, or any other desirable duty cycle target). To prevent or mitigate this reference transient, duty cycle calibration circuitry 306 may be implemented”…306 maintains desired duty cycle);
a signal frequency multiplier cell (302) configured to perform frequency multiplication processing on the calibration clock signal to acquire a corresponding frequency-multiplied clock signal (Col. 11, Lines 17-19, “frequency doubling circuitry 302 outputs a higher frequency reference signal 304, which has a frequency greater than that of the reference clock signal 104”), a first edge of the frequency-multiplied clock signal is aligned with the first edge of the calibration clock signal (see figure 15, leading edge of frequency multiplied clock signal, REF, is aligned with the leading edge of the calibration clock signal, REF CLK), and the frequency of the frequency-multiplied clock signal is a multiple of the frequency of the calibration clock signal (Col. 11, Line 17, “frequency doubling circuitry 302”);
a phase-locked loop cell (PLL loop 300) configured to:
perform a first phase-locked processing on the frequency-multiplied clock signal to acquire a first oscillating clock signal (Col. 8, Lines 29-30, “voltage-controller oscillator 118”…acquires a first oscillating clock signal based on the frequency multiplied clock signal REF); and
perform a first frequency division processing on the first oscillating clock signal to acquire a first feedback clock signal (divider 122 processes the output of the VCO 118 to acquire the feedback clock signal 106).
Fu (US 2019/0007036 A1) discloses, in figure 3, 4, & 5, a delay matching cell (303 comprising DL3, DL4) configured to perform delay matching processing on the calibration clock signal to acquire a delay-matched clock signal (Para [0051], “delay units DL3 and DL4 perform delay operations on the clock signal based on the input control signal, to gradually increase delay values till that the rising edge of the square wave of the clock signal at point C is aligned with the rising edge of the square wave of the clock signal at point A”), a first edge of the delay-matched clock signal is aligned with a first edge of the calibration clock signal (leading edge matched signals, see figure 5 step 1), and the delay-matched clock signal has the same duty cycle as the first calibration control signal (Para [0051], “duty cycle of 50% is used for description”).
However, none of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claim:
wherein, when the phase-locked loop cell is in a first locked state, a first edge of the first feedback clock signal is aligned with the first edge of the frequency-multiplied clock signal, and the first feedback clock signal has the same frequency as the frequency- multiplied clock signal; and
a calibration control cell configured to, when the phase-locked loop cell is in the first locked state, perform a first sampling processing on the delay-matched clock signal using the first feedback clock signal to acquire a first sampled signal; and generate the first calibration control signal according to the first sampled signal.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yun et al. (US 2010/0109725 A1) [Figure 1. Discloses a delay locked loop (DLL) circuit includes a duty cycle correcting unit configured to correct a duty cycle of a reference clock signal in response to a duty cycle correction signal and generate a correction clock signal. A feedback loop of the DLL circuit performs a delay lock operation on the correction clock signal and generates an output clock signal. A first duty cycle detecting unit detects a duty cycle of the correction clock signal and generates a first detection signal and a second duty cycle detecting unit detects a duty cycle of the output clock signal and generates a second detection signal. Finally, a duty cycle control unit generates the duty cycle correction signal in response to the first detection signal and the second detection signal to perform the duty cycle correction.]
Terrovitis (US 8,988,121 B2) [Figure 2. Discloses a frequency synthesizing system includes a clock generator to generate a reference clock signal, a frequency doubler to generate a frequency-doubled clock signal in response to rising edges and falling edges of the reference clock signal, a frequency multiplier to generate a frequency-multiplied clock signal in response to either rising edges or falling edges of the frequency-doubled clock signal, and a fractional-N synthesizer coupled to the frequency multiplier to generate an output clock signal in response to the frequency-multiplied clock signal.]
Park et al. (US 9,985,618 B2) [Figure 4. Discloses a phase detector coupled to an output of a frequency multiplier. A digital loop filter is coupled to the phase detector, and a duty cycle correction circuit is coupled to the digital loop filter.]
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/TYLER J PERENY/ Examiner, Art Unit 2836
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