Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting (Statutory)
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claim 20 is/are rejected under 35 U.S.C. 101 as claiming the same invention as that of claim 15 of prior U.S. Patent No. 12,388,398. This is a statutory double patenting rejection.
Double Patenting (Non-Statutory)
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,388,398. Although the claims at issue are not identical, they are not patentably distinct from each other because the examined application claims are anticipated by, the reference claims.
Claim mapping with explanations as to how the claims align is provided below.
Claim 1 of 19/272,985 Claim 1 of US 12,388,398
A system, comprising:
A system, comprising:
a first transistor coupled to a current mirror;
a first transistor having a control terminal and first and second terminals, the first terminal coupled to a current mirror and the control terminal coupled to a first current source and a resistor;
a second transistor coupled to the first transistor and the current mirror;
a second transistor having a control terminal and first and second terminals, the first terminal coupled to the current mirror, the second terminal coupled to the second terminal of the first transistor, and the control terminal coupled to the resistor and a second current source;
a third transistor coupled to the second transistor and the current mirror (see “a second transistor” section in the third right column box) ; and
a third transistor having a control terminal and first and second terminals, the first terminal coupled to a voltage terminal, the second terminal coupled to the control terminal of the second transistor, and the control terminal coupled to the first terminal of the second transistor; and
a first current source (see “a first transistor” section in the second right column box) coupled to the first (see “a first transistor” section), second (see “a second transistor” “coupled to the resistor”), and third transistors (see “a third transistor” section where “the second terminal coupled to the control terminal of the second transistor”).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 11-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tran (US 2007/0205295).
Regarding claim 1, Tran discloses a system (FIG 2), comprising:
a first transistor (Q1) coupled to a current mirror (Q4, Q5, Q6 ¶[0021]);
a second transistor (Q2) coupled to the first transistor (Q1 via R1) and the current mirror (Q6);
a third transistor (Q3) coupled to the second transistor (Q2 via R1) and the current mirror (Q5) ; and
a first current source (24) coupled to the first (Q1 via ground node), second (Q2 via ground node), and third (Q3 via R1 and R2) transistors.
Regarding claim 2|1, Tran discloses the system further comprising: a resistor (R1 and R2) coupled between the first current source (24) and the second (Q2) and third (Q3) transistors.
Regarding claim 3|2|1, Tran discloses the system wherein: the second transistor includes a control terminal (base), a first terminal (collector), and a second terminal (emitter).
Regarding claim 4|3|2|1, Tran discloses the system further comprising a second current source (R2 can be viewed as a current source in a broad sense because it delivers a current) coupled between the control terminal (base) of the second transistor (Q2) and the second terminal (emitter) of the second transistor (Q2).
Regarding claim 11|1, Tran discloses the system wherein: the first current source (24) is configured to be coupled to a first voltage (VP via Q4).
Regarding claim 12|11|1, Tran discloses the system wherein: the third transistor (Q3) is configured to be coupled to the first voltage (VP).
Regarding claim 13|11|1, Tran discloses the system wherein: the current mirror is configured to be coupled to the first voltage (VP).
Regarding claim 14, Tran discloses a system (FIG 2), comprising: a first transistor (Q1) coupled to a first current source (24); a resistor (R2) including a first terminal (lower) and a second terminal (upper), the first terminal coupled to the first current source (24 via ground node); a second transistor (Q2) coupled to the second terminal (upper) of the resistor (R2); a third transistor (Q3) coupled to the second terminal of the resistor (R2 via R1); and a first current mirror (Q4, Q5 and Q6) coupled to the first, second, and third transistors (Q1, Q2 and Q3).
Allowable Subject Matter
Claim 19 is allowed.
Claims 5-10 and 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the cited references discloses nor suggests the claimed invention including “a fourth transistor configured as a capacitor” as recited in claims 5-10 and 15-18; “the first and second terminals coupled to one another” recited in claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Butler (US 6,815,941) discloses a bandgap reference circuit showing a current mirror, transistors and a differential amplifier.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joseph Chang whose telephone number is (571)272-1759. The examiner can normally be reached M-F 7:00- 17:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah M Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH CHANG/ Primary Examiner, Art Unit 2836
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