Prosecution Insights
Last updated: October 02, 2026
Application No. 19/273,044

DATA STORAGE AND DECOMPRESSION IN A MEMORY SYSTEM

Non-Final OA §102§103§112
Filed
Jul 17, 2025
Priority
Jul 29, 2024 — provisional 63/676,746
Examiner
PHAM, KAITLYN HUNG
Art Unit
2133
Tech Center
2100 — Computer Architecture & Software
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
100%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allowance Rate
4 granted / 4 resolved
+45.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
13 currently pending
Career history
29
Total Applications
across all art units

Statute-Specific Performance

§101
9.2%
-30.8% vs TC avg
§103
62.7%
+22.7% vs TC avg
§102
9.9%
-30.1% vs TC avg
§112
14.1%
-25.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 4 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Claims 1-22 are presented for examination. This office action is in response to submission of application on 17-JULY-2025. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The term “relatively lower” in claim 7 is a relative term which renders the claim indefinite. The term “relatively lower” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. That is, the claim does not provide a definition by which how much lower “relatively lower” entails, which renders the scope of the claim indefinite. Further, the limitation “the configuration to receive the compressed data is associated with a relatively lower amount of data, a reduced bandwidth, or both compared to receiving the decompressed data” presents an unclear set of possible interpretations about what the claim entails. For example, it is unclear whether the relatively lower amount of data or reduced bandwidth is for a comparison between the compressed data and decompressed data themselves, about the write configurations used to write them, or the act of receiving the data. This is exacerbated by the fact that the first part of the comparison is “the configuration to receive the compressed data”, whereas the second part of the comparison is “compared to receiving the decompressed data”. Taken at face value, this comparison would be between “the configuration” (noun) and “receiving the decompressed data” (verb), which renders the measurability of the comparison indefinite. Further, Claim 7 recites the limitation "the configuration" in line 1. There is insufficient antecedent basis for this limitation in the claim. Information Disclosure Statement Examiner notes that an Information Disclosure Statement has not been filed by the applicant as of the date of this office action. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 5, 7-16, 18, 20-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sato, U.S. Pub. No. 20210240381 (hereinafter “Sato”). Regarding claim 1: Sato teaches A memory system, comprising: One or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: ([0027-0031], Sato teaches a controller (processing circuitry) which is coupled to and operates with a non-volatile storage media (memory device). read compressed data from a first storage location of the one or more memory devices, the compressed data written to the first storage location in accordance with a first write configuration; decompress the compressed data to obtain decompressed data based on reading the compressed data from the first storage location; and write the decompressed data to a second storage location of the one or more memory devices in accordance with a second write configuration that is different from the first write configuration ([0122] and [0131], Sato teaches that a compressed version of software is stored in a compressed format into an SLC region (first storage location) with an SLC mode (first write configuration). Further, in [0126] and [0145], Sato teaches that the compressed data stored in the SLC region is read out of the SLC region, decompressed, and then transferred as uncompressed data into the TLC region (second storage location with a second write configuration). Regarding claim 2: Sato teaches all limitations of claim 1, from which claim 2 depends. Sato further teaches receive an indication to decompress the compressed data, wherein reading the compressed data from the first storage location and decompressing the compressed data are based on receiving the indication ([0127-0131], Sato teaches a variety of events, detected by sensors, to which the device responds to a detected event (receiving an indication) which causes the reading compressed data, decompression, and storing in the TLC mode to be performed.) Regarding claim 3: Sato teaches all limitations of claim 2, from which claim 3 depends. Sato further teaches receive the indication to decompress the compressed data in response to the memory system entering an operational mode ([0171], Sato teaches a variety of different events that can trigger the decompression of compressed data which includes a testing result of the memory and a result from operation of the memory, which can both be interpreted as the memory system becoming operational.) Regarding claim 5: Sato teaches all limitations of claim 1, from which claim 5 depends. Sato further teaches receive the compressed data to be stored at the memory system; and store the compressed data to the first storage location of the one or more memory devices in accordance with the first write configuration ([0121], Sato teaches that the software is loaded into the storage device, before it is stored in a compressed format in a first mode in the memory.) Regarding claim 7: Sato teaches all limitations of claim 5, from which claim 7 depends. Sato further teaches the configuration to receive the compressed data is associated with a relatively lower amount of data, a reduced bandwidth, or both compared to receiving the decompressed data (Although “compressed data” is interpreted under its plain definition to be a data that takes less amount of space (relatively lower amount of data), in [0123], Sato teaches that the uncompressed version of the software is an expanded (relatively larger) version of the software that is stored in a compressed version.) Regarding claim 8: Sato teaches all limitations of claim 1, from which claim 8 depends. Sato further teaches the first write configuration is associated with writing to memory cells in accordance with a first storage density and the second write configuration is associated with writing to memory cells in accordance with a second storage density that is greater than the first storage density ([0134], Sato teaches that the second storage mode is a higher memory density than a first mode, the mode describing how the memory is configured to store data.) Regarding claim 9: Sato teaches all limitations of claim 1, from which claim 9 depends. Sato further teaches the first storage location comprises a first set of one or more memory cells that are each configured to store a single bit of data and the second storage location comprises a second set of one or more memory cells that are each configured to store a plurality of bits of data ([0134], Sato teaches that data is stored in a first mode in an SLC region, where the first mode defined by storing one bit per cell, and that data is stored in a second mode in a TLC region, and the second mode is defined by having two or more bits per cell.) Regarding claim 10: Sato teaches all limitations of claim 1, from which claim 10 depends. Sato further teaches the second storage location is different from the first storage location ([0134], Sato teaches that the non-volatile storage media comprises a first region (SLC region) and a second region (TLC region). Being distinct different regions with different operating modes is interpreted to be different locations.) Regarding claim 11: Sato teaches all limitations of claim 1, from which claim 11 depends. Sato further teaches the first storage location is associated with one or more first memory devices of the one or more memory devices; and the second storage location is associated with one or more second memory devices of the one or more memory devices different from the one or more first memory devices ([0132], Sato teaches that the SLC region is formed using SLC devices, and the TLC region is formed using TLC devices, which are each on different chips (memory devices).) Regarding claim 12: Sato teaches all limitations of claim 1, from which claim 12 depends. Sato further teaches the first storage location and the second storage location are associated with a same memory device of the one or more memory devices ([0026], Sato teaches that the SLC region may simply be a portion of a TLC flash array operated in an SLC mode, meaning that the same array (memory device) is used for both the first and second storage locations.) Regarding claim 13: Sato teaches all limitations of claim 1, from which claim 13 depends. Sato further teaches the compressed data and the decompressed data are associated with a firmware image for the memory system ([0122-0123], Sato teaches that the compressed data, which gets expanded to a decompressed format, may be firmware.) Regarding claim 14: Sato teaches a method by a memory system, comprising: reading compressed data from a first storage location of the one or more memory devices of the memory system, the compressed data written to the first storage location in accordance with a first write configuration; decompressing the compressed data to obtain decompressed data based on reading the compressed data from the first storage location; and writing the decompressed data to a second storage location of the one or more memory devices in accordance with a second write configuration that is different from the first write configuration ([0122] and [0131], Sato teaches that a compressed version of software is stored in a compressed format into an SLC region (first storage location) with an SLC mode (first write configuration). Further, in [0126] and [0145], Sato teaches that the compressed data stored in the SLC region is read out of the SLC region, decompressed, and then transferred as uncompressed data into the TLC region (second storage location with a second write configuration)) Regarding claim 15: Sato teaches all limitations of claim 14, from which claim 15 depends. Sato further teaches receiving an indication to decompress the compressed data, wherein reading the compressed data from the first storage location and decompressing the compressed data are based on receiving the indication ([0127-0131], Sato teaches a variety of events, detected by sensors, to which the device responds to a detected event (receiving an indication) which causes the reading compressed data, decompression, and storing in the TLC mode to be performed.) Regarding claim 16: Sato teaches all limitations of claim 15, from which claim 16 depends. Sato further teaches receive the indication to decompress the compressed data in response to the memory system entering an operational mode ([0171], Sato teaches a variety of different events that can trigger the decompression of compressed data which includes a testing result of the memory and a result from operation of the memory, which can both be interpreted as the memory system becoming operational.) Regarding claim 18: Sato teaches all limitations of claim 14, from which claim 18 depends. Sato further teaches receiving the compressed data to be stored at the memory system; and storing the compressed data to the first storage location of the one or more memory devices in accordance with the first write configuration ([0121], Sato teaches that the software is loaded into the storage device, before it is stored in a compressed format in a first mode in the memory.) Regarding claim 20: Sato teaches all limitations of claim 14, from which claim 20 depends. Sato further teaches the first write configuration is associated with writing to memory cells in accordance with a first storage density and the second write configuration is associated with writing to memory cells in accordance with a second storage density that is greater than the first storage density ([0134], Sato teaches that the second storage mode is a higher memory density than a first mode, the mode describing how the memory is configured to store data.) Regarding claim 21: Sato teaches all limitations of claim 14, from which claim 21 depends. Sato further teaches the first storage location comprises a first set of one or more memory cells that are each configured to store a single bit of data and the second storage location comprises a second set of one or more memory cells that are each configured to store a plurality of bits of data ([0134], Sato teaches that data is stored in a first mode in an SLC region, where the first mode defined by storing one bit per cell, and that data is stored in a second mode in a TLC region, and the second mode is defined by having two or more bits per cell.) Regarding claim 22: Sato teaches A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of a memory system, cause the memory system to: ([0047], Sato teaches a non-transitory computer storage medium can be used to store instructions which, when executed by the controller, cause the controller to perform the method of Sato.) read compressed data from a first storage location of the one or more memory devices of the memory system, the compressed data written to the first storage location in accordance with a first write configuration; decompress the compressed data to obtain decompressed data based on reading the compressed data from the first storage location; and write the decompressed data to a second storage location of the one or more memory devices in accordance with a second write configuration that is different from the first write configuration ([0122] and [0131], Sato teaches that a compressed version of software is stored in a compressed format into an SLC region (first storage location) with an SLC mode (first write configuration). Further, in [0126] and [0145], Sato teaches that the compressed data stored in the SLC region is read out of the SLC region, decompressed, and then transferred as uncompressed data into the TLC region (second storage location with a second write configuration)) Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Sato, U.S. Pub. No. 20210240381 (hereinafter “Sato”) in view of Fishman et al., U.S. Pub. No. 20110041124 (hereinafter “Fishman”). Regarding claim 4: Sato teaches all limitations of claim 2, from which claim 4 depends. While Sato teaches broadly that a host processor which stores the compressed data and sends the indication to decompress the compressed data can comprise a pre-programming device and additionally comprise a reading and writing device after manufacturing (see Sato [0054]), and that the decompression may come when the memory system is activated for initial or setup operation after it is pre-programmed in a compressed form during manufacturing (see Sato [0118]), Sato does not appear to explicitly disclose that the compressed data is received from a first host system and prior to the memory system being coupled with a second host system; and the indication to decompress the compressed data is received from the second host system and after coupling the memory system with the second host system. However, Fishman teaches the compressed data is received from a first host system and prior to the memory system being coupled with a second host system; and the indication to decompress the compressed data is received from the second host system and after coupling the memory system with the second host system. ([0025-0028] and [0079-0085], Fishman teaches that a compressed data for an installation package may be stored on various distribution storage mediums by a manufacturer (first host system), then later, when a user plugs (couples) the distribution storage medium into a desktop computer (second host system), the user will then initiate the installation of the software system stored in the installation package.). Sato and Fishman are analogous art because they are from the same field of endeavor, firmware distribution and installation. Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Sato and Fishman to achieve the combined result of receiving compressed data from a first manufacturer host system prior to the memory system being coupled to a second host system, which after coupling the memory system with the second host system, the second host system sends the indication to decompress the compressed data. One of ordinary skill in the art would have been motivated to make this modification in order to facilitate the installation of programs from a manufacturer based on potential user selection as discussed in Fishman [0079-0085]. Regarding claim 17: Sato teaches all limitations of claim 15, from which claim 17 depends. While Sato teaches broadly that a host processor which stores the compressed data and sends the indication to decompress the compressed data can comprise a pre-programming device and additionally comprise a reading and writing device after manufacturing (see Sato [0054]), and that the decompression may come when the memory system is activated for initial or setup operation after it is pre-programmed in a compressed form during manufacturing (see Sato [0118]), Sato does not appear to explicitly disclose that the compressed data is received from a first host system and prior to the memory system being coupled with a second host system; and the indication to decompress the compressed data is received from the second host system and after coupling the memory system with the second host system. However, Fishman teaches the compressed data is received from a first host system and prior to the memory system being coupled with a second host system; and the indication to decompress the compressed data is received from the second host system and after coupling the memory system with the second host system. ([0025-0028] and [0079-0085], Fishman teaches that a compressed data for an installation package may be stored on various distribution storage mediums by a manufacturer (first host system), then later, when a user plugs (couples) the distribution storage medium into a desktop computer (second host system), the user will then initiate the installation of the software system stored in the installation package.). Sato and Fishman are analogous art because they are from the same field of endeavor, firmware distribution and installation. Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Sato and Fishman to achieve the combined result of receiving compressed data from a first manufacturer host system prior to the memory system being coupled to a second host system, which after coupling the memory system with the second host system, the second host system sends the indication to decompress the compressed data. One of ordinary skill in the art would have been motivated to make this modification in order to facilitate the installation of programs from a manufacturer based on potential user selection as discussed in Fishman [0079-0085]. Claims 6, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sato, U.S. Pub. No. 20210240381 (hereinafter “Sato”) in view of Raikin, U.S. Patent No. 10491241 (hereinafter “Raikin”). Regarding claim 6: Sato teaches all limitations of claim 5, from which claim 6 depends. While Sato briefly lists several existing example compression algorithms, Sato does not appear to explicitly disclose to receive the compressed data, the processing circuitry is configured to cause the memory system to receive an indication of one or more symbols each including a respective pattern of plurality of bits, and receive a bitmap defining one or more respective locations for each of the one or more symbols; and to decompress the compressed data, the processing circuitry is configured to cause the memory system to obtain a sequence of decompressed bits based on mapping each of the one or more symbols in accordance with the one or more respective locations. However, Raikin teaches to receive the compressed data, the processing circuitry is configured to cause the memory system to receive an indication of one or more symbols each including a respective pattern of plurality of bits, and receive a bitmap defining one or more respective locations for each of the one or more symbols; and (Col. 5 lines 22-51, Col. 4 line 50 to Col. 5 line 10, and Fig. 1, Raikin teaches a method of data compression which involves the creation of a non-anchor data which comprises the symbols making up a source data segment (non-compressed data) that are not the anchor value, ie. an indication of one or more symbols, and the creation of a bit-map which is a map of the location of the symbols, and each of the symbols are represented with 8 bits (respective pattern of plurality of bits). Further, both the generated non-anchor data and the bit-map are output to memory.). Raikin further teaches to decompress the compressed data, the processing circuitry is configured to cause the memory system to obtain a sequence of decompressed bits based on mapping each of the one or more symbols in accordance with the one or more respective locations. (Col. 5 line 52 to Col. 6 line 8, Raikin teaches that in order to decompress a compressed data, the system receives a stream of the compressed data, and based on the bitmap which denotes the respective locations of the non-anchor data, the system sequentially outputs bits to memory in a format such that the output is the decompressed symbols stored in the desired locations.) Sato and Raikin are analogous art because they are from the same field of endeavor, data compression. Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Sato and Raikin to achieve the combined result of the system which compresses data to store in one memory location, and decompresses the compressed data to store in another location, which uses a particular method of using indications of symbols and bit-maps representing the location of those symbols in order to store the final data in a compressed format. One of ordinary skill in the art would have been motivated to make this modification in order to implement a particular method of compression which reduces the size of the data that needs to be stored as discussed in Raikin Col. 5 lines 11-14. Regarding claim 19: Sato teaches all limitations of claim 18, from which claim 19 depends. While Sato briefly lists several existing example compression algorithms, Sato does not appear to explicitly disclose receiving the compressed data comprises receiving an indication of one or more symbols each including a respective pattern of plurality of bits, and receiving a bitmap defining one or more respective locations for each of the one or more symbols; and decompressing the compressed data comprises obtaining a sequence of decompressed bits based on mapping each of the one or more symbols in accordance with the one or more respective locations. However, Raikin teaches receiving the compressed data comprises receiving an indication of one or more symbols each including a respective pattern of plurality of bits, and receiving a bitmap defining one or more respective locations for each of the one or more symbols; and (Col. 5 lines 22-51, Col. 4 line 50 to Col. 5 line 10, and Fig. 1, Raikin teaches a method of data compression which involves the creation of a non-anchor data which comprises the symbols making up a source data segment (non-compressed data) that are not the anchor value, ie. an indication of one or more symbols, and the creation of a bit-map which is a map of the location of the symbols, and each of the symbols are represented with 8 bits (respective pattern of plurality of bits). Further, both the generated non-anchor data and the bit-map are output to memory.). Raikin further teaches decompressing the compressed data comprises obtaining a sequence of decompressed bits based on mapping each of the one or more symbols in accordance with the one or more respective locations. (Col. 5 line 52 to Col. 6 line 8, Raikin teaches that in order to decompress a compressed data, the system receives a stream of the compressed data, and based on the bitmap which denotes the respective locations of the non-anchor data, the system sequentially outputs bits to memory in a format such that the output is the decompressed symbols stored in the desired locations.) Sato and Raikin are analogous art because they are from the same field of endeavor, data compression. Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Sato and Raikin to achieve the combined result of the system which compresses data to store in one memory location, and decompresses the compressed data to store in another location, which uses a particular method of using indications of symbols and bit-maps representing the location of those symbols in order to store the final data in a compressed format. One of ordinary skill in the art would have been motivated to make this modification in order to implement a particular method of compression which reduces the size of the data that needs to be stored as discussed in Raikin Col. 5 lines 11-14. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jain et al., U.S. Pub. No. 20220012592, teaches a system which compresses weight matrices by generating a bitmap indicative of respective locations of the weights in a weight matrix, by converting each byte of the matrix into a respective bit in the bitmap and packing the non-zero weights into a compressed array. Adelman et al., U.S. Pub. No. 20230409326, teaches a system which takes a weight matrix, and compresses it by creating a bitmap comprising bits each corresponding to a different respective element of the weight matrix, and whether the corresponding element of the weight matrix has some predetermined default value or a value represented in the compressed matrix data. Gurnani et al., U.S. Pub. No. 20160019547, teaches a system in which an application may come pre-installed on a device during manufacturing before it is actually configured or provisioned in an appropriate manner when the customer triggers an event. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAITLYN HUNG PHAM whose telephone number is (571)272-6333. The examiner can normally be reached M/Tu/Th/F 8:00-6:00 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio Del Mar Perez-Velez can be reached at 571-270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.H.P./Examiner, Art Unit 2133 /KHOA D DOAN/Primary Examiner, Art Unit 2133
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Prosecution Timeline

Jul 17, 2025
Application Filed
Aug 10, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
2y 2m (~1y 0m remaining)
Median Time to Grant
Low
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