Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant application having Application No. 19/273,079 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
INFORMATION CONCERNING DRAWINGS
The applicant’s drawings submitted are acceptable for examination purposes.
STATUS OF CLAIM FOR PRIORITY IN THE APPLICATION
The instant Application No. 19273079 filed 07/17/2025 claims foreign priority to 202510013495.X, filed 01/03/2025.
CLAIM CONSTRUCTION
The present application contains contingent limitations. Applicant is reminded that “the broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” See MPEP 2111.04(II).
See Ex parte Schulhauser, Appeal No. 2013-007847, 2016 WL 6277792, at *9 (PTAB, Apr. 28, 2016) (precedential) (holding "The Examiner did not need to present evidence of the obviousness of the remaining method steps of the claim that are not required to be performed under a broadest reasonable interpretation of the claim"); see also Ex parte Katz, Appeal No. 2010-006083, 2011 WL 514314, at *4-5 (BPAI Jan. 27, 2011).” Board Decision pages 5-6, emphasis in original.
Note that the limitations “when a number of faulty memory blocks in the target memory bank is greater than a threshold” (in claim 14) may never be reached within the scope of the claim under the broadest reasonable interpretation since the number of faulty memory blocks it the target memory bank may not be greater than a threshold and the “when” conditional statement may never be met. Applicant is reminded that “the broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” See MPEP211.04(II).
It is suggested method claim 14 be amended to first require determining that a number of faulty memory blocks in the target memory bank is greater than a threshold, and then in response to the determining, perform the rest of the method steps “controlling…”.
REJECTIONS NOT BASED ON PRIOR ART
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claim 5, the limitations “control the target memory bank to perform the memory operation according to the first address information when the number of the faulty memory blocks in the target memory bank is greater than the threshold” render the claim indefinite since the first address information as recited in claim 4 refers to compute-in-memory zone and claim 3 recites “configure a memory bank of the plurality of memory banks whose faulty memory blocks have a number greater than a threshold as the storage zone”. Thus, it appears that as recited in claim 5, performing the memory operation according to the first address information would correspond to the compute-in-memory zone rather than the storage zone in which banks having faulty memory blocks higher than a threshold are configured according to claim 3. Thus, claim 5 appear to contradict the limitations of claim 3. Appropriate correction/clarification is required.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6, 8-9, 12-14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20200294558) in view of Bennett et al. (US 2015/0095546).
1. A semiconductor device, comprising: a peripheral circuit; and [Yu teaches host device 110 including memory controller 112 and “The memory controller 112 includes a memory physical layer interface 114 for interfacing with the memory device 120.” (par. 0022) (fig. 1 and related text)]
an array of memory cells coupled with the peripheral circuit, comprising: [Yu teaches the memory controller including the memory PHY 114 is coupled to memory cell array 121 (figs. 1-2 and related text)]
a storage zone; and [Yu teaches memory device 120 comprising “normal memory region 124” (fig. 1 and related text) “divide the memory cell array 121 into… a normal memory region 124” (par. 0024)]
a compute-in-memory zone comprising a plurality of memory banks, wherein the storage zone and any one of the memory banks comprise a plurality of memory blocks; [Yu teaches “PIM region 122” (fig. 1 and related text) “dive the memory cell array 121 into a PIM region 122” (par. 0024) “[0084] Referring to FIG. 5, the memory cell array 121 may include, for example, eight banks BANK1 to BANK8. First to fourth banks BANK to BANK4 may be allocated to the PIM region 122, and fifth to eighth banks BANK5 to BANK8 may be allocated to the normal memory region 124. The eight banks BANK1 to BANK8 may be addressed by a 3-bit bank address. When the most significant bit of a bank address is “0”, the first to fourth banks BANK1 to BANK4 may be selected. On the contrary, when the most significant bit of the bank address is “1”, the fifth to eighth banks BANK5 to BANK8 may be selected. As a result, the PIM region 122 and the normal memory region 124 may be selectively accessed according to the most significant bit of the bank address.” where “the memory device 120 may be any one of non-volatile memory devices like a flash memory” (par. 0030)] but Yu does not expressly refer to the storage or normal zone comprising a plurality of blocks and any one of the memory banks comprising a plurality of memory blocks
wherein the plurality of memory banks are configured to perform a compute-in-memory operation; and [Yu teaches ““PIM region 122” (fig. 1 and related text) “dive the memory cell array 121 into a PIM region 122” (par. 0024) “[0084] Referring to FIG. 5, the memory cell array 121 may include, for example, eight banks BANK1 to BANK8. First to fourth banks BANK to BANK4 may be allocated to the PIM region 122” “[0036] The PIM region 122 may refer to a memory cell region configured to access internal processing data for an internal processing operation performed in the internal processing mode. Internal processing operations of the memory device 120 may include a write operation to the PIM region 122 and/or a read operation from the PIM region 122.” “[0049]… For example, an internal processing operation may include a processing operation for internal processing data stored in the PIM region 122, e.g., data search, data arithmetic operation (e.g., add, subtract, multiple, divide, etc.) , data move, data inversion, data shift, data swap, data comparison, logical operations, data processing/operations, etc.”]
wherein the plurality of memory blocks in the storage zone are configured to perform a memory operation [Yu teaches “[0032] In the normal mode, the memory device 120 performs a general data transaction operation under the control of the memory controller 112. A general data transaction operation is a data exchange operation performed according to a predefined protocol like the DDR protocol and/or the LPDDR protocol.” “[0037] The normal memory region 124 may refer to a memory cell region configured to access data according to a general data transaction operation performed in the normal mode. Data transaction operations of memory device 120 may include a write operation to the normal memory region 124 and/or a read operation from the normal memory region 124.”].
Regarding the limitations storage or normal zone comprising a plurality of blocks and any one of the memory banks comprising a plurality of memory blocks, Bennett teaches [”[0023] Each bank 124 of the flash memory 108 may be arranged in blocks of memory cells. A block of memory cells is the unit of erase, i.e., the smallest number of memory cells that are physically erasable together. For increased parallelism, however, the blocks may be operated in larger metablock units.”].
Yu and Bennett are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the system/method of Yu which may use flash memory for normal and PIM regions, where each region may comprise a plurality of banks, to have the banks include a plurality of blocks as taught by Bennett since doing so would facilitate memory access and management operations, where Bennett teaches “[0050] An advantage of the disclosed method and system is that uneven wear may be reduced to provide a potentially longer operating life to a storage device”.
Therefore, it would have been obvious to combine Yu and Bennett for the benefit of creating a storage system/method to obtain the invention as specified in claim 1.
2. The semiconductor device according to claim 1, wherein physical address ranges mapped to the memory blocks in the storage zone and the compute-in-memory zone are different and have no intersection [Yu teaches “[0044] The PIM mode selector 210 may receive the address ADDR from the memory controller 112 through the command/address signal lines 132 of the memory bus 130 and output a PIM mode selection signal PIM_SEL in response to the received address ADDR. The PIM mode selector 210 may determine whether a specific address is included in the received address ADDR and output the PIM mode selection signal PIM_SEL as a result of the determination. In an exemplary embodiment, the PIM mode selector 210 outputs a PIM mode selection signal PIM_SEL set to a first logic level to indicate the internal processing mode when the received address ADDR is within a predefined range of addresses and outputs the PIM mode selection signal PIM_SEL set to a second other logic level to indicate the normal mode when the received address ADDR is outside the predefined range of addresses. For example, the specific address may be an address within the range or the specific address itself.” “[0084] Referring to FIG. 5, the memory cell array 121 may include, for example, eight banks BANK1 to BANK8. First to fourth banks BANK to BANK4 may be allocated to the PIM region 122, and fifth to eighth banks BANK5 to BANK8 may be allocated to the normal memory region 124. The eight banks BANK1 to BANK8 may be addressed by a 3-bit bank address. When the most significant bit of a bank address is “0”, the first to fourth banks BANK1 to BANK4 may be selected. On the contrary, when the most significant bit of the bank address is “1”, the fifth to eighth banks BANK5 to BANK8 may be selected. As a result, the PIM region 122 and the normal memory region 124 may be selectively accessed according to the most significant bit of the bank address.”].
6. The semiconductor device according to claim 1, wherein the peripheral circuit is configured to: configure a first number of memory blocks in the plurality of memory blocks of the memory bank as working memory blocks, and configure a second number of memory blocks as extra memory blocks [Bennett teaches “[0042] Referring to FIG. 8, a simplified version of the storage device 502 of FIG. 5 is shown to illustrate the concept of unused GAT capacity and overprovisioned physical capacity. The SLC flash memory 540 in each bank 524 may include a GAT 526 or other mapping structure with an allocated LBA range 802 and a pre-allocated overprovisioned and unused range 804. Similarly, the MLC flash memory area 542 may include a designated used physical capacity 806 and overprovisioned unused capacity 808.”].
8. The semiconductor device according to claim 6, wherein the peripheral circuit is configured to: control target memory blocks in a target memory bank to perform the compute-in-memory operation according to a first address information, and wherein the target memory bank is a memory bank in the compute-in-memory zone; a number of the target memory blocks is the first number; and the first address information is configured to determine positions of the target memory bank and the target memory blocks [Yu teaches “[0024] For example, the specific address information may indicate specific addresses used to divide the memory cell array 121 into a PIM region 122 and a normal memory region 124. The PIM region 122 may be a memory cell region accessed when the memory device 120 operates in an internal processing mode, and the normal memory region may be a memory cell region accessed when the memory device 120 operates in a normal mode.” “[0038] When the address ADDR received through the command/address signal lines 132 includes a specific address that is the basis of an internal processing operation, the PIM command converter 126 converts the command CMD received through the command/address signal lines 132 into an internal processing operation command PIM_CMD…” “[0044] The PIM mode selector 210 may receive the address ADDR from the memory controller 112 through the command/address signal lines 132 of the memory bus 130 and output a PIM mode selection signal PIM_SEL in response to the received address ADDR. The PIM mode selector 210 may determine whether a specific address is included in the received address ADDR and output the PIM mode selection signal PIM_SEL as a result of the determination. In an exemplary embodiment, the PIM mode selector 210 outputs a PIM mode selection signal PIM_SEL set to a first logic level to indicate the internal processing mode when the received address ADDR is within a predefined range of addresses and outputs the PIM mode selection signal PIM_SEL set to a second other logic level to indicate the normal mode when the received address ADDR is outside the predefined range of addresses. For example, the specific address may be an address within the range or the specific address itself.” “[0045] In an exemplary embodiment, the specific address that the PIM mode selector 210 is aware of is the same as a specific address that is stored in the control register 116 of the memory controller 112 and used to address the PIM region 122. For example, one or more addresses may be stored in the control register 116 as the specific address. “ Bennett teaches “[0023] Each bank 124 of the flash memory 108 may be arranged in blocks of memory cells. A block of memory cells is the unit of erase, i.e., the smallest number of memory cells that are physically erasable together. For increased parallelism, however, the blocks may be operated in larger metablock units… [0042] Referring to FIG. 8, a simplified version of the storage device 502 of FIG. 5 is shown to illustrate the concept of unused GAT capacity and overprovisioned physical capacity. The SLC flash memory 540 in each bank 524 may include a GAT 526 or other mapping structure with an allocated LBA range 802 and a pre-allocated overprovisioned and unused range 804. Similarly, the MLC flash memory area 542 may include a designated used physical capacity 806 and overprovisioned unused capacity 808.”].
9. The semiconductor device according to claim 8, wherein the peripheral circuit is configured to: control the target memory blocks in the target memory bank to perform the memory operation according to the first address information when the number of the target memory blocks is less than the first number [Yu teaches “[0024] For example, the specific address information may indicate specific addresses used to divide the memory cell array 121 into a PIM region 122 and a normal memory region 124.” “[0044]… In an exemplary embodiment, the PIM mode selector 210 outputs a PIM mode selection signal PIM_SEL set to a first logic level to indicate the internal processing mode when the received address ADDR is within a predefined range of addresses and outputs the PIM mode selection signal PIM_SEL set to a second other logic level to indicate the normal mode when the received address ADDR is outside the predefined range of addresses. For example, the specific address may be an address within the range or the specific address itself.” Where “[0042]… According to embodiments, the PIM region 122 and the normal memory region 124 may be set as variable regions in the memory cell array 121. In an exemplary embodiment where the regions are variable, their sizes and physical locations within the memory cell array 121, their sizes and physical locations within the memory cell array 121 may dynamically change based on or more conditions.” Thus the size of the normal region may comprise any size. ““ Bennett teaches “[0023] Each bank 124 of the flash memory 108 may be arranged in blocks of memory cells. A block of memory cells is the unit of erase, i.e., the smallest number of memory cells that are physically erasable together. For increased parallelism, however, the blocks may be operated in larger metablock units…”].
12. A method of operating a semiconductor device, comprising: controlling a target memory bank in a compute-in-memory zone to perform a compute- in-memory operation according to a first address information, wherein the first address information is configured to determine a position of the target memory bank; and [Yu teaches “[0038] When the address ADDR received through the command/address signal lines 132 includes a specific address that is the basis of an internal processing operation, the PIM command converter 126 converts the command CMD received through the command/address signal lines 132 into an internal processing operation command PIM_CMD…” “[0044] The PIM mode selector 210 may receive the address ADDR from the memory controller 112 through the command/address signal lines 132 of the memory bus 130 and output a PIM mode selection signal PIM_SEL in response to the received address ADDR. The PIM mode selector 210 may determine whether a specific address is included in the received address ADDR and output the PIM mode selection signal PIM_SEL as a result of the determination. In an exemplary embodiment, the PIM mode selector 210 outputs a PIM mode selection signal PIM_SEL set to a first logic level to indicate the internal processing mode when the received address ADDR is within a predefined range of addresses and outputs the PIM mode selection signal PIM_SEL set to a second other logic level to indicate the normal mode when the received address ADDR is outside the predefined range of addresses. For example, the specific address may be an address within the range or the specific address itself.” “[0045] In an exemplary embodiment, the specific address that the PIM mode selector 210 is aware of is the same as a specific address that is stored in the control register 116 of the memory controller 112 and used to address the PIM region 122. For example, one or more addresses may be stored in the control register 116 as the specific address.“ “[0084] Referring to FIG. 5, the memory cell array 121 may include, for example, eight banks BANK1 to BANK8. First to fourth banks BANK to BANK4 may be allocated to the PIM region 122, and fifth to eighth banks BANK5 to BANK8 may be allocated to the normal memory region 124. The eight banks BANK1 to BANK8 may be addressed by a 3-bit bank address. When the most significant bit of a bank address is “0”, the first to fourth banks BANK1 to BANK4 may be selected. On the contrary, when the most significant bit of the bank address is “1”, the fifth to eighth banks BANK5 to BANK8 may be selected. As a result, the PIM region 122 and the normal memory region 124 may be selectively accessed according to the most significant bit of the bank address.”]
controlling a target memory block in a storage zone to perform a memory operation according to a second address information, wherein the second address information is configured to determine a position of the target memory block [Yu teaches “normal memory region 124” (fig. 1 and related text) “divide the memory cell array 121 into… a normal memory region 124” (par. 0024) “[0032] In the normal mode, the memory device 120 performs a general data transaction operation under the control of the memory controller 112. A general data transaction operation is a data exchange operation performed according to a predefined protocol like the DDR protocol and/or the LPDDR protocol.” “[0037] The normal memory region 124 may refer to a memory cell region configured to access data according to a general data transaction operation performed in the normal mode. Data transaction operations of memory device 120 may include a write operation to the normal memory region 124 and/or a read operation from the normal memory region 124.” Where “[0044]… The PIM mode selector 210 may determine whether a specific address is included in the received address ADDR and output the PIM mode selection signal PIM_SEL as a result of the determination. In an exemplary embodiment, the PIM mode selector 210 outputs a PIM mode selection signal PIM_SEL set to a first logic level to indicate the internal processing mode when the received address ADDR is within a predefined range of addresses and outputs the PIM mode selection signal PIM_SEL set to a second other logic level to indicate the normal mode when the received address ADDR is outside the predefined range of addresses. For example, the specific address may be an address within the range or the specific address itself.” “[0084] Referring to FIG. 5… fifth to eighth banks BANK5 to BANK8 may be allocated to the normal memory region 124… when the most significant bit of the bank address is “1”, the fifth to eighth banks BANK5 to BANK8 may be selected. As a result, the PIM region 122 and the normal memory region 124 may be selectively accessed according to the most significant bit of the bank address.”, where “the memory device 120 may be any one of non-volatile memory devices like a flash memory” (par. 0030)] but Yu does not expressly refer to target memory blocks; however, regarding these limitations, Bennett teaches [”[0023] Each bank 124 of the flash memory 108 may be arranged in blocks of memory cells. A block of memory cells is the unit of erase, i.e., the smallest number of memory cells that are physically erasable together. For increased parallelism, however, the blocks may be operated in larger metablock units.” [0042] Referring to FIG. 8, a simplified version of the storage device 502 of FIG. 5 is shown to illustrate the concept of unused GAT capacity and overprovisioned physical capacity. The SLC flash memory 540 in each bank 524 may include a GAT 526 or other mapping structure with an allocated LBA range 802 and a pre-allocated overprovisioned and unused range 804. Similarly, the MLC flash memory area 542 may include a designated used physical capacity 806 and overprovisioned unused capacity 808.”].
Yu and Bennett are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the system/method of Yu which may use flash memory for normal and PIM regions, where each region may comprise a plurality of banks, to have the banks include a plurality of blocks as taught by Bennett since doing so would facilitate memory access and management operations, where Bennett teaches “[0050] An advantage of the disclosed method and system is that uneven wear may be reduced to provide a potentially longer operating life to a storage device”.
Therefore, it would have been obvious to combine Yu and Bennett for the benefit of creating a storage system/method to obtain the invention as specified in claim 12.
13. The method according to claim 12, wherein physical address ranges mapped to memory blocks in the storage zone and the compute-in-memory zone are different and have no intersection [The rationale in the rejection of claim 2 is herein incorporated].
14. The method according to claim 12, further comprising: controlling the target memory bank to perform the memory operation according to the first address information when a number of faulty memory blocks in the target memory bank is greater than a threshold [See claim construction section above, where the when statement may never be met within the scope of claim 14. Yu teaches “normal memory region 124” (fig. 1 and related text) “divide the memory cell array 121 into… a normal memory region 124” (par. 0024) “[0032] In the normal mode, the memory device 120 performs a general data transaction operation under the control of the memory controller 112. A general data transaction operation is a data exchange operation performed according to a predefined protocol like the DDR protocol and/or the LPDDR protocol.” “[0037] The normal memory region 124 may refer to a memory cell region configured to access data according to a general data transaction operation performed in the normal mode. Data transaction operations of memory device 120 may include a write operation to the normal memory region 124 and/or a read operation from the normal memory region 124.” Where “[0044]… The PIM mode selector 210 may determine whether a specific address is included in the received address ADDR and output the PIM mode selection signal PIM_SEL as a result of the determination. In an exemplary embodiment, the PIM mode selector 210 outputs a PIM mode selection signal PIM_SEL set to a first logic level to indicate the internal processing mode when the received address ADDR is within a predefined range of addresses and outputs the PIM mode selection signal PIM_SEL set to a second other logic level to indicate the normal mode when the received address ADDR is outside the predefined range of addresses. For example, the specific address may be an address within the range or the specific address itself.” “[0084] Referring to FIG. 5… fifth to eighth banks BANK5 to BANK8 may be allocated to the normal memory region 124… when the most significant bit of the bank address is “1”, the fifth to eighth banks BANK5 to BANK8 may be selected. As a result, the PIM region 122 and the normal memory region 124 may be selectively accessed according to the most significant bit of the bank address.”, where “the memory device 120 may be any one of non-volatile memory devices like a flash memory” (par. 0030)].
20. A system, comprising: a controller; and a semiconductor device coupled to the controller, the semiconductor device comprising: a peripheral circuit; and an array of memory cells coupled with the peripheral circuit, comprising: a storage zone; and a compute-in-memory zone comprising a plurality of memory banks, wherein the storage zone and any one of the memory banks comprise a plurality of memory blocks; wherein the plurality of memory banks are configured to perform a compute-in- memory operation; and wherein the plurality of memory blocks in the storage zone are configured to perform a memory operation [The rationale in the rejection of claim 1 is herein incorporated. Yu teaches controller 112 and memory device 120 coupled to the controller where “The memory controller 112 includes a memory physical layer interface 114 for interfacing with the memory device 120.” (par. 0022) and the memory PHY 114 is coupled to memory cell array 121 (figs. 1-2 and related text)].
Claims 10-11 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20200294558) in view of Bennett et al. (US 2015/0095546) as applied in the rejection of claim 1 above, and further in view of Kamran et al. (US 20220121563).
10. The semiconductor device according to claim 1, wherein the peripheral circuit is configured to: read data in the compute-in-memory zone and write the data into the storage zone; erase the data in the compute-in-memory zone; and read the data in the storage zone and write the data into the compute-in-memory zone [Yu teaches “the memory device 120 may be any one of non-volatile memory devices like a flash memory” (par. 0030) “[0036] The PIM region 122 may refer to a memory cell region configured to access internal processing data for an internal processing operation performed in the internal processing mode. Internal processing operations of the memory device 120 may include a write operation to the PIM region 122 and/or a read operation from the PIM region 122… [0037] The normal memory region 124 may refer to a memory cell region configured to access data according to a general data transaction operation performed in the normal mode. Data transaction operations of memory device 120 may include a write operation to the normal memory region 124 and/or a read operation from the normal memory region 124.” Bennett teaches “[0023] Each bank 124 of the flash memory 108 may be arranged in blocks of memory cells. A block of memory cells is the unit of erase, i.e., the smallest number of memory cells that are physically erasable together.” “[0040] In addition to reassigning a logical range of TRIM'd (logically erased) data where no physical copy of associated data is necessary, and/or reassigning a logical address range where the associated valid data is physically copied from the hottest to the coldest bank, another version of remapping is contemplated. In this additional version of remapping, the logical block address range selected for remapping may be remapped to the coldest memory bank as described in FIG. 6 but, rather than also copying any valid data associated with the remapped logical range to the new bank, the controller will wait until a next host write command comes in with data for that remapped range and divert the data to the bank having the remapped logical address range. In this manner, the time and resources of a concurrent copy operation for valid data can be avoided. Depending on the selected logical block address range for remapping, one or more of the data remapping procedures noted above may be used alone or in combination.”] thus teaching reading, writing and erasing data but the combination of Yu and Bennett does not expressly disclose the read… write… erase… read and write for the same data; however, regarding these limitations, Kamran teaches [“[0048] In some embodiments, the allocated over-provisioned capacity can be utilized by the garbage collection/defragmentation control module 250 as temporary workspace to manage the scheduling of valid page merge operations, wherein the valid pages of one or more victim blocks are copied into free pages in the over-provisioned capacity, which is then followed by writing the valid pages from the over-provisioned capacity into free pages of blocks of the user capacity at some later scheduled time (during a period of low I/O activity) before erasing and reclaiming the victim blocks of the user capacity. In some embodiments, reclaimed pages and blocks can be tagged for inclusion into the over-provisioned capacity in instances when the over-provisioning factor is increased by the adaptive endurance tuning control system 260.”].
Yu, Bennett and Kamran are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Yu and Bennett to include the read… write… erase… read and write for the same data in the manner taught by Kamran such as to perform garbage collection and allow blocks of deleted or obsolete data to be reused as well as facilitating even wear across memory cells as well as “provide automated adaptive endurance tuning of solid-state storage media” (par. 0005).
Therefore, it would have been obvious to combine Yu and Bennett with Kamran for the benefit of creating a storage system/method to obtain the invention as specified in claim 10.
11. The semiconductor device according to claim 10, wherein the data in the compute-in-memory zone comprise valid data configured to perform the compute-in-memory operation, and the peripheral circuit is configured to: read the valid data in the compute-in-memory zone and write the valid data into the storage zone; erase the data in the compute-in-memory zone; and read the valid data in the storage zone and write the valid data into the compute-in-memory zone [The rationale in the rejection of claim 10 is herein incorporated].
15. The method according to claim 12, further comprising: reading data in the compute-in-memory zone and writing the data into the storage zone; erasing the data in the compute-in-memory zone; and reading the data in the storage zone and writing the data into the compute-in-memory zone [The rationale in the rejection of claim 10 is herein incorporated].
16. The method according to claim 15, wherein the data in the compute-in-memory zone comprises valid data configured to perform the compute-in-memory operation, and the method further comprises: reading the valid data in the compute-in-memory zone and writing the valid data into the storage zone; erasing the data in the compute-in-memory zone; and reading the valid data in the storage zone and writing the valid data into the compute-in- memory zone [The rationale in the rejection of claim 10 is herein incorporated].
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20200294558) in view of Bennett et al. (US 2015/0095546) as applied in the rejection of claim 1 above, and further in view of Kim et al. (US 2017/0062074).
17. The method according to claim 12, wherein a number of faulty memory blocks in the target memory bank of the compute-in-memory zone is less than a threshold [Bennett teaches “[0037] Referring again to FIG. 6, the address range selected by the controller for remapping from the memory bank 124, 524 with the highest erase count (see step 620) may be a contiguous or discontiguous range of logical block addresses. In one embodiment, the controller 106 (or controllers 506, 538) may select the range of logical addresses based on a set of selection criteria or a priority listing. For example, the range of addresses may be selected based on the type of data that may require the least amount of time to transfer, or selected based on the most active data such wear due to erase cycles may be more effectively spread out. With respect to prioritizing selection of data from the hottest bank that requires the least overhead or processing time, logically erased data, such as data subject to a TRIM command, may be given highest priority for remapping by the controller.” “[0048] The method and system described above for re-mapping data between memory banks to reduce hot spot wear may be implemented on a removable or standalone storage device or memory embedded in a host. Techniques for implementing a bank wear balancing method, that is triggered at only a few points in the life of a multi-bank memory have been described.” “[0050] An advantage of the disclosed method and system is that uneven wear may be reduced to provide a potentially longer operating life to a storage device. Logical address ranges exclusively assigned to a specific bank may be decreased in one of more banks where hot spots or growing defects have led to an increased number of block erases and remapped to one or more colder memory banks such that the total logical block address range for data handled by the colder block is increased and the total logical block address range associated with the hotter block is decreased. This rebalancing of data responsibility can assist in avoiding uneven wear and premature failure of a multi-bank storage device.”], where, as the blocks compute-in-zone bank Yu may comprise a plurality of blocks as taught by Bennett, which continue to be used in a manner that evens the wear of the blocks, the number of faulty blocks in the bank may be considered as lower than a threshold (note the threshold may be interpreted as any number); however, the combination of Yu and Bennett does not expressly refer to a number of faulty blocks in the bank less than a threshold; however, regarding these limitations, Kim teaches [“[0090] Referring to FIG. 12, the result of the first test may include first through N-th sub-test results. In some example embodiments, the K-th (K is any positive integer equal to or smaller than N) sub-test result may have a logic high value (e.g., “1”) when the number of the failed unit blocks in the K-th memory banks is equal to or greater than a threshold number NLIMIT, and the K-th sub-test result has a logic low value (e.g., “0”) when the number of the failed unit blocks in the K-th memory banks is smaller than the threshold number NLIMIT, as illustrated in FIG. 12. The first through n-th sub-test results may be set or stored in the repair registers PPRR1 through PPRRN, respectively. In other example embodiments, the K-th sub-test result may have a logic low value (e.g., “0”) when the number of the failed unit blocks in the K-th memory banks is equal to or greater than a threshold number NLIMIT, and the K-th sub-test result has a logic high value (e.g., “1”) when the number of the failed unit blocks in the K-th memory banks is smaller than the threshold number NLIMIT”].
Yu, Bennett and Kim are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Yu and Bennett to include a number of faulty blocks in the bank less than a threshold as taught by Kim since doing so would provide flexibility of design and allow for continued use of the bank having less than a threshold number of faulty blocks.
Therefore, it would have been obvious to combine Yu and Bennett with Kim for the benefit of creating a storage system/method to obtain the invention as specified in claim 17.
18. The method according to claim 12, wherein the target memory bank of the compute-in-memory zone comprises a first number of working memory blocks and a second number of extra memory blocks [The rationale in the rejection of claim 6 is herein incorporated].
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20200294558) in view of Bennett et al. (US 2015/0095546) and Kim et al. (US 2017/0062074) as applied in the rejection of claim 1 above, and further in view of Querbach et al. (US 2015/0187439).
19. The method according to claim 18, wherein a number of faulty memory blocks in the target memory bank of the compute-in-memory zone is less than the second number [The rationale in the rejection of claims 17-18 is herein incorporated, where Bennett teaches using blocks and evening the wear of blocks, where a spare blocks are provided (see rejection of claims 6 and 17 above)] but the combination of Yu, Bennett and Kim does not expressly refer to the number of faulty blocks less than the second number of extra blocks; however, regarding these limitations, Querbach teaches [“[0105] Stress testing of Bank 0 continues until all of that bank has been stress tested with each of the programmed stress tests. As the stress testing of Bank 0 progresses, once the number of detected new, unique rows containing a defect exceeds the number of spare rows for Bank 0, the failure maximum is reached (block 520), and the failure maximum flag may be set (block 524) in the Bank 0 Flags location in the repair list repository 224. At that point, no additional memory cell row addresses are recorded (block 514) in the repair list repository since no additional spare rows remain for Bank 0. However, stress testing of Bank 0 may continue, in one embodiment, even after the failure maximum is reached, to identify whether additional defects exist in Bank 0. In other embodiments, stress testing of a particular bank may be terminated once the failure maximum has been reached.”], thus, the number of faulty blocks in a bank should remain below the number of spares before the failure maximum is reached.
Yu, Bennett, Kim and Querbach are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious person of ordinary skill in the art to modify the combination of Yu and Bennett and Kim to have the number of faulty blocks less than the second number of extra blocks as taught by Querbach since doing so would allow for [“[0002]… Defects which have been identified in a memory may be repaired by issuing commands to the device to replace defective memory cells with spare memory cells placed on the device for that purpose.”]
Therefore, it would have been obvious to combine Yu, Bennett and Kim with Querbach for the benefit of creating a storage system/method to obtain the invention as specified in claim 19.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
Kotra et al. (US 2023/0205693) teaches “[0012] Implementations in accordance with the present disclosure are directed to the utilization of processing-in-memory (PIM) resources, such as PIM registers, to expedite non-PIM memory instructions. In various implementations, PIM registers are used to buffer data for non-PIM read instructions and non-PIM write instructions such that data can be transferred between the PIM registers and a memory array opportunistically, for example, when a bank is idle or when a memory row is already open. In some implementations, PIM registers are used as a write buffer to increase the rate at which non-PIM write instructions are drained from memory controller write queues. Writing data to PIM registers is faster than reading from memory because it does not require opening and closing memory rows. The data written to the PIM register can be to the memory array when, for example, the memory bank is idle. In other implementations, PIM registers are used as read buffers (e.g., staging buffers, early fetch buffers, prefetch buffers, and/or a memory-side cache) to reduce read latency. Data targeted by non-PIM read instructions can be read into PIM registers in advance of picking the non-PIM read instruction for dispatch by the memory controller. When the non-PIM read instruction is ready to be picked at the memory controller, the data is read from the PIM registers, which is faster because it does not require opening and closing memory rows. Additional features and advantages of the implementations will be recognized by those of skill in the art in view of the following disclosure.”
Knauerhase (US 2024/0212777) teaches “[0011] An indication of the detected fault is output (e.g., to a decision engine) such that a response to the detected fault is initiable. By testing the memory within the memory module using the processing-in-memory component, the described techniques do not cause additional traffic on the interconnect which reduces contention. This is not possible in conventional approaches to testing memory which utilize the core of the remote host processor to perform operations to test the memory. Furthermore, the described techniques also save cycles of the remote host processor which reduces power consumption and/or frees up the core for execution of other tasks relative to the conventional approaches… [0012] In some aspects, the techniques described herein relate to a system including: a memory of a memory module, and a processing-in-memory component of the memory module to: receive memory testing logic, execute the memory testing logic in the processing-in-memory component to test the memory, and output an indication of a detected fault based on testing the memory… [0014] In some aspects, the techniques described herein relate to a system, further including a decision engine to initiate a response to the detected fault… [0015] In some aspects, the techniques described herein relate to a system, wherein the response is ignoring the detected fault… [0016] In some aspects, the techniques described herein relate to a system, wherein the response is ceasing use of a portion of the memory associated with the detected fault.”
Song (US 2021/0208801) teaches “A processing-in-memory (PIM) device includes a plurality of memory banks and a plurality of multiplication/accumulation (MAC) operators. The MAC operators perform MAC arithmetic operations using data output from the plurality of memory banks and input into the MAC operators. A page is allocated to have a first page size in the plurality of memory banks in a memory mode. The page is allocated to have a second page size, which is greater than the first page size, in the plurality of memory banks in a MAC arithmetic mode.” (Abstract).
CLOSING COMMENTS
a. STATUS OF CLAIMS IN THE APPLICATION
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-2, 5-6 and 8-20 have received a first action on the merits and are subject of a first action non-final.
a(2) ALLOWABLE SUBJECT MATTER
Per the instant office action, claims 3 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
3. The semiconductor device according to claim 1, wherein the peripheral circuit is configured to: configure a memory bank of the plurality of memory banks whose faulty memory blocks have a number greater than a threshold as the storage zone.
7. The semiconductor device according to claim 6, wherein the peripheral circuit is configured to: configure a memory bank of the plurality of memory banks whose faulty memory blocks have a number greater than the second number as the storage zone.
Claim 4 is objected to by virtue of their dependence on objected claim 3.
4. The semiconductor device according to claim 3, wherein the peripheral circuit is configured to: control a target memory bank in the compute-in-memory zone to perform the compute- in-memory operation according to a first address information, wherein the first address information is configured to determine a position of the target memory bank; and control a target memory block in the storage zone to perform the memory operation according to a second address information, wherein the second address information is configured to determine a position of the target memory block.
b. DIRECTION OF FUTURE CORRESPONDENCES
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July 15, 2026
/YAIMA RIGOL/
Primary Examiner, Art Unit 2135
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