Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
The IDS, filed 7/18/26, has been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10 and 13-14 of U.S. Patent No. 12,386,696.
Claim(s) 1-10 and 13-14 of patent #12,386,696 contain(s) every element of claim(s) 1-20 of the instant application and as such anticipate(s) claim(s) 1-20 of the instant application.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Below is the claim mapping between claim 1 of the instant application and claim 1 of the patent 12,386,696.
Current Application
1.A method comprising:
storing a data block to a first cache while executing a child thread;
receiving a cache message to evict the data block from the first cache after storing the data block;
waiting until execution of the child thread is finished before invalidating the data block stored in the first cache;
finishing the execution of the child thread after storing the data block; and
invalidating the data block in the first cache after finishing the execution of the child thread and in response to the cache message.
Patent 12,386,696
1.A device comprising:
a first cache; and a processing core configured to:
while executing a child thread, store a copy of data blocks to the first cache;
receive a cache message to evict the data blocks from the first cache after storing the copy of the data blocks;
refrain from invalidating the data blocks stored in the first cache until the processing core has finished executing the child thread; write an updated value to the first cache after storing the copy of data blocks;
finish executing the child thread after writing the updated value; and
invalidate the data blocks in the first cache after finishing executing the child thread and in response to the cache message.
Claim 1 of the instant application and claim 1 of the patent 12,386,696 are not patentably distinct. Claim 1 of the patent recites a device having a first cache and a processing core configured to perform substantially the same delayed-snoop sequence recited in claim 1 of the instant application. Specifically, the processing core of claim 1 of the patent is configured to store data blocks in the first cache while executing a child thread, receive a cache message to evict the data blocks, refrain from invalidating the data blocks until execution of the child thread and in response to the cache message. These operations correspond to the storing, receiving, waiting, finishing, and invalidating steps of claim 1 of the instant application.
The only material difference is that claim 1 of the instant application is drafted as a method claim and omits the updated value to the first cache operation cited in claim 1 of the patent. This difference does not render the claimed subject matter patentably distinct. Here, the method steps are simply the functional operation of the processing core and cache expressly claimed in the patent. Claim 1 of the patent includes all of the operations of claim 1 of the instant application, anticipating claim 1 of the instant application.
Accordingly, one of ordinary skill in the art would have found claim 1of the instant application to be an obvious variation of the subject matter of claim 1 of the patent. The claims therefore lack patentable distinction required to permit separate patent rights for the same underlying delayed-snoop operation.
Dependent claims 2-8 are similarly mapped to claims 2-8 of patent 12,386,696.
Independent claim 9 is similarly rejected for the same reasons as claim 1. Claim 9 of the instant application is a system claim while claim 1 of the patent is a device claim. Claim 1 of the patent include the same combinations of limitations of claim 1 of the instant application. It would have been obvious to one of ordinary skills to implement the device of claim 1 of the patent as part of a system. Both perform identical functions.
Dependent claims 10-20 are similarly mapped to claims 1-10 and 13-14 of the patent 12,386,696.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20030014602 discloses a cache memory control method of a microprocessor for executing a plurality of threads simultaneously, wherein upon completion of execution of a thread, when there is a cache line corresponding to the address stored in the buffer, data of the address stored in the buffer is written into the cache line.
Patent 6,122,712 discloses a cache coherency controller reflects a cache line including data produced by a preceding thread to a cache line including data produced by a succeeding thread. On the other hand, the cache coherency controller prevents a cache line including data produced by the succeeding thread from being reflected to the cache line including data produced by the preceding thread. The cache coherency controller maintains a sequential order (relationship) among threads based on a thread sequence information table and thereby maintains data anti-dependence.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAN NGUYEN whose telephone number is (571)272-4198. The examiner can normally be reached M-F 7:00am -4:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached at (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THAN NGUYEN/Primary Examiner, Art Unit 2138
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