Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ikuma et al. (WO 2022259762, hereinafter Ikuma, US 2024/0121533 being used as translation).
Re claim 1, Ikuma discloses, A solid-state imaging device comprising: a pixel array (1) in which a plurality of pixels are arranged in rows and columns (fig 1); and a first power supply line (RS, fig 3), wherein each of the plurality of pixels includes: a photoelectric converter that converts received light into a signal charge (PD); a floating diffusion for accumulating the signal charge (FD0); a capacitance accumulator for accumulating the signal charge (C1 and/or C2); a first transfer transistor for reading out the signal charge from the photoelectric converter to the floating diffusion (TG); an overflow transistor for discharging, to the capacitance accumulator, the signal charge that overflows from the photoelectric converter (OF, par [0148]); a second transfer transistor for transferring the signal charge accumulated in the capacitance accumulator to the floating diffusion (GC2 and/or GC1); a first reset transistor that includes a first terminal connected to the second transfer transistor and a second terminal connected to the first power supply line (RS, fig 3); and an amplifier transistor that includes a gate connected to the floating diffusion (SF1), the solid-state imaging device further comprises a resetter for resetting the floating diffusion and the capacitance accumulator at voltages different from each other (pars [0143]-[0148]).
Re claim 5, Ikuma discloses the limitations of claim 1 including wherein the resetter includes a voltage booster for boosting a voltage of the floating diffusion, the voltage booster being included in the solid-state imaging device (Rs).
Re claim 10, Ikuma discloses the limitations of claim 1 including an imaging apparatus comprising the solid-state imaging device according to claim 1 (Abstract).
Allowable Subject Matter
Claim 9 is allowed.
Claims 2-4 and 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOEL W FOSSELMAN whose telephone number is (571)270-3728. The examiner can normally be reached 8:00 - 5:00 M-F.
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/JOEL W FOSSELMAN/Primary Examiner, Art Unit 2639
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