DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A (Figs. 5A-5B, 7A-7B) in the reply filed on 6/1/2026 is acknowledged. Currently, claims 1-15 are pending, but claims 5-7 and 9-11 are withdrawn from examination as directed to non-elected subject matter. And claims 1-4, 8 and 12-15 are examined as follows.
Drawings
Figures 4A-4B should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Display device with different clock signals to different areas”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. in US 2018/0204889 (hereinafter Yu) in view of Jang et al. in US 2022/0208052 (hereinafter Jang).
Regarding claim 1, Yu disclose a display device (Yu’s Fig. 1 and par. 31) comprising:
a display panel (Yu’s Figs. 1-2 and par. 36: see 14) including a first area (Yu’s Fig. 6 and par. 55: area B, shown as bottom two rows in Fig. 15) and a second area (Yu’s Fig. 6 and par. 55: area A, shown as top three rows in Fig. 15) in which a plurality of pixels are arranged (Yu’s Fig. 6 and par. 53: pixels 22);
a plurality of gate drivers (Yu’s Fig. 7 and par. 56: circuit 78/20B for each row), wherein the plurality of gate drivers comprise at least one first gate driver disposed in the first area (Yu’s Fig. 15: see drivers 20B next to two bottom rows) and at least one second gate driver disposed in the second area (Yu’s Fig. 15: see drivers 20B next to notch area IA in the top three rows);
a first clock line (Yu’s Fig. 7 and par. 58: see CLKB) connected to the at least one first gate driver disposed in the first area (Yu’s Fig. 7 and par. 58: see a driver 78/20B corresponding to one of the bottom two rows in Fig. 15);
a second clock line (Yu’s Fig. 7 and par. 58: see CLKA) connected to the at least one second gate driver disposed in the second area (Yu’s Fig. 7 and par. 58: see a driver 78/20B corresponding to one of the top three rows in Fig. 15); and
a clock generator (Yu’s Fig. 7 and par. 56: see 70/72) configured to generate a first clock signal (Yu’s Fig. 7 and par. 58: CLKB) and a second clock signal (Yu’s Fig. 7 and par. 58: CLKA) to be applied to each of the first clock line and the second clock line, respectively (as shown in Yu’s Fig. 7),
wherein the first clock signal and the second clock signal have different voltage levels or gate-on times (Yu’s Figs. 8-10 and par. 59).
Yu fails to disclose a level shifter configured to generate the first clock signal and the second clock signal.
However, in the related field of endeavor of generating different clocks for a display device, Jang discloses a level shifter (Jang’s Fig. 8 and par. 185: see 300) configured to generate a first clock signal and a second clock signal (Jang’s Fig. 8 and par. 185: see CLK1 and CLk2).
Therefore, it would have been obvious to one of ordinary skill in the art, that Yu’s clock generators (Yu’s Fig. 7 and par. 56) are a level shifter (Jang’s Fig. 8 and par. 185), in order to obtain the predictable result of a known circuit that generates clocks for display devices (Jang’s Figs. 1, 4, 8 and par. 133, 135, 185).
By doing such combination, Yu in view of Jang disclose:
a level shifter (Yu’s Fig. 7 and par. 56: see 70/72 which upon combination are implemented by a level shifter per Jang’s Fig. 8 and par. 185) configured to generate a first clock signal (Yu’s Fig. 7 and par. 58: CLKB equivalent to CLK1 in Jang’s Fig. 8) and a second clock signal (Yu’s Fig. 7 and par. 58: CLKA equivalent to CLK2 in Jang’s Fig. 8) to be applied to each of the first clock line and the second clock line, respectively (as shown in Yu’s Fig. 7 and Jang’s Fig. 4).
Regarding claim 2, Yu in view of Jang disclose wherein the first area (Yu’s Fig. 6 and par. 55: area B, shown as bottom two rows in Fig. 15) and the second area (Yu’s Fig. 6 and par. 55: area A, shown as top three rows in Fig. 15) are divided according to a shape of the display panel (Yu’s Fig. 6: see notch 66), and wherein a length of the second area over which the second clock signal is applied (Yu’s Fig. 6: see length of area of region A excluding the notch 66 where CLKA is applied, such as to the top three rows of Fig. 15) is shorter compared to a length of the first area over which the first clock signal is applied (Yu’s Fig. 6: see length of area of region B which does not have a notch and where CLKB is applied, such as to the two bottom rows of Fig. 15).
Regarding claim 3, Yu in view of Jang further disclose wherein the level shifter (Yu’s Fig. 7 and par. 56: see 70/72 which upon combination are implemented by a level shifter per Jang’s Fig. 8 and par. 185) includes a first level shifter (Jang’s Fig. 8 and par. 185: COC1) and a second level shifter (Jang’s Fig. 8 and par. 185: COC2), and the first level shifter generates the first clock signal (Jang’s Fig. 8: see CLK1 out of COC1, where CLK1 is equivalent to CLKB of Yu’s Fig. 7) having a first gate-on voltage and a first gate-off voltage (Jang’s Fig. 9: see VGH and VGL of CLK1 equivalent to low and high levels of CLKB in Yu’s Figs. 8-10), and the second level shifter generates the second clock signal (Jang’s Fig. 8: see CLK2 out of COC2, where CLK2 is equivalent to CLKA of Yu’s Fig. 7) having a second gate-on voltage and a second gate-off voltage (Jang’s Fig. 9: see VGH and VGL of CLK2 equivalent to low and high levels of CLKA in Yu’s Figs. 8-10).
It would also have been obvious to one of ordinary skill in the art, that Yu includes a first and second level shifter generating the two clocks with a gate on and gate off voltage (Jang’s Figs. 8-9), in order to obtain the predictable result of generating the two clocks of Yu’s Fig. 7.
Regarding claim 12, Yu disclose a display device (Yu’s Fig. 1 and par. 31) comprising:
a display panel (Yu’s Figs. 1-2 and par. 36: see 14) including a first area (Yu’s Fig. 6 and par. 55: area B, shown as bottom two rows in Fig. 15) and a second area (Yu’s Fig. 6 and par. 55: area A, shown as top three rows in Fig. 15) in which a plurality of pixels are arranged (Yu’s Fig. 6 and par. 53: pixels 22);
a plurality of gate drivers (Yu’s Fig. 7 and par. 56: circuit 78/20B for each row), wherein the plurality of gate drivers comprise at least one first gate driver disposed in the first area (Yu’s Fig. 15: see drivers 20B next to two bottom rows) and at least one second gate driver disposed in the second area (Yu’s Fig. 15: see drivers 20B next to notch area IA in the top three rows); and
a clock generator (Yu’s Fig. 7 and par. 56: see 70/72) configured to generate a first clock signal (Yu’s Fig. 7 and par. 58: CLKB) and a second clock signal (Yu’s Fig. 7 and par. 58: CLKA) to be respectively applied to the at least one first gate driver disposed in the first area (Yu’s Figs. 7, 15: see drivers 20B next to two bottom rows) and the at least one second gate driver disposed in the second area (Yu’s Figs. 7, 15: see drivers 20B next to notch area IA in the top three rows),
wherein the first clock signal and the second clock signal have different voltage levels (Yu’s Fig. 10 and par. 59: see the step of CLKA which has a different voltage level than CLKB).
Yu fails to disclose a level shifter configured to generate the first clock signal and the second clock signal.
However, in the related field of endeavor of generating different clocks for a display device, Jang discloses a level shifter (Jang’s Fig. 8 and par. 185: see 300) configured to generate a first clock signal and a second clock signal (Jang’s Fig. 8 and par. 185: see CLK1 and CLk2).
Therefore, it would have been obvious to one of ordinary skill in the art, that Yu’s clock generators (Yu’s Fig. 7 and par. 56) are a level shifter (Jang’s Fig. 8 and par. 185), in order to obtain the predictable result of a known circuit that generates clocks for display devices (Jang’s Figs. 1, 4, 8 and par. 133, 135, 185),
By doing such combination, Yu in view of Jang disclose:
a level shifter (Yu’s Fig. 7 and par. 56: see 70/72 which upon combination are implemented by a level shifter per Jang’s Fig. 8 and par. 185) configured to generate a first clock signal (Yu’s Fig. 7 and par. 58: CLKB equivalent to CLK1 in Jang’s Fig. 8) and a second clock signal (Yu’s Fig. 7 and par. 58: CLKA equivalent to CLK2 in Jang’s Fig. 8) to be respectively applied to the at least one first gate driver disposed in the first area (Yu’s Figs. 7, 15: see drivers 20B next to two bottom rows) and the at least one second gate driver disposed in the second area (Yu’s Figs. 7, 15: see drivers 20B next to notch area IA in the top three rows).
Regarding claim 13, Yu in view of Jang disclose wherein the second clock signal (Yu’s Fig. 10: see CLKA) has a voltage level (Yu’s Fig. 10 and par. 59: see middle step of CLKA) less than that of the first clock signal (Yu’s Fig. 10: high level of CLKB).
Claims 4, 8 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Jang as applied above, in further view of Feng et al. in US 2025/0014521 (hereinafter Feng).
Regarding claim 4, Yu in view of Jang fail to disclose wherein the first gate-on voltage is higher than the second gate-on voltage, and the first gate-off voltage is lower than the second gate-off voltage.
However, in the related field of endeavor of multiple clocks used in a display, Feng discloses that the clocks have a different amplitude where the amplitude is increased by increasing the high potential voltage and decreasing the low potential voltage (Feng’s Fig. 15 and par. 139).
Therefore, it would have been obvious to one of ordinary skill in the art, that Yu’s clocks CLKA and CLKB have different amplitudes (as disclosed by Feng’s Fig. 15 and par. 139), in order to obtain the benefit of providing a clock with a higher amplitude to the rows with more pixels (such as those in the center of region B in Yu’s Fig. 6) and a clock with a smaller amplitude to the rows with less pixels (such as those in the left and right regions A of Yu’s Fig. 6) and thus obtain the benefit of adjusting the clock signal according to distance from the gate driver (Feng’s par. 19, such as the distance from the pixels to the drivers 20B in Yu’s Fig. 15), and the intended objective of other combinations of signals CLKA and CLKB (Yu’s par. 59).
By doing such combination, Yu in view of Jang and Feng disclose:
wherein the first gate-on voltage (Yu’s Fig. 8: see high of CLKB, equivalent to VGH of CLK1 in Jang’s Fig. 9 and which has a higher amplitude achieved by increasing the high potential per Feng’s Fig. 15 and par. 139) is higher than the second gate-on voltage (Yu’s Fig. 8: see high of CLKA, equivalent to VGH of CLK2 in Jang’s Fig. 9 and which has a smaller amplitude achieved by decreasing the high potential per Feng’s Fig. 15 and par. 139), and the first gate-off voltage (Yu’s Fig. 8: see low of CLKB, equivalent to VGL of CLK1 in Jang’s Fig. 9 and which has a higher amplitude achieved by decreasing the low potential per Feng’s Fig. 15 and par. 139) is lower than the second gate-off voltage (Yu’s Fig. 8: see low of CLKA, equivalent to VGL of CLK2 in Jang’s Fig. 9 and which has a smaller amplitude achieved by increasing the low potential per Feng’s Fig. 15 and par. 139).
Regarding claim 8, Yu in view of Jang fail to disclose wherein the display panel includes a plurality of boundary areas adjacent to a boundary between the first area and the second area, and wherein a plurality of clock signals applied to the plurality of boundary areas are set to differ by a predetermined magnitude in their voltage levels or gate-on times.
However, in the related field of endeavor of multiple clocks used in a display, Feng discloses a plurality of clock signals (Feng’s Fig. 15) applied to a plurality of different areas in a display (Feng’s Fig. 14: different rows), wherein the plurality of clock signals are set to differ by a predetermined magnitude in their voltage levels (Feng’s Fig. 15 and par. 139: different amplitudes as shown).
Therefore, it would have been obvious to one of ordinary skill in the art, that Yu’s display panel includes a plurality of boundary rows adjacent to a boundary between the region B and the region A (Yu’s Fig. 6, the boundary between A and B includes rows that are applied with differing clocks per Feng’s Fig. 15 and par. 139), and for a plurality of clock signal to be applied to the boundary rows different by a predetermined magnitude in their voltage levels (Feng’s Fig. 15 and par. 139), in order to obtain the benefit of adjusting the clock signal according to the length difference for reaching the gate drivers (Feng’s Fig. 14 and par. 140, such as the length of 30 in Yu’s Fig. 2 to the different gate drives in 20B) and the intended objective of other combinations of signals CLKA and CLKB (Yu’s par. 59).
By doing such combination, Yu in view of Jang and Feng disclose:
wherein the display panel includes a plurality of boundary areas (rows in the boundary of region A and B in Yu’s Figs. 6, 15, 25) adjacent to a boundary between the first area and the second area (Yu’s Figs. 6, 15, 25: boundary between regions A and B), and wherein a plurality of clock signals applied to the plurality of boundary areas (Yu’s Figs. 6, 15, 25: the rows in the boundary of regions A and B, upon combination, are applied a different clock signal depending on the distance from the supply of the clock signal at top per Feng’s Figs. 14-15 and par. 139) are set to differ by a predetermined magnitude in their voltage levels (Feng’s Fig. 15 and par. 139) or gate-on times (limitation in the alternative).
Regarding claim 14, Yu in view of Jang further disclose a power supply (Jang’s Fig. 8: see supply of VGH and VGL which is inherent to the top and bottom levels of CLKA and CLKB of Yu’s Figs. 8-10) configured to supply a gate-on voltage and a gate-off voltage to the level shifter (Jang’s Figs. 8-9 and par. 186-188: VGH and VGL equivalent to top and bottom levels of CLKA and CLKB of Yu’s Figs. 8-10).
Yu in view of Jang fail to disclose wherein the first clock signal has the gate-on voltage higher than that of the second clock signal, and the first clock signal has the gate-off voltage lower than that of the second clock signal.
However, in the related field of endeavor of multiple clocks used in a display, Feng discloses that the clocks have a different amplitude where the amplitude is increased by increasing the high potential voltage and decreasing the low potential voltage (Feng’s Fig. 15 and par. 139).
Therefore, it would have been obvious to one of ordinary skill in the art, that Yu’s clocks CLKA and CLKB have different amplitudes (as disclosed by Feng’s Fig. 15 and par. 139), in order to obtain the benefit of providing a clock with a higher amplitude to the rows with more pixels (such as those in the center of region B in Yu’s Fig. 6) and a clock with a smaller amplitude to the rows with less pixels (such as those in the left and right regions A of Yu’s Fig. 6) and thus obtain the benefit of adjusting the clock signal according to distance from the gate driver (Feng’s par. 19, such as the distance from the pixels to the drivers 20B in Yu’s Fig. 15), and the intended objective of other combinations of signals CLKA and CLKB (Yu’s par. 59).
By doing such combination, Yu in view of Jang and Feng disclose:
wherein the first clock signal has the gate-on voltage (Yu’s Fig. 8: see high of CLKB, equivalent to VGH of CLK1 in Jang’s Fig. 9 and which has a higher amplitude achieved by increasing the high potential per Feng’s Fig. 15 and par. 139) higher than that of the second clock signal (Yu’s Fig. 8: see high of CLKA, equivalent to VGH of CLK2 in Jang’s Fig. 9 and which has a smaller amplitude achieved by decreasing the high potential per Feng’s Fig. 15 and par. 139), and
the first clock signal has the gate-off voltage (Yu’s Fig. 8: see low of CLKB, equivalent to VGL of CLK1 in Jang’s Fig. 9 and which has a higher amplitude achieved by decreasing the low potential per Feng’s Fig. 15 and par. 139) lower than that of the second clock signal (Yu’s Fig. 8: see low of CLKA, equivalent to VGL of CLK2 in Jang’s Fig. 9 and which has a smaller amplitude achieved by increasing the low potential per Feng’s Fig. 15 and par. 139).
Regarding claim 15, Yu in view of Jang fail to disclose wherein the display panel includes a plurality of boundary areas adjacent to the boundary between the first area and the second area, and wherein a plurality of clock signals applied to the plurality of boundary areas are set differently between voltage levels of the first clock signal and the second clock signal.
However, in the related field of endeavor of multiple clocks used in a display, Feng discloses a plurality of clock signals (Feng’s Fig. 15) applied to a plurality of different areas in a display (Feng’s Fig. 14: different rows), wherein the plurality of clock signals are set differently between voltage levels of the first clock signal and the second clock signal (Feng’s Fig. 15 and par. 139: different amplitudes as shown between CLK1 and CLK6).
Therefore, it would have been obvious to one of ordinary skill in the art, that Yu’s display panel includes a plurality of boundary rows adjacent to a boundary between the region B and the region A (Yu’s Fig. 6, the boundary between A and B includes rows that are applied with differing clocks per Feng’s Fig. 15 and par. 139), and for a plurality of clock signal to be set differently between voltage levels of the first clock signal and the second clock signal (Feng’s Fig. 15 and par. 139: different amplitudes as shown between CLK1 and CLK6, where CLK1 or CLK6 are equivalent to CLKA or CLKB of Yu’s Fig. 7), in order to obtain the benefit of adjusting the clock signal according to the length difference for reaching the gate drivers (Feng’s Fig. 14 and par. 140, such as the length of 30 in Yu’s Fig. 2 to the different gate drives in 20B) and the intended objective of other combinations of signals CLKA and CLKB (Yu’s par. 59).
By doing such combination, Yu in view of Jang and Feng disclose:
wherein the display panel includes a plurality of boundary areas (rows in the boundary of region A and B in Yu’s Figs. 6, 15, 25) adjacent to the boundary between the first area and the second area (Yu’s Figs. 6, 15, 25: boundary between regions A and B), and wherein a plurality of clock signals applied to the plurality of boundary areas (Yu’s Figs. 6, 15, 25: the rows in the boundary of regions A and B, upon combination, are applied a different clock signal depending on the distance from the supply of the clock signal at top per Feng’s Figs. 14-15 and par. 139) are set differently between voltage levels of the first clock signal and the second clock signal (Feng’s Fig. 15 and par. 139: different amplitudes as shown between CLK1 and CLK6, where CLK1 or CLK6 are equivalent to CLKA or CLKB of Yu’s Fig. 7).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sasaki et al. in US 2019/0197976 (par. 65) and Furuta et al. in US 2019/0331974 (Fig. 12) directed to different clocks near a notch area.
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/LILIANA CERULLO/Primary Examiner, Art Unit 2621
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