DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in reply to an Amendment filed on June 25, 2026 regarding Application No. 19/274,688. Applicants amended claims 1, 14, and 17. Claims 1-20 are pending.
Priority
Acknowledgment is made of Applicants’ claim for foreign priority under 35 U.S.C. 119(a)-(d). A certified copy of the KR 10-2024-0099245 and KR 10-2025-0028927 applications filed in Korea on July 26, 2024 and March 6, 2025, respectively, have been filed.
Response to Arguments
Applicants’ arguments filed on June 25, 2026 have been fully considered but they are not persuasive or are moot in view of new grounds of rejection.
In response to the argument regarding claim 3 and obviousness (Remarks, p. 10), the Office respectfully disagrees and submits that it would have been obvious to include the recited features since it would have been within the general skill of one of ordinary skill in the art to select power supply voltages on the basis of their suitability for the intended use for pixel compensation and image display. See MPEP 2144.07.
In response to the argument regarding Zhu and “wherein each of the first power supply voltage and the second power supply voltage transitions between a low voltage level and a high voltage level during a frame period” (Remarks, pp. 8, 10, and 12), the Office respectfully submits that the argument is not commensurate with the rejections and Zhu teaches: wherein the first power supply voltage transitions between a low voltage level and a high voltage level during a frame period (e.g., when the display device is turned on at the beginning of a frame period, or turned off during or at the end of a frame period). Although Zhu does not teach: wherein the second power supply voltage transitions between a low voltage level and a high voltage level during a frame period, it would have been obvious to include, such that Zhu as modified teaches: wherein each of the first power supply voltage and the second power supply voltage transitions between a low voltage level and a high voltage level during a frame period, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use for pixel compensation and image display.
In response to the argument regarding Zhu, “the light-emitting control signal E1 is applied to a plurality of pixels simultaneously”, and obviousness (Remarks, p. 12; the citation to pp. 29-30 (claim 15 rejection) of the March 27, 2026 Office action appears to be incorrect and instead, e.g., p. 11 (claim 2 rejection) and/or p. 37 (claim 18 rejection) may be appropriate), the Office respectfully disagrees and submits that it would have been obvious to include the relevant claimed features since it would have been within the general skill of one of ordinary skill in the art to select application of a light emission signal to a plurality of pixels timing on the basis of their suitability for the intended use for image display. See MPEP 2144.07.
For the reasons discussed above and in the rejections, pending claims 1-20 are not allowable.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicants are advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 5, and 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu.
Regarding claim 1, Zhu teaches:
A pixel (pixel unit in FIG. 6) of a display device (electronic device that includes a display panel) comprising (Zhu: FIG. 6, “[0003] An organic light-emitting display panel uses an organic light-emitting element to display images. The organic light-emitting display panel has been increasingly and widely applied to various kinds of electronic devices….”, and “[0126]… As shown in FIG. 6, the organic light-emitting display panel may include a plurality of rows of pixel units 610….”, see also FIGs. 2A-C and 5, [0004]… [A] display panel of the organic light-emitting display device includes a plurality of pixels arranged in a matrix, and each of the plurality of pixels includes an organic light-emitting element….”, [0062], “[0071] FIG. 2B illustrates an example implementation of an organic light-emitting pixel driving circuit in FIG. 2A ….”, “[0126]… A pixel unit in the plurality of rows of pixel units 610 may include an organic light-emitting pixel driving circuit.“, and “[0128] … [A] pixel unit in the plurality of rows of pixel units 610 may include an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B….”):
a first transistor (260 in FIG. 2B) including a gate connected to a first node (N1), a first terminal receiving a first power supply voltage (PVDD voltage), and a second terminal connected to a second node (N2) (Zhu: FIGs. 2B-C, “[0071]… [T]he organic light-emitting pixel driving circuit may include… a driving transistor 260….”, “[0072] The organic light-emitting pixel driving circuit may further include… a first power supply voltage end PVDD….”, and “[0087]… [Referring to FIG. 2C,] [b]ecause the second transistor T2 is turned off and the driving transistor 260 is turned on in the first stage P1, the signal carried by the first power supply voltage end PVDD may raise the voltage level at the node N2 from Vinit to Vref−Vth via the driving transistor 260….”);
a capacitor (C1 in FIG. 2B) including a first electrode connected to a third node (T3-T4-C1 node), and a second electrode connected to the second node (Zhu: FIG. 2B and “[0076]… [A] second electrode of the third transistor T3 may be electrically connected to a first plate of the first capacitor C1…. A second plate of the first capacitor C1 may be electrically connected to a source electrode of the driving transistor 260.”, see also FIG. 2A, “[0071]… [T]the organic light-emitting pixel driving circuit may include… a storage module 250….”, and “[0073]… [T]he storage module 250 may include a first capacitor C1.”);
a second transistor (T4 in FIG. 2B) including a gate receiving a write signal (S1 signal), a first terminal connected to a data line (D1), and a second terminal connected to the third node (Zhu: FIGs. 2B-C, “[0077]… [A] first electrode of the fourth transistor T4 may be electrically connected to the data line D1, and a second electrode of the fourth transistor T4 may be electrically connected to the first plate of the first capacitor C1…. [A] gate electrode of the fourth transistor T4 may be electrically connected to the first scanning signal line S1.”, “[0082]… [Referring to FIG. 2C,] in the first stage P1, a high voltage level signal may be supplied to the first scanning signal line S1…, thereby turning on… the fourth transistor T4….”, and “[0085] In the second stage P2, a high voltage level signal may be supplied to the first scanning signal line S1, thereby turning on… the fourth transistor T4….”, see also FIG. 2A, “[0071]… [T]the organic light-emitting pixel driving circuit may include… a data write-in module 240….”, “[0072] The organic light-emitting pixel driving circuit may further include… a first scanning signal line S1… [and] a data line D1….”, and “[0073]… [T]he data write-in module 240 may include a fourth transistor T4….”);
a third transistor (T1 in FIG. 2B) including a gate receiving the write signal, a first terminal receiving a reference voltage (Vref), and a second terminal connected to the first node (Zhu: FIGs. 2B-C, “[0074]… [A] first electrode of the first transistor T1 may be electrically connected to the reference voltage line V1, a second electrode of the first transistor T1 may be electrically connected to a gate electrode of the driving transistor 260, and a gate electrode of the first transistor T1 may be electrically connected to the first scanning signal line S1.”, “[0082]… [Referring to FIG. 2C,] in the first stage P1, a high voltage level signal may be supplied to the first scanning signal line S1…, thereby turning on the first transistor T1….”, “[0083]… [I]n the first stage P1, a reference voltage Vref may be supplied to the reference voltage line V1….”, and “[0085] In the second stage P2, a high voltage level signal may be supplied to the first scanning signal line S1, thereby turning on the first transistor T1….”, see also FIG. 2A, “[0071]… [T]the organic light-emitting pixel driving circuit may include a first initialization module 210….”, “[0072] The organic light-emitting pixel driving circuit may further include a reference voltage line V1….”, and “[0073]… [T]he first initialization module 210 may include a first transistor T1….”);
a fourth transistor (T3 in FIG. 2B) including a gate receiving an emission signal (E1 signal), a first terminal connected to the first node, and a second terminal connected to the third node (Zhu: FIG. 2B, “[0076]… [A] first electrode of the third transistor T3 may be electrically connected to the gate electrode of the driving transistor 260, a second electrode of the third transistor T3 may be electrically connected to a first plate of the first capacitor C1, and a gate electrode of the third transistor T3 may be electrically connected to the light-emitting control signal line E1….”, and “[0090] In the third stage P3, a high voltage level signal may be supplied to the light-emitting control signal line E1, thereby turning on the third transistor T3….”, see also “[0071]… [T]the organic light-emitting pixel driving circuit may include… a threshold detection module 230….”, “[0072] The organic light-emitting pixel driving circuit may further include… a light-emitting control signal line E1….”, and “[0073]… [T]he threshold detection module 230 may include a third transistor T3….”); and
a light-emitting element (270 in FIG. 2B) including an anode connected to the second node, and a cathode receiving a second power supply voltage (PVEE voltage) (Zhu: FIGs. 2B-C, “[0071]… [T]he organic light-emitting pixel driving circuit may include… a light-emitting element 270.”, “[0072] The organic light-emitting pixel driving circuit may further include… a second power supply voltage end PVEE….”, “[0075]… [A] second electrode of the second transistor T2 may be electrically connected to an anode of the light-emitting element 270….”, and “[0089]… [T]he voltage level of the cathode of the light-emitting element 270 is the second power supply voltage PVEE outputted by the second voltage supply voltage end PVEE….”), and
wherein the first power supply voltage transitions between a low voltage level and a high voltage level during a frame period (e.g., when the display device is turned on at the beginning of a frame period, or turned off during or at the end of a frame period).
However, it is noted that Zhu does not teach:
wherein the second power supply voltage transitions between a low voltage level and a high voltage level during a frame period,
but which would have been obvious to includes, such that Zhu as modified teaches: wherein each of the first power supply voltage and the second power supply voltage transitions between a low voltage level and a high voltage level during a frame period, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use for pixel compensation and image display.
Regarding claim 2, Zhu as modified teaches:
The pixel of claim 1, wherein the display device includes a plurality of pixels (610 in FIG. 6) (Zhu: FIG. 6, “[0126]… As shown in FIG. 6, the organic light-emitting display panel may include a plurality of rows of pixel units 610….”),
wherein the emission signal is applied to the plurality of pixels (Zhu: FIGs. 2C and 6 and “[0090] In the third stage P3, a high voltage level signal may be supplied to the light-emitting control signal line E1, thereby turning on the third transistor T3.”, “[0128] … [A] pixel unit in the plurality of rows of pixel units 610 [in FIG. 6] may include an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B….”, and “[0133]… [W]hen an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B is used in the disclosed organic light-emitting display panel, a timing sequence in FIG. 2C may be configured to drive the organic light-emitting pixel driving circuit in the organic light-emitting display panel….”), and
wherein the write signal is applied to the plurality of pixels in an initialization period (P1 in FIG. 2C), and is applied to the plurality of pixels in a compensation period (P2) (Zhu: FIG. 2C, “[0082]… [I]n the first stage P1, a high voltage level signal may be supplied to the first scanning signal line S1…, thereby turning on the first transistor T1….”, “[0085] In the second stage P2, a high voltage level signal may be supplied to the first scanning signal line S1, thereby turning on the first transistor T1….”, “[0091]… By [the time the light-emitting element 270 emits light],… the voltage level Vs of the source electrode of the driving transistor 260 may be equal to PVEE+Voled.”, “[0092] When the second stage P2 ends,… the voltage level Vg of the gate electrode of the driving transistor 260 may be equal to PVEE+Voled+Vdata−Vref+Vth.”, “[0093]… [T]he driving current of the light-emitting element 260 may be: Ioled∝(Vgs−Vth).sup.2=(Vg−Vs−Vth)2=((PVEE+Voled+Vdata−Vref+Vth)−(PVEE+Voled)−Vth)2=(Vdata−Vref)2.”, and “[0094] From the equation above, the driving current Ioled of the light-emitting element 270 may not be related to the threshold voltage Vth of the driving transistor 260, and the compensation for the threshold voltage of the driving transistor 260 may be realized.”, [0128], and [0133]).
However, it is noted that Zhu as modified does not teach:
wherein the emission signal is substantially simultaneously applied to the plurality of pixels, and
wherein the write signal is substantially simultaneously applied to the plurality of pixels in the initialization period, and is sequentially applied to the plurality of pixels on a row- by-row basis in the compensation period,
but which would have been obvious to include, such that Zhu as modified teaches: wherein the emission signal is substantially simultaneously applied to the plurality of pixels, and wherein the write signal is substantially simultaneously applied to the plurality of pixels in an initialization period, and is sequentially applied to the plurality of pixels on a row- by-row basis in a compensation period, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use for pixel compensation and image display.
Regarding claim 3, Zhu as modified teaches:
The pixel of claim 1.
However, it is noted that Zhu does not teach:
wherein the first power supply voltage has a first low voltage level in an initialization period, and has a first high voltage level in a compensation period, a data writing period and an emission period, and
wherein the second power supply voltage has a second high voltage level in the initialization period, the compensation period and the data writing period, and has a second low voltage level in the emission period,
but which would have been obvious to include, such that Zhu as modified teaches: wherein the first power supply voltage has a first low voltage level in an initialization period, and has a first high voltage level in a compensation period, a data writing period and an emission period, and
wherein the second power supply voltage has a second high voltage level in the initialization period, the compensation period and the data writing period, and has a second low voltage level in the emission period, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use for pixel compensation and image display.
Regarding claim 5, Zhu as modified teaches:
The pixel of claim 1, wherein a frame period for the display device includes (Zhu: FIG. 4 and “[0109]… [A]s shown in FIG. 4, a flow chart of a driving method for an organic light-emitting pixel driving circuit in one frame period is provided. Further, the driving method of the organic light-emitting pixel driving circuit may be configured to drive the organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B.”):
an initialization period (P1 in FIG. 2C) in which the first node and the anode of the light-emitting element are initialized (Zhu: FIG. 2C, “[0083]… [I]n the first stage P1, a reference voltage Vref may be supplied to the reference voltage line V1, and an initialization signal voltage Vinit may be supplied to the initialization signal line V2. Because the first transistor T1 is turned on, the first transistor T1 may transmit the reference voltage Vref carried by the reference voltage line V1 to the node N1, such that the voltage level of the gate electrode of the driving transistor 260 may be equal to Vref….”, and “[0084]… [T]he second transistor T2 may transmit the initialization signal voltage Vinit carried by the initialization signal line V2 to the node N2, such that the voltage level of the anode of the light-emitting element 270 may be equal to Vinit….”, see also FIG. 4);
a compensation period (P2) in which a threshold voltage (Vth) of the first transistor is compensated (Zhu: FIG. 2C, “[0091]… By [the time the light-emitting element 270 emits light],… the voltage level Vs of the source electrode of the driving transistor 260 may be equal to PVEE+Voled.”, “[0092] When the second stage P2 ends,… the voltage level Vg of the gate electrode of the driving transistor 260 may be equal to PVEE+Voled+Vdata−Vref+Vth.”, “[0093]… [T]he driving current of the light-emitting element 260 may be: Ioled∝(Vgs−Vth).sup.2=(Vg−Vs−Vth)2=((PVEE+Voled+Vdata−Vref+Vth)−(PVEE+Voled)−Vth)2=(Vdata−Vref)2.”, and “[0094] From the equation above, the driving current Ioled of the light-emitting element 270 may not be related to the threshold voltage Vth of the driving transistor 260, and the compensation for the threshold voltage of the driving transistor 260 may be realized.”, see also FIG. 4);
a data writing period (P2) in which a data voltage (Vdata) is provided through the data line (Zhu: FIG. 2C, “[0085] In the second stage P2, a high voltage level signal may be supplied to the first scanning signal line S1, thereby turning on… the fourth transistor T4….”, and “[0088]… [B]ecause the fourth transistor T4 is turned on [in the second stage P2], the data signal Vdata carried by the data line D1 maybe transmitted to the first plate of the first capacitor C1….”, see also FIG. 4); and
an emission period (P3) in which the light-emitting element emits light (Zhu: FIG. 2C and “[0091] In the third stage P3,… the light-emitting element 270… emit[s] light….”, see also FIG. 4).
Regarding claim 7, Zhu as modified teaches:
The pixel of claim 5, wherein, in the compensation period,
the emission signal has an off-level (Zhu: FIG. 2C and “[0085] In the second stage P2,… [a] low voltage level signal may be supplied to… the light-emitting control signal line E1, thereby turning off… the third transistor T3.”), and
the first transistor is turned on until a voltage of the second node becomes a voltage obtained by subtracting the threshold voltage of the first transistor from the reference voltage (Zhu: FIG. 2C, “[0085] In the second stage P2,… [a] low voltage level signal may be supplied to the second scanning signal line S2…, thereby turning off the second transistor T2….”, “[0087] Because the second transistor T2 is turned off and the driving transistor 260 is turned on in the first stage P1, the signal carried by the first power supply voltage end PVDD may raise the voltage level at the node N2 from Vinit to Vref−Vth via the driving transistor 260. By then, the voltage level Vs of the source electrode of the driving transistor 260 may be equal to Vref−Vth, where Vth is the threshold voltage of the driving transistor 260.’, and “[0091] In the third stage P3, the driving transistor 260 may be turned on, and the voltage level at the node N2 may be raised from Vref−Vth to PVEE+Voled, such that the light-emitting element 270 may emit light. By then, the voltage level of the anode of the light-emitting element 270 may be equal to PVEE+Voled. That is, the voltage level Vs of the source electrode of the driving transistor 260 may be equal to PVEE+Voled.”).
However, it is noted that Zhu as modified does not teach:
in the compensation period,
the first power supply voltage has a first high voltage level, the second power supply voltage has a second high voltage level, and
the first transistor is turned on until a voltage of the second node becomes a voltage obtained by subtracting the threshold voltage of the first transistor from the reference voltage,
but which would have been obvious to include, such that Zhu as modified teaches: in the compensation period, the first power supply voltage has a first high voltage level, the second power supply voltage has a second high voltage level, and the first transistor is turned on until a voltage of the second node becomes a voltage obtained by subtracting the threshold voltage of the first transistor from the reference voltage, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use for pixel compensation.
Regarding claim 8, Zhu as modified teaches:
The pixel of claim 5, wherein, in the data writing period,
the write signal has an on-level, the emission signal has an off-level, and the data voltage is provided through the data line (Zhu: FIG. 2C, “[0085] In the second stage P2, a high voltage level signal may be supplied to the first scanning signal line S1, thereby turning on… the fourth transistor T4. A low voltage level signal may be supplied to… the light-emitting control signal line E1, thereby turning off… the third transistor T3.”, and “[0088] Further, because the fourth transistor T4 is turned on, the data signal Vdata carried by the data line D1 maybe transmitted to the first plate of the first capacitor C1….”),
the third transistor is turned on in response to the write signal having the on-level, and transfers the reference voltage to the first node (Zhu: FIG. 2C, “[0085] In the second stage P2, a high voltage level signal may be supplied to the first scanning signal line S1, thereby turning on the first transistor T1….”, and “[0086]… [I]in the second stage P2, the reference voltage Vref may be supplied to the reference voltage line V1, and because the first transistor T1 is turned on, the first transistor T1 may transmit the reference voltage Vref to the node N1….”),
the second transistor is turned on in response to the write signal having the on-level, and transfers the data voltage from the data line to the third node (Zhu: FIG. 2C, “[0085] In the second stage P2, a high voltage level signal may be supplied to the first scanning signal line S1, thereby turning on… the fourth transistor T4….”, and “[0088]… [B]ecause the fourth transistor T4 is turned on, the data signal Vdata carried by the data line D1 maybe transmitted to the first plate of the first capacitor C1….”), and
the capacitor stores, between the first electrode and the second electrode, a voltage obtained by subtracting the reference voltage from the data voltage and adding the threshold voltage of the first transistor (Zhu: FIG. 2C and “[0088]… [In the second stage P2,] the voltage difference between the two plates of the first capacitor C1 may be Vdata−Vref+Vth.”).
However, it is noted that Zhu as modified does not teach:
the first power supply voltage has a first high voltage level, the second power supply voltage has a second high voltage level,
the first transistor is turned on in response to the reference voltage at the first node,
but which would have been obvious to include, such that Zhu as modified teaches: the first power supply voltage has a first high voltage level, the second power supply voltage has a second high voltage level, the first transistor is turned on in response to the reference voltage at the first node,
since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use for pixel compensation.
Regarding claim 9, Zhu as modified teaches:
The pixel of claim 5, wherein the data writing period is within the compensation period (Zhu: FIG. 2C, “[0085] In the second stage P2, a high voltage level signal may be supplied to the first scanning signal line S1, thereby turning on… the fourth transistor T4….”, and “[0088]… [B]ecause the fourth transistor T4 is turned on [in the second stage P2], the data signal Vdata carried by the data line D1 maybe transmitted to the first plate of the first capacitor C1….”, “[0091]… By [the time the light-emitting element 270 emits light],… the voltage level Vs of the source electrode of the driving transistor 260 may be equal to PVEE+Voled.”, “[0092] When the second stage P2 ends,… the voltage level Vg of the gate electrode of the driving transistor 260 may be equal to PVEE+Voled+Vdata−Vref+Vth.”, “[0093]… [T]he driving current of the light-emitting element 260 may be: Ioled∝(Vgs−Vth).sup.2=(Vg−Vs−Vth)2=((PVEE+Voled+Vdata−Vref+Vth)−(PVEE+Voled)−Vth)2=(Vdata−Vref)2”, and “[0094] From the equation above, the driving current Ioled of the light-emitting element 270 may not be related to the threshold voltage Vth of the driving transistor 260, and the compensation for the threshold voltage of the driving transistor 260 may be realized.”).
Regarding claim 10, Zhu as modified teaches:
The pixel of claim 5, wherein, in the emission period,
the write signal has an off-level, and the emission signal has an on-level (Zhu: FIG. 2C and “[0090] In the third stage P3, a high voltage level signal may be supplied to the light-emitting control signal line E1, thereby turning on the third transistor T3. A low voltage level signal maybe supplied to the first scanning signal line S1…, thereby turning off the first transistor T1… and the fourth transistor T4….”),
the fourth transistor is turned on in response to the emission signal having the on-level, and connects the third node to the first node (Zhu: FIG. 2C and “[0090] In the third stage P3, a high voltage level signal may be supplied to the light-emitting control signal line E1, thereby turning on the third transistor T3…. Because the third transistor T3 is turned on, two plates of the first capacitor C1 may be electrically connected between the gate electrode and the source electrode of the driving transistor 260.”),
the first transistor generates a driving current based on a voltage stored in the capacitor (Zhu: FIG. 2C, “[0091]… By [the time the light-emitting element 270 emits light],… the voltage level Vs of the source electrode of the driving transistor 260 may be equal to PVEE+Voled.”, “[0092] When the second stage P2 ends, the voltage difference between the two plates of the first capacitor C1 may be equal to Vdata−Vref+Vth…. [T]he voltage level Vg of the gate electrode of the driving transistor 260 may be equal to PVEE+Voled+Vdata−Vref+Vth.”, “[0093]… [T]he driving current of the light-emitting element 260 may be: Ioled∝(Vgs−Vth)2=(Vg−Vs−Vth)2=((PVEE+Voled+Vdata−Vref+Vth)−(PVEE+Voled)−Vth)2=(Vdata−Vref)2.”, and “[0094] From the equation above, the driving current Ioled of the light-emitting element 270 may not be related to the threshold voltage Vth of the driving transistor 260, and the compensation for the threshold voltage of the driving transistor 260 may be realized.”), and
the light-emitting element emits light based on the driving current (Zhu: “[0093] According to the equation of the driving current generated by the light-emitting element 270, the driving current Ioled that flows through the driving transistor 260 and is configured to drive the light-emitting element 270 to emit light ….”, see also [0091]).
However, it is noted that Zhu as modified does not teach:
the first power supply voltage has a first high voltage level, the second power supply voltage has a second low voltage level,
but which would have been obvious to include, such that Zhu as modified teaches: the first power supply voltage has a first high voltage level, the second power supply voltage has a second low voltage level, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use for image display.
Regarding claim 11, Zhu as modified teaches:
The pixel of claim 1, wherein the display device includes a plurality of pixels (610 in FIG. 6) (Zhu: FIG. 6, “[0126]… As shown in FIG. 6, the organic light-emitting display panel may include a plurality of rows of pixel units 610….”),
wherein the emission signal is applied to the plurality of pixels (Zhu: FIGs. 2C and 6 and “[0090] In the third stage P3, a high voltage level signal may be supplied to the light-emitting control signal line E1, thereby turning on the third transistor T3.”, “[0128] … [A] pixel unit in the plurality of rows of pixel units 610 [in FIG. 6] may include an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B….”, and “[0133]… [W]hen an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B is used in the disclosed organic light-emitting display panel, a timing sequence in FIG. 2C may be configured to drive the organic light-emitting pixel driving circuit in the organic light-emitting display panel….”), and
wherein the write signal is applied to the plurality of pixels (Zhu: FIGs. 2C and 6, “[0082]… [I]n the first stage P1, a high voltage level signal may be supplied to the first scanning signal line S1…, thereby turning on the first transistor T1…. and the fourth transistor T4….”, “[0085] In the second stage P2, a high voltage level signal may be supplied to the first scanning signal line S1, thereby turning on the first transistor T1 and the fourth transistor T4….”, [0128], and [0133]).
However, it is noted that Zhu as modified does not teach:
wherein the emission signal is sequentially applied to the plurality of pixels on a row- by-row basis, and
wherein the write signal is sequentially applied to the plurality of pixels on a row-by- row basis,
but which would have been obvious to include, such that Zhu as modified teaches: wherein the emission signal is sequentially applied to the plurality of pixels on a row- by-row basis, and
wherein the write signal is sequentially applied to the plurality of pixels on a row-by- row basis, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use for pixel compensation and image display.
Regarding claim 12, Zhu as modified teaches:
The pixel of claim 1, wherein the first transistor is an N-type metal-oxide- semiconductor transistor (Zhu: FIG. 2B and “[0079]… [T]he driving transistor 260 may be… [an] N-type transistor[] (e.g., NMOS transistors)….”).
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu in view of Takahashi et al. in WO 2024/204135 A1 (hereinafter Takahashi; an original copy and full machine translation thereof was provided with the March 27, 2026 Office action).
Regarding claim 4, Zhu as modified teaches:
The pixel of claim 1, wherein the reference voltage is provided in an initialization period (P1 in FIG. 2C) (Zhu: FIG. 2C and “[0083]… [I]n the first stage P1, a reference voltage Vref may be supplied to the reference voltage line V1, and an initialization signal voltage Vinit may be supplied to the initialization signal line V2….”).
However, it is noted that Zhu as modified does not teach:
wherein the reference voltage is provided through the data line in the initialization period.
Takahashi teaches:
wherein a reference voltage (Vref in FIG. 4) is provided through a data line (SIG in FIG. 1) in an initialization period (t1-t2 in FIG. 4) (Takahashi: FIGs. 1 and 4, “[0023] The signal output portion 14 outputs a video signal… to each signal line SIG. The signal output portion 14 selectively outputs the reference voltage Vref….”, and “(0034] During the period from time t1 to t2, the signal WS and signal AZ become high, and the reference voltage Vref drops to the reference voltage Vofs. In addition, the signal DS becomes high during the period from time t1 to t2….”, see also “[0024] The reference voltage Vref/reference voltage Vofs/signal voltage Vsig selectively output from the signal output portion 14 is written to each pixel PIX of the pixel array portion 11 via the signal line SIG in units of the pixel row selected by the line sequential scan by the write scan portion 12.”, and “(0038] Then, when the signal WS and signal AZ become low at time t6, the luminescence ends and transitions to the extinction period (t5 - the next initialization start time)….”, see also FIG. 2).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Takahashi, such that Zhu as modified teaches: wherein the reference voltage is provided through the data line in an initialization period (reference voltage, data line, and initialization period of Zhu combined with the reference voltage, data line, and initialization period of Takahashi), to provide an initialization period prior to a compensation period for pixel compensation.
Regarding claim 6, Zhu as modified teaches:
The pixel of claim 5, wherein, in the initialization period,
the write signal has an on-level, the emission signal has an off-level (Zhu: FIG. 2C and “[0082]… [I]n the first stage P1, a high voltage level signal may be supplied to the first scanning signal line S1…, thereby turning on the first transistor T1… and the fourth transistor T4. A low voltage level signal may be supplied to the light-emitting control signal line E1, thereby turning off the third transistor T3.”),
the third transistor is turned on in response to the write signal having the on-level, and transfers the reference voltage to the first node (Zhu: FIG. 2C, “[0082]… [I]n the first stage P1, a high voltage level signal may be supplied to the first scanning signal line S1…, thereby turning on the first transistor T1…”, and “[0083]… [I]n the first stage P1, a reference voltage Vref may be supplied to the reference voltage line V1…. Because the first transistor T1 is turned on, the first transistor T1 may transmit the reference voltage Vref carried by the reference voltage line V1 to the node N1….”),
the second transistor is turned on in response to the write signal having the on-level (Zhu: FIG. 2C and “[0082] … [I]n the first stage P1, a high voltage level signal may be supplied to the first scanning signal line S1…, thereby turning on… the fourth transistor T4….”),
the first transistor is turned on (Zhu: FIG. 2C and “[0087]… [T]he driving transistor 260 is turned on in the first stage P1….”),
the first node is initialized based on the reference voltage (Zhu: FIG. 2C and “[0083]… [I]n the first stage P1, a reference voltage Vref may be supplied to the reference voltage line V1…. Because the first transistor T1 is turned on, the first transistor T1 may transmit the reference voltage Vref carried by the reference voltage line V1 to the node N1, such that the voltage level of the gate electrode of the driving transistor 260 may be equal to Vref….”), and
the anode of the light-emitting element is initialized (Zhu: FIG. 2C, “[0082]… [I]n the first stage P1, a high voltage level signal may be supplied to… the second scanning signal line S2, thereby turning on… the second transistor T2….”, and “[0084]… [T]he second transistor T2 may transmit the initialization signal voltage Vinit carried by the initialization signal line V2 to the node N2, such that the voltage level of the anode of the light-emitting element 270 may be equal to Vinit….”).
However, it is noted that Zhu as modified does not teach:
the first power supply voltage has a first low voltage level, the second power supply voltage has a second high voltage level,
the first transistor is turned on in response to the reference voltage at the first node, and transfers the first power supply voltage having the first low voltage level to the anode of the light-emitting element,
the anode of the light-emitting element is initialized based on the first power supply voltage having the first low voltage level,
but which would have been obvious to include, such that Zhu as modified teaches: the first power supply voltage has a first low voltage level, the second power supply voltage has a second high voltage level, the first transistor is turned on in response to the reference voltage at the first node, and transfers the first power supply voltage having the first low voltage level to the anode of the light-emitting element, and the anode of the light-emitting element is initialized based on the first power supply voltage having the first low voltage level, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to provide an initialization period prior to a compensation period for pixel compensation.
However, it is noted that Zhu as modified does not teach:
the reference voltage is provided through the data line,
the second transistor transfers the reference voltage from the data line to the third node.
Takahashi teaches:
a reference voltage (Vref in FIG. 4) is provided through a data line (SIG. in FIG. 1) (Takahashi: FIGs. 1 and 4, “[0023] The signal output portion 14 outputs a video signal… to each signal line SIG. The signal output portion 14 selectively outputs the reference voltage Vref….”, and “(0034] During the period from time t1 to t2, the signal WS and signal AZ become high, and the reference voltage Vref drops to the reference voltage Vofs. In addition, the signal DS becomes high during the period from time t1 to t2….”, see also “[0024] The reference voltage Vref/reference voltage Vofs/signal voltage Vsig selectively output from the signal output portion 14 is written to each pixel PIX of the pixel array portion 11 via the signal line SIG in units of the pixel row selected by the line sequential scan by the write scan portion 12.”, and “(0038] Then, when the signal WS and signal AZ become low at time t6, the luminescence ends and transitions to the extinction period (t5 - the next initialization start time)….” , see also FIG. 2).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Takahashi, such that Zhu as modified teaches: the reference voltage is provided through the data line (reference voltage and data line of Zhu as modified combined with the reference voltage and provided of Takahashi), the second transistor is turned on in response to the write signal having the on-level, and transfers the reference voltage from the data line to the third node (second transistor and turned on, reference voltage, data line, and third node of Zhu as modified combined with the reference voltage and provided of Takahashi), to provide an initialization period prior to a compensation period for pixel compensation.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu in view of Yuan et al. in US 2025/0273142 A1 (hereinafter Yuan).
Regarding claim 13, Zhu as modified teaches:
The pixel of claim 1.
However, it is noted that Zhu as modified does not teach:
further comprising:
a fifth transistor located between the second node and the anode of the light-emitting element, and configured to connect the anode of the light-emitting element to the second node in response to another emission signal.
Yuan teaches:
a fifth transistor (T6 in FIG. 30) located between a second node (N2)and an anode of a light-emitting element (O1), and configured to connect the anode of the light-emitting element to the second node in response to another emission signal (EM3 signal) (Yuan: FIG. 30, “[0290] The gate electrode of the sixth transistor T6 is electrically connected to the third light emitting control line EM3, the source electrode of the sixth transistor T6 is electrically connected to the second node N2, and the drain electrode of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1.”, and “[0291]… T6 is turned on… to conduct the light emitting path.”).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Yuan, such that Zhu as modified teaches: further comprising: a fifth transistor located between the second node and the anode of the light-emitting element, and configured to connect the anode of the light-emitting element to the second node in response to another emission signal (second node and anode of the light emitting element of Zhu combined with the fifth transistor located and configured of Yuan), “to prevent N2 from being coupled through the low voltage terminal ELVSS when the signal is written.” (Yuan: [0291]).
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu in view of Okamoto et al. in US 2024/0321205 A1 (hereinafter Okamoto).
Regarding claim 14, Zhu teaches:
A display device (electronic device that includes a display panel) comprising (Zhu: FIG. 6, “[0003] An organic light-emitting display panel uses an organic light-emitting element to display images. The organic light-emitting display panel has been increasingly and widely applied to various kinds of electronic devices….”, and “[0126]… As shown in FIG. 6, the organic light-emitting display panel may include a plurality of rows of pixel units 610….”, see also FIGs. 2A-C and 5, [0004]… [A] display panel of the organic light-emitting display device includes a plurality of pixels arranged in a matrix, and each of the plurality of pixels includes an organic light-emitting element….”, [0062], “[0071] FIG. 2B illustrates an example implementation of an organic light-emitting pixel driving circuit in FIG. 2A ….”, “[0126]… A pixel unit in the plurality of rows of pixel units 610 may include an organic light-emitting pixel driving circuit.“, and “[0128] … [A] pixel unit in the plurality of rows of pixel units 610 may include an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B….”):
a display panel (see FIG. 6) including a plurality of pixels (610) (Zhu: FIG. 6, “[0126]… As shown in FIG. 6, the organic light-emitting display panel may include a plurality of rows of pixel units 610….”);
provide a data voltage (Vdata) to each of the plurality of pixels (Zhu: FIGs. 2B-C and 6, “[0088]… [Referring to FIG. 2C, in the second stage P2,] because the fourth transistor T4 is turned on, the data signal Vdata carried by the data line D1 maybe transmitted to the first plate of the first capacitor C1….”, “[0128] … [A] pixel unit in the plurality of rows of pixel units 610 [in FIG. 6] may include an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B….”, and “[0133]… [W]hen an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B is used in the disclosed organic light-emitting display panel, a timing sequence in FIG. 2C may be configured to drive the organic light-emitting pixel driving circuit in the organic light-emitting display panel….”);
provide a write signal (S1 signal) to each of the plurality of pixels (Zhu: FIGs. 2B-C and 6, “[0085] In the second stage P2 [in FIG. 2C], a high voltage level signal may be supplied to the first scanning signal line S1, thereby turning on the first transistor T1 and the fourth transistor T4….”, [0128], and [0133]);
wherein each of the plurality of pixels includes (Zhu: FIG. 6, “[0128] … [A] pixel unit in the plurality of rows of pixel units 610 may include an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B….”, and “[0133]… [W]hen an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B is used in the disclosed organic light-emitting display panel, a timing sequence in FIG. 2C may be configured to drive the organic light-emitting pixel driving circuit in the organic light-emitting display panel….”):
a first transistor (260 in FIG. 2B) including a gate connected to a first node (N1), a first terminal receiving a first power supply voltage (PVDD voltage), and a second terminal connected to a second node (N2) (Zhu: FIGs. 2B-C, “[0071]… [T]he organic light-emitting pixel driving circuit may include… a driving transistor 260….”, “[0072] The organic light-emitting pixel driving circuit may further include… a first power supply voltage end PVDD….”, and “[0087]… [Referring to FIG. 2C,] [b]ecause the second transistor T2 is turned off and the driving transistor 260 is turned on in the first stage P1, the signal carried by the first power supply voltage end PVDD may raise the voltage level at the node N2 from Vinit to Vref−Vth via the driving transistor 260….”);
a capacitor (C1 in FIG. 2B) including a first electrode connected to a third node (T3-T4-C1 node), and a second electrode connected to the second node (Zhu: FIG. 2B and “[0076]… [A] second electrode of the third transistor T3 may be electrically connected to a first plate of the first capacitor C1…. A second plate of the first capacitor C1 may be electrically connected to a source electrode of the driving transistor 260.”, see also FIG. 2A, “[0071]… [T]the organic light-emitting pixel driving circuit may include… a storage module 250….”, and “[0073]… [T]he storage module 250 may include a first capacitor C1.”);
a second transistor (T4 in FIG. 2B) disposed between a data line (D1) and the third node, and transferring the data voltage to the third node in response to the write signal (Zhu: FIGs. 2B-C, “[0077]… [Referring to FIG. 2B,] a first electrode of the fourth transistor T4 may be electrically connected to the data line D1, and a second electrode of the fourth transistor T4 may be electrically connected to the first plate of the first capacitor C1…. [A] gate electrode of the fourth transistor T4 may be electrically connected to the first scanning signal line S1.”, “[0085] In the second stage P2 [in FIG. 2C], a high voltage level signal may be supplied to the first scanning signal line S1, thereby turning on… the fourth transistor T4….”, and “[0088]… [B]ecause the fourth transistor T4 is turned on [in the second stage P2], the data signal Vdata carried by the data line D1 maybe transmitted to the first plate of the first capacitor C1….”, see also FIG. 2A, “[0071]… [T]the organic light-emitting pixel driving circuit may include… a data write-in module 240….”, “[0072] The organic light-emitting pixel driving circuit may further include… a first scanning signal line S1… [and] a data line D1….”, and “[0073]… [T]he data write-in module 240 may include a fourth transistor T4….”);
a third transistor (T1 in FIG. 2B) connected to the first node, and transferring a reference voltage (Vref) to the first node in response to the write signal (Zhu: FIGs. 2B-C and “[0074]… [Referring to FIG. 2B,] a first electrode of the first transistor T1 may be electrically connected to the reference voltage line V1, a second electrode of the first transistor T1 may be electrically connected to a gate electrode of the driving transistor 260, and a gate electrode of the first transistor T1 may be electrically connected to the first scanning signal line S1.”, “[0085] In the second stage P2 [in FIG. 2C], a high voltage level signal may be supplied to the first scanning signal line S1, thereby turning on the first transistor T1….”, and “[0086]… [I]n the second stage P2, the reference voltage Vref may be supplied to the reference voltage line V1, and because the first transistor T1 is turned on, the first transistor T1 may transmit the reference voltage Vref to the node N1….”, see also FIG. 2A, “[0071]… [T]the organic light-emitting pixel driving circuit may include a first initialization module 210….”, “[0072] The organic light-emitting pixel driving circuit may further include a reference voltage line V1….”, and “[0073]… [T]he first initialization module 210 may include a first transistor T1….”);
a fourth transistor (T3 in FIG. 2B) disposed between the third node and the first node, and connecting the third node to the first node in response to an emission signal (E1 signal) (Zhu: FIGs. 2B-C and “[0076]… [Referring to FIG. 2B,] a first electrode of the third transistor T3 may be electrically connected to the gate electrode of the driving transistor 260, a second electrode of the third transistor T3 may be electrically connected to a first plate of the first capacitor C1, and a gate electrode of the third transistor T3 may be electrically connected to the light-emitting control signal line E1….”, and “[0090] In the third stage P3 [in FIG. 2C], a high voltage level signal may be supplied to the light-emitting control signal line E1, thereby turning on the third transistor T3…. Because the third transistor T3 is turned on, two plates of the first capacitor C1 may be electrically connected between the gate electrode and the source electrode of the driving transistor 260.”, see also FIG. 2A, “[0071]… [T]the organic light-emitting pixel driving circuit may include… a threshold detection module 230….”, “[0072] The organic light-emitting pixel driving circuit may further include… a light-emitting control signal line E1….”, and “[0073]… [T]he threshold detection module 230 may include a third transistor T3….”); and
a light-emitting element (270 in FIG. 2B) including an anode connected to the second node, and a cathode receiving a second power supply voltage (PVEE voltage) (Zhu: FIGs. 2B-C, “[0071]… [T]he organic light-emitting pixel driving circuit may include… a light-emitting element 270.”, “[0072] The organic light-emitting pixel driving circuit may further include… a second power supply voltage end PVEE….”, “[0075]… [A] second electrode of the second transistor T2 may be electrically connected to an anode of the light-emitting element 270….”, and “[0089]… [T]he voltage level of the cathode of the light-emitting element 270 is the second power supply voltage PVEE outputted by the second voltage supply voltage end PVEE….”), and
wherein the emission signal is applied to the plurality of pixels (Zhu: FIGs. 2C and 6 and “[0090] In the third stage P3, a high voltage level signal may be supplied to the light-emitting control signal line E1, thereby turning on the third transistor T3.”, “[0128] … [A] pixel unit in the plurality of rows of pixel units 610 [in FIG. 6] may include an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B….”, and “[0133]… [W]hen an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B is used in the disclosed organic light-emitting display panel, a timing sequence in FIG. 2C may be configured to drive the organic light-emitting pixel driving circuit in the organic light-emitting display panel….”).
However, it is noted that Zhu does not teach:
wherein the emission signal is substantially simultaneously applied to the plurality of pixels,
but which would have been obvious to include, such that Zhu as modified teaches: wherein the emission signal is substantially simultaneously applied to the plurality of pixels, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use for image display.
However, it is noted that Zhu as modified does not teach:
a data driver configured to provide the data voltage to each of the plurality of pixels;
a scan driver configured to provide the write signal to each of the plurality of pixels; and
a controller configured to control the data driver and the scan driver.
Okamoto teaches:
a data driver (232 in FIG. 27A) configured to provide a data voltage (signal line voltage) to each of a plurality of pixels (230) (Okamoto: FIG. 27A, “[0263]… The display apparatus 10 includes a display region 235… and a second driver circuit portion 232. The display region 235 includes a plurality of pixels 230….”, and “[0264]… A circuit included in the second driver circuit portion 232 functions as, for example, a signal line driver circuit….”, see also FIGs. 32A-B);
a scan driver (231) configured to provide a write signal (scan line signal) to each of the plurality of pixels (Okamoto: FIG. 27A, “[0263]… The display apparatus 10 includes a display region 235… [and] a first driver circuit portion 231…. The display region 235 includes a plurality of pixels 230…..”, and “[0264] A circuit included in the first driver circuit portion 231 functions as… a scan line driver circuit….”, see also FIGs. 32A-B); and
a controller (23 in FIG. 32B) configured to control the data driver and the scan driver (Okamoto: FIG. 32B, “[0349]… In the display apparatus 10 in FIG. 32B,… the first driver circuit portion 231 and the second driver circuit portion 232 are provided in the layer 40….”, “[0352] The layer 40 may include a CPU 23 (Central Processing Unit)… in addition to the peripheral driver circuit….”, and “[0353]… [T]he CPU 23 has a function of controlling the operations of… the circuits provided in the layer 40 ….”).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Okamoto, such that Zhu as modified teaches:
a data driver configured to provide a data voltage to each of the plurality of pixels (provide of Zhu combined with the data driver and provide of Okamoto); a scan driver configured to provide a write signal to each of the plurality of pixels (provide of Zhu combined with scan driver and provide of Okamoto); and a controller configured to control the data driver and the scan driver (controller and control of Okamoto), for image display.
Regarding claim 15, Zhu as modified by Okamoto teaches:
The display device of claim 14, wherein the scan driver applies the write signal to the plurality of pixels (claim 14 above; i.e., the write signals are applied to the plurality of pixels of Zhu by the scan driver of Okamoto), and
applies the emission signal to the plurality of pixels (Zhu: FIGs. 2C and 6, “[0090] In the third stage P3, a high voltage level signal may be supplied to the light-emitting control signal line E1, thereby turning on the third transistor T3….”, “[0091] In the third stage P3,… the light-emitting element 270… emit[s] light….”, “[0128] … [A] pixel unit in the plurality of rows of pixel units 610 may include an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B….”, and “[0133]… [W]hen an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B is used in the disclosed organic light-emitting display panel, a timing sequence in FIG. 2C may be configured to drive the organic light-emitting pixel driving circuit in the organic light-emitting display panel….”).
However, it is noted that Zhu as modified by Okamoto, as particularly cited, does not teach:
wherein the scan driver substantially simultaneously applies the write signal to the plurality of pixels in an initialization period, and sequentially applies the write signal to the plurality of pixels on a row-by-row basis in a compensation period, and
wherein the controller simultaneously applies the emission signal to the plurality of pixels,
but which would have been obvious to include, such that Zhu as modified teaches: wherein the scan driver substantially simultaneously applies the write signal to the plurality of pixels in an initialization period, and sequentially applies the write signal to the plurality of pixels on a row-by-row basis in a compensation period, and wherein the controller simultaneously applies the emission signal to the plurality of pixels, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to provide initialization and compensation periods for pixel compensation and for image display.
Regarding claim 16, Zhu as modified by Okamoto teaches:
The display device of claim 14, wherein the display device has a resolution of about 1,000 pixels per inch (PPI) or more (Okamoto: FIG. 27 and “[0277] The pixel density of the display region 235 [in FIG. 27] is… preferably higher than or equal to 1000 ppi and lower than or equal to 10000 ppi. For example, the pixel density of the display region 235 may be higher than or equal to 2000 ppi and lower than or equal to 6000 ppi, or higher than or equal to 3000 ppi and lower than or equal to 5000 ppi.”).
The motivation to combine is to provide high resolution images.
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu in view of Jinta in US 2023/0180578 A1 (hereinafter Jinta).
Regarding claim 17, Zhu teaches:
An electronic device comprising (Zhu: FIG. 6 and “[0003] An organic light-emitting display panel uses an organic light-emitting element to display images. The organic light-emitting display panel has been increasingly and widely applied to various kinds of electronic devices….”, see also FIGs. 2A-C and 5, [0004]… [A] display panel of the organic light-emitting display device includes a plurality of pixels arranged in a matrix, and each of the plurality of pixels includes an organic light-emitting element….”, [0062], “[0071] FIG. 2B illustrates an example implementation of an organic light-emitting pixel driving circuit in FIG. 2A ….”, “[0126]… A pixel unit in the plurality of rows of pixel units 610 may include an organic light-emitting pixel driving circuit.“, and “[0128] … [A] pixel unit in the plurality of rows of pixel units 610 may include an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B….”):
provide input image data (D1 data in FIG. 2B) (Zhu: FIGs. 2B-C and “[0088]… [Referring to FIG. 2C, in the second stage P2,] because the fourth transistor T4 is turned on, the data signal Vdata carried by the data line D1 maybe transmitted to the first plate of the first capacitor C1….”); and
a display device (see FIG. 6) including a plurality of pixels (610), receiving the input image data, and driving the plurality of pixels based on the input image data (Zhu: FIGs. 2B-C and 6, “[0088]… [Referring to FIG. 2C, in the second stage P2,] because the fourth transistor T4 is turned on, the data signal Vdata carried by the data line D1 maybe transmitted to the first plate of the first capacitor C1….”, “[0091] In the third stage P3,… the light-emitting element 270… emit[s] light….”, “[0093]… [T]he driving current of the light-emitting element 260 may be: Ioled∝(Vgs−Vth)2=(Vg−Vs−Vth)2=((PVEE+Voled+Vdata−Vref+Vth) −(PVEE+Voled)−Vth)2=(Vdata−Vref) 2.”, “[0128] … [A] pixel unit in the plurality of rows of pixel units 610 may include an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B….”, and “[0133]… [W]hen an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B is used in the disclosed organic light-emitting display panel, a timing sequence in FIG. 2C may be configured to drive the organic light-emitting pixel driving circuit in the organic light-emitting display panel….”, see also [0089], [0090], [0092], and [0094]),
wherein each of the plurality of pixels includes (Zhu: FIG. 6, “[0128] … [A] pixel unit in the plurality of rows of pixel units 610 may include an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B….”, and “[0133]… [W]hen an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B is used in the disclosed organic light-emitting display panel, a timing sequence in FIG. 2C may be configured to drive the organic light-emitting pixel driving circuit in the organic light-emitting display panel….”):
a first transistor (260 in FIG. 2B) including a gate connected to a first node (N1), a first terminal receiving a first power supply voltage (PVDD voltage), and a second terminal connected to a second node (N2) (Zhu: FIGs. 2B-C, “[0071]… [T]he organic light-emitting pixel driving circuit may include… a driving transistor 260….”, “[0072] The organic light-emitting pixel driving circuit may further include… a first power supply voltage end PVDD….”, and “[0087]… [Referring to FIG. 2C,] [b]ecause the second transistor T2 is turned off and the driving transistor 260 is turned on in the first stage P1, the signal carried by the first power supply voltage end PVDD may raise the voltage level at the node N2 from Vinit to Vref−Vth via the driving transistor 260….”);
a capacitor (C1 in FIG. 2B) including a first electrode connected to a third node (T3-T4-C1 node), and a second electrode connected to the second node (Zhu: FIG. 2B and “[0076]… [A] second electrode of the third transistor T3 may be electrically connected to a first plate of the first capacitor C1…. A second plate of the first capacitor C1 may be electrically connected to a source electrode of the driving transistor 260.”, see also FIG. 2A, “[0071]… [T]the organic light-emitting pixel driving circuit may include… a storage module 250….”, and “[0073]… [T]he storage module 250 may include a first capacitor C1.”);
a second transistor (T4 in FIG. 2B) disposed between a data line (D1) and the third node, and transferring a data voltage (Vdata) to the third node in response to a write signal (S1 signal) (Zhu: FIGs. 2B-C, “[0077]… [Referring to FIG. 2B,] a first electrode of the fourth transistor T4 may be electrically connected to the data line D1, and a second electrode of the fourth transistor T4 may be electrically connected to the first plate of the first capacitor C1…. [A] gate electrode of the fourth transistor T4 may be electrically connected to the first scanning signal line S1.”, “[0085] In the second stage P2 [in FIG. 2C], a high voltage level signal may be supplied to the first scanning signal line S1, thereby turning on… the fourth transistor T4….”, and “[0088]… [B]ecause the fourth transistor T4 is turned on [in the second stage P2], the data signal Vdata carried by the data line D1 maybe transmitted to the first plate of the first capacitor C1….”, see also FIG. 2A, “[0071]… [T]the organic light-emitting pixel driving circuit may include… a data write-in module 240….”, “[0072] The organic light-emitting pixel driving circuit may further include… a first scanning signal line S1… [and] a data line D1….”, and “[0073]… [T]he data write-in module 240 may include a fourth transistor T4….”);
a third transistor (T1 in FIG. 2B) connected to the first node, and transferring a reference voltage (Vref) to the first node in response to the write signal (Zhu: FIGs. 2B-C and “[0074]… [Referring to FIG. 2B,] a first electrode of the first transistor T1 may be electrically connected to the reference voltage line V1, a second electrode of the first transistor T1 may be electrically connected to a gate electrode of the driving transistor 260, and a gate electrode of the first transistor T1 may be electrically connected to the first scanning signal line S1.”, “[0085] In the second stage P2 [in FIG. 2C], a high voltage level signal may be supplied to the first scanning signal line S1, thereby turning on the first transistor T1….”, and “[0086]… [I]n the second stage P2, the reference voltage Vref may be supplied to the reference voltage line V1, and because the first transistor T1 is turned on, the first transistor T1 may transmit the reference voltage Vref to the node N1….”, see also FIG. 2A, “[0071]… [T]the organic light-emitting pixel driving circuit may include a first initialization module 210….”, “[0072] The organic light-emitting pixel driving circuit may further include a reference voltage line V1….”, and “[0073]… [T]he first initialization module 210 may include a first transistor T1….”);
a fourth transistor (T3 in FIG. 2B) disposed between the third node and the first node, and connecting the third node to the first node in response to an emission signal (E1 signal) (Zhu: FIGs. 2B-C and “[0076]… [Referring to FIG. 2B,] a first electrode of the third transistor T3 may be electrically connected to the gate electrode of the driving transistor 260, a second electrode of the third transistor T3 may be electrically connected to a first plate of the first capacitor C1, and a gate electrode of the third transistor T3 may be electrically connected to the light-emitting control signal line E1….”, and “[0090] In the third stage P3 [in FIG. 2C], a high voltage level signal may be supplied to the light-emitting control signal line E1, thereby turning on the third transistor T3…. Because the third transistor T3 is turned on, two plates of the first capacitor C1 may be electrically connected between the gate electrode and the source electrode of the driving transistor 260.”, see also FIG. 2A, “[0071]… [T]the organic light-emitting pixel driving circuit may include… a threshold detection module 230….”, “[0072] The organic light-emitting pixel driving circuit may further include… a light-emitting control signal line E1….”, and “[0073]… [T]he threshold detection module 230 may include a third transistor T3….”); and
a light-emitting element (270 in FIG. 2B) including an anode connected to the second node, and a cathode receiving a second power supply voltage (PVEE voltage) (Zhu: FIGs. 2B-C, “[0071]… [T]he organic light-emitting pixel driving circuit may include… a light-emitting element 270.”, “[0072] The organic light-emitting pixel driving circuit may further include… a second power supply voltage end PVEE….”, “[0075]… [A] second electrode of the second transistor T2 may be electrically connected to an anode of the light-emitting element 270….”, and “[0089]… [T]he voltage level of the cathode of the light-emitting element 270 is the second power supply voltage PVEE outputted by the second voltage supply voltage end PVEE….”), and
wherein the first power supply voltage transitions between a low voltage level and a high voltage level during a frame period (e.g., when the electronic device is turned on at the beginning of a frame period, or turned off during or at the end of a frame period).
However, it is noted that Zhu does not teach:
wherein the second power supply voltage transitions between a low voltage level and a high voltage level during a frame period,
but which would have been obvious to includes, such that Zhu as modified teaches: wherein each of the first power supply voltage and the second power supply voltage transitions between a low voltage level and a high voltage level during a frame period, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use for pixel compensation and image display.
However, it is noted that Zhu as modified does not teach:
a processor configured to provide the input image data; and
the display device receiving the input image data from the processor.
Jinta teaches:
a processor (21 in FIG. 20) configured to provide input image data (video data) (Jinta: FIG. 20 and “[0201]… The [interface] I/F circuit 15 receives video data… from a host processor 21… provided outside the image display device 1….”, see also FIGs. 1A-B); and
a display device (2) including a plurality of pixels (in pixel array unit 12), receiving the input image data from the processor (Jinta: FIG. 20, “[0198] The display panel 2 includes a pixel array unit 12, a shift register (gate driver) 13, and a selector switch 14. As described above, the pixel array unit 12 includes a plurality of pixels….”, and [0201]… The [interface] I/F circuit 15 receives video data… from a host processor 21… provided outside the image display device 1. The data latch circuit 16 latches the video data at a predetermined timing. The DAC 17 converts the video data latched by the data latch circuit 16 into an analog pixel voltage. The timing generator 18 controls a latch timing of the data latch circuit 16 and a timing of D/A conversion by the DAC 17 on the basis of the control data received by the I/F circuit 15. The frame memory 19 has, for example, a memory capacity for storing video data for one frame displayed on the display panel 2. The display panel 2 updates the display about 60 times per second….”, see also FIGs. 21-22, [0200], [0202]-[0203]).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Jinta, such that Zhu as modified teaches: a processor configured to provide input image data (provide of Zhu combined with the processor and provide of Jinta); and a display device including a plurality of pixels, receiving the input image data from the processor (display device and receiving of Zhu combined with the display device and receiving of Jinta), for image display.
Regarding claim 18, Zhu as modified by Jinta teaches:
The electronic device of claim 17, wherein the emission signal is applied to the plurality of pixels (Zhu: FIGs. 2C and 6, “[0090] In the third stage P3, a high voltage level signal may be supplied to the light-emitting control signal line E1, thereby turning on the third transistor T3….”, “[0128] … [A] pixel unit in the plurality of rows of pixel units 610 may include an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B….”, and “[0133]… [W]hen an organic light-emitting pixel driving circuit illustrated in FIG. 2A or FIG. 2B is used in the disclosed organic light-emitting display panel, a timing sequence in FIG. 2C may be configured to drive the organic light-emitting pixel driving circuit in the organic light-emitting display panel….”), and
wherein the write signal is applied to the plurality of pixels (Zhu: FIGs. 2C and 6, “[0082]… [I]n the first stage P1, a high voltage level signal may be supplied to the first scanning signal line S1…, thereby turning on the first transistor T1…. and the fourth transistor T4….”, “[0085] In the second stage P2, a high voltage level signal may be supplied to the first scanning signal line S1, thereby turning on the first transistor T1 and the fourth transistor T4….”, [0128], and [0133]).
However, it is noted that Zhu as modified by Jinta, as particularly cited, does not teach:
wherein the emission signal is substantially simultaneously applied to the plurality of pixels, and
wherein the write signal is substantially simultaneously applied to the plurality of pixels in an initialization period, and is sequentially applied to the plurality of pixels on a row- by-row basis in a compensation period,
but which would have been obvious to include, such that Zhu as modified teaches: wherein the emission signal is substantially simultaneously applied to the plurality of pixels, and wherein the write signal is substantially simultaneously applied to the plurality of pixels in an initialization period, and is sequentially applied to the plurality of pixels on a row- by-row basis in a compensation period, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use for pixel compensation and image display.
Regarding claim 19, Zhu as modified by Jinta teaches:
The electronic device of claim 17.
However, it is noted that Zhu as modified by Jinta, as particularly cited, does not teach:
wherein the first power supply voltage has a first low voltage level in an initialization period, and has a first high voltage level in a compensation period, a data writing period and an emission period, and
wherein the second power supply voltage has a second high voltage level in the initialization period, the compensation period and the data writing period, and has a second low voltage level in the emission period,
but which would have been obvious to include, such that Zhu as modified teaches: wherein the first power supply voltage has a first low voltage level in an initialization period, and has a first high voltage level in a compensation period, a data writing period and an emission period, and wherein the second power supply voltage has a second high voltage level in the initialization period, the compensation period and the data writing period, and has a second low voltage level in the emission period, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use for pixel compensation and image display.
Regarding claim 20, Zhu as modified by Jinta teaches:
The electronic device of claim 17, wherein the electronic device (1 in FIGs. 1A-B of Jinta) is a virtual reality (VR) device or an augmented reality (AR) device (Jinta: FIGs. 1A-B, “[0129]… As illustrated in FIG. 1A, the image display device 1… includes a display panel 2….”, and “[0285] The image display device 1.. is also applicable to a head mounted display (hereinafter, referred to as an HMD). The HMD can be used for virtual reality (VR)… [or] augmented reality (AR)….”).
The motivation to combine the references is to provide a convenient display mountable on a user’s head.
Conclusion
Applicants’ amendments necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to K. Kiyabu whose telephone number is (571) 270-7836. The examiner can normally be reached Monday to Thursday 9:00 A.M. - 5:00 P.M. ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae, can be reached at (571) 272-3017. The fax number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/K. K./
Examiner, Art Unit 2626
/TEMESGHEN GHEBRETINSAE/Supervisory Patent Examiner, Art Unit 2626 9/2/26
