DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites “the plurality of second pixel blocks corresponding to the entire region of the display panel”. However, claim 12, from which claim 18 depends, recites “a plurality of first pixel blocks associated with a first region of the display panel, the first region corresponding to an entire region of the display panel” and “a plurality of second pixel blocks associated with a second region of the display panel, the second region being different than the first region”. It is unclear how the second pixel blocks can both correspond to the entire region of the display panel (claim 18) and correspond to a region different from the entire region of the display panel (i.e., different than the first region of claim 12). In other words, Applicant has claimed a second region that is both different from and the same as the first region. The scope of the claimed subject matter cannot be determined by one of ordinary skill in the art, and thus claim 18 is indefinite.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 12-14 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kambhatla et al. (US 2018/0190174).
Regarding claim 12, Kambhatla discloses a display system comprising: a display panel including a plurality of pixels (fig. 1, display 113, ¶ 1-2, ¶ 20-22);
a display controller configured to, group all of the plurality of pixels into a plurality of first pixel blocks associated with a first region of the display panel, the first region corresponding to an entire region of the display panel (fig. 1, e.g., driver 114, ¶ 20-33, pixels grouped into blocks, e.g., low, med, or high granularity, see also figs. 2-5; see also ¶ 34-51; see also fig. 11, ¶ 78-88),
and provide first accumulated block stress values based on input image data, each of the first accumulated block stress values representing a degeneration degree of the pixels included in each of the plurality of first pixel blocks (figs. 2-5, ¶ 20-33, history data represents damage that has occurred on the OLED display, see also ¶ 34-51);
and a display driving integrated circuit configured to, group at least a portion of the plurality of pixels into a plurality of second pixel blocks associated with a second region of the display panel, the second region being different than the first region (fig. 1, e.g., controller 124; see also figs. 2-5, ¶ 20-33, history data represents damage that has occurred on the OLED display, e.g., med granularity, see also ¶ 34-51; see also fig. 11, ¶ 78-88),
provide second accumulated block stress values based on the input image data, each of the second accumulated block stress values representing a degeneration degree of the pixels included in each of the plurality of second pixel blocks (figs. 2-5, ¶ 20-33, history data represents damage that has occurred on the OLED display, see also ¶ 34-51, block sizes modified to adjust granularity at which pixel aging is tracked, balance between quality versus power and performance disclosed; block adjustment via multiple iterations disclosed),
and generate final compensation factor values based on the first accumulated block stress values and the second accumulated block stress values (figs. 2-5, ¶ 20-33, history data represents damage that has occurred on the OLED display, intensity of pixels adjusted based on history data, see also ¶ 34-51, block sizes modified to adjust granularity at which pixel aging is tracked, balance between quality versus power and performance disclosed; block adjustment via multiple iterations disclosed; see also fig. 10, ¶ 74-76, history of a parent block is not reset, but is migrated to each of the child blocks; see ¶ 23 and ¶ 31, entire screen brightness adjusted to match most damaged areas, relative brightness of different colors used to calculate the compensation function; see also ¶ 37, pixel histories for all different colors within a block may be combined to create a single pixel history value).
Regarding claim 13, Kambhatla discloses wherein the display controller is further configured to update block boundaries of the plurality of first pixel blocks based on a distribution of the first accumulated block stress values (figs. 2-5, ¶ 20-33, history data represents damage that has occurred on the OLED display, see also ¶ 34-51, block sizes modified to adjust granularity at which pixel aging is tracked, balance between quality versus power and performance disclosed; block adjustment via multiple iterations disclosed).
Regarding claim 14, Kambhatla discloses wherein the display controller is further configured to, generate first compensation factor values with respect to the entire region based on the first accumulated block stress values, and provide the first compensation factor values to the display driving integrated circuit (figs. 2-5, ¶ 20-33, history data represents damage that has occurred on the OLED display, intensity of pixels adjusted based on history data; see also ¶ 34-51).
Regarding claim 17, Kambhatla discloses wherein the second region corresponds to a partial region of the display panel (figs. 2-5, ¶ 20-33, e.g., med granularity, see also ¶ 34-51);
and the display driving integrated circuit is further configured to, correct the input image data corresponding to a rest region of the display panel, the rest region not including the partial region, based on the first compensation factor values (figs. 2-5, ¶ 20-33, history data represents damage that has occurred on the OLED display, intensity of pixels adjusted based on history data; see also ¶ 34-51),
generate second compensation factor values with respect to the partial region of the display panel based on the second accumulated block stress values (figs. 2-5, ¶ 20-33, history data represents damage that has occurred on the OLED display, see also ¶ 34-51, block sizes modified to adjust granularity at which pixel aging is tracked, balance between quality versus power and performance disclosed; block adjustment via multiple iterations disclosed),
and correct the input image data corresponding to the partial region of the display panel based on the second compensation factor values (figs. 2-5, ¶ 20-33, history data represents damage that has occurred on the OLED display, intensity of pixels adjusted based on history data, see also ¶ 34-51, block sizes modified to adjust granularity at which pixel aging is tracked, balance between quality versus power and performance disclosed; block adjustment via multiple iterations disclosed).
Regarding claim 18, Kambhatla discloses wherein a size of each of the plurality of second pixel blocks is greater than a size of each of the plurality of first pixel blocks, the plurality of second pixel blocks corresponding to the entire region of the display panel (figs. 2-5, ¶ 20-33, e.g., low granularity, see also ¶ 34-51; see also ¶ 3, ¶ 21, balance between quality versus power and performance, e.g., larger granularity consumes less power);
and the display driving integrated circuit is further configured to, generate second compensation factor values with respect to the entire region of the display panel based on the second accumulated block stress values (figs. 2-5, ¶ 20-33, history data represents damage that has occurred on the OLED display, intensity of pixels adjusted based on history data, see also ¶ 34-51),
generate the final compensation factor values based on the first compensation factor values and the second compensation factor values (figs. 2-5, ¶ 20-33, history data represents damage that has occurred on the OLED display, intensity of pixels adjusted based on history data, see also ¶ 34-51; see ¶ 23 and ¶ 31, entire screen brightness adjusted to match most damaged areas, relative brightness of different colors used to calculate the compensation function)
and correct the input image data corresponding to the entire region of the display panel based on the final compensation factor values (figs. 2-5, ¶ 20-33, history data represents damage that has occurred on the OLED display, intensity of pixels adjusted based on history data, see also ¶ 34-51, block sizes modified to adjust granularity at which pixel aging is tracked, balance between quality versus power and performance disclosed; block adjustment via multiple iterations disclosed; see ¶ 23 and ¶ 31, entire screen brightness adjusted to match most damaged areas, relative brightness of different colors used to calculate the compensation function).
Regarding claim 19, Kambhatla discloses wherein the display driving integrated circuit is further configured to: generate processed image data by processing the input image data; and generate the second accumulated block stress values by accumulating the processed image data (figs. 2-5, ¶ 20-33, history data represents damage that has occurred on the OLED display, see also ¶ 34-51).
Regarding claim 20, Kambhatla discloses wherein the display controller is further configured to generate the first accumulated block stress values by accumulating the input image data while the display controller performs a normal operation (figs. 2-5, ¶ 20-33, history data represents damage that has occurred on the OLED display, see also ¶ 34-51);
and wherein the display driving integrated circuit is further configured to generate the second accumulated block stress values by accumulating the input image data while the display controller performs a low-power operation (figs. 2-5, ¶ 20-33, history data represents damage that has occurred on the OLED display; screensaver disclosed, see also ¶ 34-51; see also ¶ 3, ¶ 21, balance between quality versus power and performance, e.g., larger granularity consumes less power).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2016/0140895) in view of Kambhatla.
Regarding claim 1, Park discloses an electroluminescent display device comprising: a display panel including a plurality of pixels (fig. 2, ¶ 50-55);
and a degeneration compensating logic configured to, group the plurality of pixels into a plurality of pixel blocks arranged in present block rows and present block columns based on initial block boundaries (abstract, figs. 1-5, ¶ 50, ¶ 66-67);
calculate accumulated block stress values associated with each pixel block based on a first input image data, each accumulated block stress value representing a degeneration degree of the pixels included in each pixel block of the plurality of pixel blocks (figs. 1-5, ¶ 50-51, ¶ 66-67);
perform a boundary updating operation on the plurality of pixel blocks (fig. 1, figs. 7-10, ¶ 50-53, ¶ 70-81, accumulated block stress values are corrected based on stress values of adjacent pixel blocks using estimated stress boundary positions);
correct the first input image data based on the accumulated block stress values and the updated block boundaries (fig. 1, ¶ 50-53, input image data corrected based on corrected stress values; see also figs. 7-10, ¶ 70-81);
receive a second input image data; and calculate new accumulated block stress values based on the second input image data (fig. 1, ¶ 50-53, input image data corrected based on corrected stress values, see ¶ 61, plural frames disclosed; see also figs. 7-10, ¶ 70-81).
Park fails to disclose the performing the boundary updating operation including moving present block boundaries of the plurality of pixel blocks to updated block boundaries based on a distribution of the accumulated block stress values, calculating new accumulated block stress values based on the updated block boundaries, each new accumulated block stress value representing the degeneration degree of the pixels included in the updated block boundaries of each pixel block of the plurality of pixel blocks.
Kambhatla teaches the performing the boundary updating operation including moving present block boundaries of the plurality of pixel blocks to updated block boundaries based on a distribution of the accumulated block stress values (figs. 2-5, ¶ 20-22, block sizes modified to adjust granularity at which pixel aging is tracked, see also ¶ 34-51, granularity of blocks in horizontal and/or vertical direction changed based on block usage value),
calculating new accumulated block stress values based on the updated block boundaries, each new accumulated block stress value representing the degeneration degree of the pixels included in the updated block boundaries of each pixel block of the plurality of pixel blocks (figs. 2-5, ¶ 20-22, block sizes modified to adjust granularity at which pixel aging is tracked, see also ¶ 34-51, block adjustment via multiple iterations disclosed).
Park and Kambhatla are both directed to degradation compensation for display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Park with the block boundary moving of Kambhatla since such a modification enables a balance between quality versus power and performance (Kambhatla, ¶ 21) and protects from image sticking (Kambhatla, ¶ 47).
Regarding claim 2, Park discloses wherein the degeneration compensating logic is further configured to: update the present block boundaries to the updated block boundaries based on a difference between degeneration degrees of adjacent pixel blocks of the plurality of pixel blocks (fig. 1, figs. 7-10, ¶ 50-53, ¶ 70-81, difference values calculated).
Regarding claim 3, Park discloses wherein the degeneration compensating logic is further configured to: update the present block boundaries to the updated block boundaries by comparing the degeneration degree of each pixel block of the plurality of pixel blocks to a desired threshold (fig. 1, figs. 7-10, ¶ 50-53, ¶ 70-81, reference value TH utilized).
Regarding claim 4, Kambhatla further teaches wherein the degeneration compensating logic is further configured to: repeat the boundary updating operation until the updated block boundaries approach burn-in boundaries, the burn-in boundaries indicated based on a degeneration pattern of the plurality of pixels (figs. 2-5, ¶ 20-22, block sizes modified to adjust granularity at which pixel aging is tracked, balance between quality versus power and performance disclosed, see also ¶ 34-51, block adjustment via multiple iterations disclosed; see also ¶ 53, smaller block sizes, or even pixel sizes may be used).
Regarding claim 5, Kambhatla further teaches wherein a moving amount of each block boundary by a single boundary updating operation is limited to be less than a desired moving amount (figs. 2-5, ¶ 20-22, block sizes modified to adjust granularity at which pixel aging is tracked, balance between quality versus power and performance disclosed, see also ¶ 34-51, block adjustment via multiple iterations disclosed; see also ¶ 53, smaller block sizes, or even pixel sizes may be used).
Regarding claim 6, Kambhatla further teaches wherein the desired moving amount is a pixel size (figs. 2-5, ¶ 20-22, block sizes modified to adjust granularity at which pixel aging is tracked, balance between quality versus power and performance disclosed, see also ¶ 34-51, block adjustment via multiple iterations disclosed; see also ¶ 53, smaller block sizes, or even pixel sizes may be used).
Regarding claim 7, Kambhatla further teaches a nonvolatile memory device configured to store the updated block boundaries (fig. 1, ¶ 26-29, ¶ 80-84),
wherein the degeneration compensating logic is further configured to: calculate the new accumulated block stress values based on the updated block boundaries stored in the nonvolatile memory device in response to the boundary updating operation (figs. 2-5, ¶ 20-22, block sizes modified to adjust granularity at which pixel aging is tracked, balance between quality versus power and performance disclosed, see also ¶ 34-51, block adjustment via multiple iterations disclosed).
Regarding claim 8, Park discloses wherein the degeneration compensating logic is further configured to: update column block boundaries of the pixel blocks included in each present block rows based on a distribution of the accumulated block stress values of the pixel blocks included in each of the present block rows (figs. 7-14, ¶ 70-81; see also fig. 16).
Regarding claim 9, Park discloses wherein the degeneration compensating logic is further configured to: update row block boundaries of the plurality of pixel blocks included in each of the present block columns based on a distribution of the accumulated block stress values of the pixel blocks included in each of the present block columns (figs. 7-14, ¶ 70-81; see also fig. 18).
Regarding claim 10, Park discloses wherein the degeneration compensating logic is further configured to: determine delta values indicating a difference between degeneration degrees of adjacent pixel blocks of each of the present block rows or each of the present block columns of the plurality of pixel blocks (fig. 1, figs. 7-10, ¶ 50-53, ¶ 70-81, difference values calculated);
determine moving directions corresponding to the present block boundaries based on the delta values of each of the present block rows or each of the present block columns of the plurality of pixel blocks (fig. 1, figs. 7-10, ¶ 50-53, ¶ 70-81, accumulated block stress values are corrected based on stress values of adjacent pixel blocks using estimated stress boundary positions);
and determine the updated block boundaries based on the moving directions (fig. 1, figs. 7-10, ¶ 50-53, ¶ 70-81, accumulated block stress values are corrected based on stress values of adjacent pixel blocks using estimated stress boundary positions).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Kambhatla as applied to claim 1 above, and further in view of Lee et al. (US 2014/0160142).
Regarding claim 11, Park discloses wherein the degeneration compensating logic is further configured to: determine a function based on an average of the accumulated block stress values of adjacent pixel blocks (fig. 1, figs. 7-10, ¶ 50-53, ¶ 70-81, accumulated block stress values are corrected based on stress values of adjacent pixel blocks using estimated stress boundary positions; average values disclosed);
determine an accumulated distribution function based on values that are obtained by sequentially accumulating values of the determined function (fig. 1, figs. 7-10, ¶ 50-53, ¶ 70-81, accumulated block stress values are corrected based on stress values of adjacent pixel blocks using estimated stress boundary positions);
determine moving directions corresponding to the present block boundaries based on values of the accumulated distribution function (fig. 1, figs. 7-10, ¶ 50-53, ¶ 70-81, accumulated block stress values are corrected based on stress values of adjacent pixel blocks using estimated stress boundary positions);
and determine the updated block boundaries based on the moving directions (fig. 1, figs. 7-10, ¶ 50-53, ¶ 70-81, accumulated block stress values are corrected based on stress values of adjacent pixel blocks using estimated stress boundary positions).
Park in view of Kambhatla fails to disclose a low pass filter function.
Lee teaches a low pass filter function (¶ 51, low pass filter applied to compensation blocks; see also ¶ 59).
Park in view of Kambhatla and Lee are both directed to degradation compensation for display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Park in view of Kambhatla with the low pass filter of Lee since such a modification reduces a deviation between adjacent compensation blocks (Lee, ¶ 51) and provides a smoother image (Lee, ¶ 51).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kambhatla in view of Mobasher et al. (US 2019/0289308).
Regarding claim 15, Kambhatla fails to explicitly disclose wherein the display driving integrated circuit is further configured to: compress the first compensation factor values received from the display controller; and store the compressed first compensation factor values.
Mobasher teaches wherein the display driving integrated circuit is further configured to: compress the first compensation factor values received from the display controller; and store the compressed first compensation factor values (abstract, figs. 1-3, see ¶ 3, ¶ 36-47, stress data compressed and stored in memory).
Kambhatla and Mobasher are both directed to degradation compensation for display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Kambhatla with the compression of Mobasher since such a modification reduces memory requirements (Mobasher, ¶ 3, ¶ 44) and mitigates the effects of truncation errors (Mobasher, ¶ 2).
Claims 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kambhatla in view of Hack et al. (US 2022/0059003).
Regarding claim 16, Kambhatla fails to explicitly disclose wherein the display controller is further configured to: receive a panel image, the panel image generated by an image sensor capturing a test image displayed on the display panel; and update the first compensation factor values based on the panel image.
Hack teaches wherein the display controller is further configured to: receive a panel image, the panel image generated by an image sensor capturing a test image displayed on the display panel; and update the first compensation factor values based on the panel image (figs. 3-4, ¶ 18-20, luminance data acquired by camera used to update degradation data, see also ¶ 72-82, ¶ 86-91).
Kambhatla and Hack are both directed to degradation compensation for display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Kambhatla with the device of Hack since such a modification combines a predictive compensation scheme with the accuracy of a measured scheme (Hack, ¶ 75) and provides accurate correction to emissive displays (Hack, ¶ 76).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10, 15, and 17 of U.S. Patent No. 12,412,523 (hereinafter referred to as Ok). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are anticipated by the reference claims.
Regarding claim 1, Ok claims an electroluminescent display device comprising: a display panel including a plurality of pixels (claim 1);
and a degeneration compensating logic configured to, group the plurality of pixels into a plurality of pixel blocks arranged in present block rows and present block columns based on initial block boundaries (claim 1),
calculate accumulated block stress values associated with each pixel block based on a first input image data, each accumulated block stress value representing a degeneration degree of the pixels included in each pixel block of the plurality of pixel blocks (claim 1),
perform a boundary updating operation on the plurality of pixel blocks, the performing the boundary updating operation including moving present block boundaries of the plurality of pixel blocks to updated block boundaries based on a distribution of the accumulated block stress values (claim 1),
correct the first input image data based on the accumulated block stress values and the updated block boundaries (claim 1),
receive a second input image data (claim 1);
and calculate new accumulated block stress values based on the second input image data and the updated block boundaries, each new accumulated block stress value representing the degeneration degree of the pixels included in the updated block boundaries of each pixel block of the plurality of pixel blocks (claim 1).
Regarding claims 2-11, these claims are rejected in view of claims 2-10, 15, and 17 of Ok, respectively.
Response to Arguments
Applicant's arguments filed 6/30/26 have been fully considered but they are not persuasive. Regarding claims 1 and 12, Applicant argues Kambhatla does not teach “moving present block boundaries … to updated block boundaries” because Kambhatla discloses the addition of new boundaries to create the split in in the pixel block and does not move the present block boundaries (Remarks, pp. 11-13).
Examiner disagrees. Applicant claims “updating” block boundaries by “moving” block boundaries. However, Examiner notes that these boundaries are not physical boundaries, but rather boundaries defined with respect to digital image processing to distinguish between different groups of pixels having different respective stress values. As one of ordinary skill in the art would understand, if a pixel block is delineated by a boundary relative to other pixel blocks, and this boundary is changed in some way (e.g., changed in size or shape such that the changed boundary delineates a different group of pixels), then this boundary has been ‘updated’ by ‘moving’ as is claimed.
Applicant points to an annotated version of fig. 3 of Kambhatla and argues that, e.g., “boundaries A to D are not moved and instead a new boundary, E, is added” to split block 304 into blocks 308 and 310. However, Examiner is not restricted to such a narrow interpretation of the claimed boundaries. For example, boundaries A, B, C, and D (as annotated by Applicant) may be considered a single boundary. Thus Examiner may consider the boundary surrounding block 304 and the boundary surrounding block 308 to be the same boundary, albeit one that has changed in size and/or shape. Kambhatla clearly shows that in this case, said boundary has moved (i.e., changed in size and/or shape) in the top right of fig. 3 relative to the top left of fig. 3. Put differently, Applicant’s claims fail to require boundaries that are unchanging in size, number, and/or relative orientation across “boundary updating” operations. If the (non-physical) boundaries have changed, then the boundaries have moved.
Regarding claim 12, Applicant further argues that Kambhatla discloses “the splitting operations are performed by the same processor which performs the initial grouping operation” (Remarks, p. 15). First, whether or not this is true, Applicant’s claims fail to require ‘different processors’. The claim merely refers to a display controller and a display driving integrated circuit. These terms are not mutually exclusive under their broadest reasonable interpretation. Second, Kambhatla explicitly discloses (see ¶ 26-28 and ¶ 88, figs. 1 and 11) a device driver (e.g., a GPU) that may be part of a system-on-a-chip processing unit and further that various processor blocks may be integrated within a single circuit or may be implemented using two or more separate integrated circuits.
Applicant further argues that “Kambhatla appears to only provide compensation on a per pixel block basis” and “the compensation value applied to block 318 of Fig. 3 would be generated based on the pixel history of block 318 only, and would not include the pixel histories of block 316, block 310, block 304, block 306, etc. (Remarks, pp. 15-16). Examiner disagrees. As cited in the above rejection of the claims, fig. 10 and ¶ 74-76 of Kambhatla explicitly discloses that the history of a parent block is not reset during splitting, but is migrated to each of the child blocks.
Applicant’s arguments regarding the taking of Official Notice with regards to claim 15 are moot in view of the newly cited Mobasher reference. Examiner notes that this reference is added only as directly corresponding evidence to support the prior common knowledge finding (see MPEP 2144.03).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH L CRAWLEY whose telephone number is (571)270-7616. The examiner can normally be reached Monday - Friday 10-6 ET.
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/KEITH L CRAWLEY/Primary Examiner, Art Unit 2626
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