DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the first terminal is a switching terminal and the third terminal is a ground terminal” as recited in claim 24 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The amendment filed 8/11/26 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows:
There is no support in the original disclosure for the limitation of “the first terminal is a switching terminal and the third terminal is a ground terminal” as recited in claim 24, since the invention is only drawn to a high side driver as shown in Fig. 3. Furthermore, the recited limitations of claim 25 are not disclosed when “the first terminal is a switching terminal and the third terminal is a ground terminal” as recited in claim 24.
Applicant is required to cancel the new matter in the reply to this Office Action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 24-25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There is no support in the original disclosure for the limitation of “the first terminal is a switching terminal and the third terminal is a ground terminal” as recited in claim 24, since the invention is only drawn to a high side driver as shown in Fig. 3. Furthermore, the recited limitations of claim 25 are not disclosed when “the first terminal is a switching terminal and the third terminal is a ground terminal” as recited in claim 24.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 24-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 24 the recitation of “the first terminal is a switching terminal and the third terminal is a ground terminal” cannot be understood, since there is no support for such a limitation in the original disclosure. Furthermore, the recited limitations of claim 25 are not disclosed when “the first terminal is a switching terminal and the third terminal is a ground terminal” as recited in claim 24.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 7-13, 16, 19-22 and 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kondou (USPN 9,263,935).
With respect to claim 1, Kondou discloses, in Figs. 7-16, an apparatus (at least one of the circuits disclosed in Figs. 7-16. Note, that each circuit disclosed in Figs. 8-16 are a modification of at least the circuit of Fig. 7. Thus, Figs. 8-16 disclose specific embodiments or details of a circuit that is substantially similar to that of the circuit of Fig. 7. Thus, for ease of explanation the rejections will be discussed with respect to the circuit as shown in Fig. 7 unless otherwise noted) comprising:
a first transistor (e.g., Mp2 of Fig. 7; or Mn5 of Fig. 12) coupled between a power input (Vdd input) and an intermediate terminal (drain terminal connected to Mp3; or source terminal connected to Mn4), and having a first control terminal (gate terminal);
circuitry coupled (Ch1, Dh1, Ch2, Dh2 and Ch3 with Ip2 of Fig. 7, see also operations disclosed in Figs. 9A-9B; or Dl6, Cl6, Cl5 and Dl4 with In5 of Fig. 12) between the power input (Vdd power input via Ch1, Dh1, Ch2 to the PMOS and NMOS transistors of Ip2; or Vdd via Dl6, Cl6, D14, Cl15 and Dl4 to the PMOS and NMOS transistors of In5 of Fig. 12) and the first control terminal and configurable to set a first voltage at the first control terminal (at least one of the voltage levels output from Ip2 or In5. For instance, see 10.6V and 10V of Figs. 9A and 9B output from Ip2. Note, In5 will have a similar operation) responsive to a second voltage at the power input (both the voltages levels output from the respective Ip2 and In5 are responsive, at least in part, on the Vdd voltage on the Vdd power input. Due the voltage level control provided by Ch1, Dh1, Ch2, Dh2 and Ch3, or Dl6, Cl6, Cl5 and Dl4 of Fig. 12, which are dependent, at least in part, upon the voltage at the VDD input);
a second transistor (MP3 of Fig. 7; or M4 of Fig. 12) coupled between the intermediate terminal and a switching terminal (Lx) and having a second control terminal (gate); and
a gate driver circuit (Ip3 or In4 of Fig. 12) coupled to the second control terminal (gate) and configurable to set a state of the second control terminal (high and low value of Ip3 or In4) responsive to a switching signal (output of 31 to Ip3/In4 via In0 and 41-44).
With respect to claim 7, the apparatus of claim 1, wherein the switching signal is a pulse width modulated signal (31 generates a PWM signal).
With respect to claim 8, the apparatus of claim 1, further comprising an inductor (L1) coupled between the switching terminal (Lx) and a power output (voltage on/across C1).
With respect to claim 9, the apparatus of claim 1, wherein the first and second transistors are part of a voltage regulator circuit (the circuitry of Figs. 7-16 constitute a buck regulator).
With respect to claim 10, the apparatus of claim 9, wherein the voltage regulator circuit is a buck voltage regulator circuit (the circuit is a buck regulator).
With respect to claim 11, the apparatus of claim 1, the first and second transistors having a same maximum voltage rating that is below a maximum voltage at the power input (the maximum voltage rating, i.e., withstand voltage, of each transistor is lower than the maximum voltage at the power input, see Col. 16 lines 39-47).
With respect to claim 12, the apparatus of claim 1, wherein the first and second transistors are each a n-channel field effect transistor (NFET) (in Fig. 12 the circuit is connected and operative as claimed).
With respect to claim 13, Kondou discloses, in Figs. 7-16, a voltage regulator circuit (at least one of the buck regulator circuits disclosed in Figs. 7-16. Note that each circuit disclosed in Figs. 8-16 are a modification of at least the circuit of Fig. 7. Thus, Figs. 8-16 disclose specific embodiments or details of a circuit that is substantially similar to that of the circuit of Fig. 7. Thus, for ease of explanation the rejections will be discussed with respect to the circuit as shown in Fig. 7 unless otherwise noted) comprising:
a first transistor (e.g., Mp2 of Fig. 7; or Mn5 of Fig. 12) coupled between a power input (Vdd input) and an intermediate terminal (drain terminal connected to Mp3; or source terminal connected to Mn4), and having a first control terminal (gate terminal);
circuitry coupled (Ch1, Dh1, Ch2, Dh2 and Ch3 with Ip2 of Fig. 7, see also operations disclosed in Figs. 9A-9B; or Dl6, Cl6, Cl5 and Dl4 with In5 of Fig. 12) between the power input (Vdd power input via Ch1, Dh1, Ch2 to the PMOS and NMOS transistors of Ip2; or Vdd via Dl6, Cl6, D14, Cl15 and Dl4 to the PMOS and NMOS transistors of In5 of Fig. 12) and the first control terminal and configurable to set a first voltage at the first control terminal (at least one of the voltage levels output from Ip2 or In5. For instance, see 10.6V and 10V of Figs. 9A and 9B output from Ip2. Note, In5 will have a similar operation) responsive to a second voltage at the power input (both the voltages levels output from the respective Ip2 and In5 are responsive, at least in part, on the Vdd voltage on the Vdd power input due the voltage level control provided by Ch1, Dh1, Ch2, Dh2 and Ch3, or Dl6, Cl6, Cl5 and Dl4 of Fig. 12, which are dependent, at least in part, upon the voltage at the VDD input);
a second transistor (MP3 of Fig. 7; or M4 of Fig. 12) coupled between the intermediate terminal and a switching terminal (Lx) and having a second control terminal (gate); and
a gate driver circuit (Ip3 or In4 of Fig. 12) having a supply input terminal (one of the supply terminals at the sources of the PMOS and NMOS transistors of Ip3 or In4) and a gate drive output (signal at the drains of the PMOS and NMOS transistors of Ip3 or In4), wherein the supply input terminal is coupled to a voltage supply terminal (supply voltage generated at one of the nodes between Dh2 and Ch3 and between Ch3 and Dh3 of Fig. 7; or on of the supply voltage generated at one of the nodes between Dl4 and Cl4 and between Cl4 and Dl3 of Fig. 12) the gate drive output coupled to the second control terminal (gate), and the gate drive circuit configurable to set a state of the second control terminal (high and low value of Ip3 or In4) responsive to a switching signal (output of 31 to Ip3/In4 via In0 and 41-44).
With respect to claim 16, the voltage regulator circuit of claim 13, further comprising:
an inductor coupled (L1 of Fig. 7) between the switching terminal (LX) and a power output (output voltage on/across C1);
a diode (one of the diodes of Dla3, Dla2 and Dha1 connected to ground of Fig. 10 which is a modification of Fig. 7) coupled between the switching terminal (LX via Dl3 of Fig. 10) and a ground terminal (ground at the source of Mn1/cathode of last diode of bottom Dha1)); and
a capacitor coupled between the power output and the ground terminal (C1).
Claims 19 and 20 are rejected for the same reasons as 11 and 12.
With respect to claim 21, an apparatus (Fig. 7) comprising:
a first transistor (MP2) coupled between a first terminal (Vdd terminal via MP1) and a second terminal (terminal at the drain of MP2/source of MP3), and having a first control terminal (gate);
circuitry coupled between the first terminal and the first control terminal (Ch1, Dh1 and Ch2 with Ip2) and configurable to set a first voltage at the first control terminal (voltage on the gate of MP2) responsive to a second voltage at the first terminal (voltage on Vdd terminal which controls the level produced by the output of the PMOS and NMOS transistors of Ip2 due to the operations of Ch1, Dh1 and Ch2);
a second transistor (MP3) coupled between the second terminal and a third terminal (LX) and having a second control terminal (gate); and
a gate driver circuit coupled to the second control terminal (Ip3) and configurable to set a state of the second control terminal responsive to a switching signal (output of 31 which controls IP3 via In0 and 41-44).
With respect to claim 22, the apparatus of claim 21, wherein the first terminal is a power input (Vdd is power input terminal) and the third terminal is a switching terminal (LX is a switching terminal).
With respect to claim 21, (note second interpretation of claim 21) an apparatus (Fig. 7 see also Figs. 9A and 9B) comprising:
a first transistor (MN2) coupled between a first terminal (LX terminal Via Mn3) and a second terminal (terminal at the source of Mn2 and drain of Mn1), and having a first control terminal (gate);
circuitry coupled between the first terminal and the first control terminal (Dl3, Cl3, Dl2 and Cl2 with In2) and configurable to set a first voltage at the first control terminal (output voltage of In2) responsive to a second voltage at the first terminal (the output voltage of In2 is responsive, at least in part on the voltage on LX via the voltage level setting provided by Dl3, Cl3, Dl2 and Cl2, see Figs. 9A and 9B);
a second transistor (MN1) coupled between the second terminal and a third terminal (ground/GND) and having a second control terminal (gate); and
a gate driver circuit (In1) coupled to the second control terminal and configurable to set a state of the second control terminal responsive to a switching signal (output of In1 responsive to the output of 31 via the control of In0 and 41).
With respect to claim 24 (according to the second interpretation), the apparatus of claim 21, wherein the first terminal is a switching terminal (LX is a switching termina) and the third terminal is a ground terminal (GND is a ground terminal).
Allowable Subject Matter
Claims 2-6, 14-15, 17-18 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 25 allowable subject matter could not be determined due to the deficiencies as discussed above with respect to the rejections under 35 U.S.C. 112 first and second paragraphs.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 7-13, 16, 19-22 and 24-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836
