CTNF 19/275,153 CTNF 81182 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 1-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-12 of U.S. Patent No. 12,368,437 . Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-12 of the instant specification are similar to claims 1-12 of 13-20 of United States Patent No. 12,368,437. However, the claims of 13-20 of United States Patent No. 12,368,437 include additional limitations that are not included within claims of the instant application. Such as the “first and second terminals” of the first transistor, the “the first and second terminals” of the second transistors, and the “second cathode” of the second diode and further including the resistor, first voltage clamp circuit, second voltage clamp circuit, and second diode connected to the respective first and second terminals of the first and second transistors and/or respective connections cathode/anodes of the second diode. Nevertheless, it would have been obvious to remove the additional elements and/or connections between the elements of claims 1-12 of United States Patent No. 12,368,437 to arrive at the claimed invention of the instant application, since it has been held that omission of an element and its function in a combination where the remaining elements perform the same functions as before involves only routine skill in the art. In re Karlson, 136 USPQ 184. One would have been motivated to do so for the purposes of simplifying circuit construction . 08-30 AIA A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co. , 151 U.S. 186 (1894); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert , 245 F.2d 467, 114 USPQ 330 (CCPA 1957). A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101. 08-31 AIA Claim s 13-20 is/are rejected under 35 U.S.C. 101 as claiming the same invention as that of claim s 13-20 of prior U.S. Patent No. 12,368,437 . This is a statutory double patenting rejection. With respect to claims 13-20, the above claims are essentially the same as claims 13-20 of United States Patent No. 12,368,437. There is a minor difference in that claims 13-20 of the instant application recite “wherein the first transistor has a first maximum voltage rating” and “the second transistor has a second maximum voltage rating”. However, such maximum voltage ratings (e.g., maximum drain to source voltage ratings/breakdown voltages) are inherent to transistors. Furthermore, there is no explicit range/values in the claims that define the “maximum voltage rating” of the first and second transistors. Thus, the claimed subject matter is the same including the inherent properties of the transistors. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 13-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. With respect to claims 13-20, there it cannot be determined whether or not the recitation of “a voltage supply terminal” on line 16 refers to the same, or different, element as the recitation of “a voltage supply terminal” on line 3. It will be assumed for purposes of examination that the recitation of “a supply voltage terminal” on line 16 refers to the same supply voltage terminal as the recitation of “a supply voltage terminal” on line 3. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1 and 11 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by McCallum (USPN 6,815,845) . With respect to claim 1, McCallum discloses, in Figs. 1 and 2, a power driver circuit (Fig. 2 details of the switching elements S1-S4 disclosed in Fig. 1) comprising: a first transistor (e.g., Q8 of Fig. 1 within S1 of Fig. 2) coupled between an input voltage terminal (E2 via Q1-Q7. Note E2 terminal of S1 of Fig. 2 is connected to the HV Dc SOURCE) and an intermediate terminal (node between the source of Q8 and the drain of Q9), and having a first control terminal (gate), wherein the first transistor has a first maximum voltage rating (all MOSFET transistors have a maximum voltage rating); a second transistor (Q9 of Fig. 1 with S1 of Fig. 2) coupled between the intermediate terminal and a switching terminal (E6 of Fig. 1/ Vo of Fig. 2) and having a second control terminal (gate), wherein the second control terminal is coupled to an output of a gate drive circuit (one of U1, or the circuit that generates E3 and E4 with U1), and the second transistor has a second maximum voltage rating (maximum voltage rating of Q9, all transistors have a maximum voltage rating); a first diode (VR17) having a first anode (connected to E5) and a first cathode (connected to VR16/R9/intermediate node), wherein the first anode is coupled to the input voltage terminal (Via Q1-Q8 or VR1, VR3, VR5, VR7, VR9, VR11, VR13 and VR15); a resistor (R9) coupled between the first cathode (cathode of VR17) and the first control terminal (gate of Q8); a first voltage clamp circuit coupled between the first control terminal and the intermediate terminal (VR16); a second voltage clamp circuit (VR15) coupled between the first control terminal and the switching terminal (anode of VR15 is connected to the first control terminal/gate of Q8 via R9 and the anode of VR15 is connected to the switching terminal/E6. Thus, the anode of VR15 is connected between the gate of Q8 and the switching terminal via R9 and Q9); and a second diode (CR8) coupled between the first control terminal (gate of Q8) and a voltage supply terminal (E1 which is the voltage supply terminal of 102 of Fig. 2). With respect to claim 11, the power driver circuit of claim 1, wherein the first maximum voltage rating is equal to the second maximum voltage rating (the transistors are constructed the same and will thus have the same maximum voltage rating) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vinciarelli (USPN 7,561,446) in view of McCallum (USPN 6,815,845) . With respect to claim 8, Vinciarelli discloses, in Fig. 1 a high voltage buck boost regulator having an switching (130) coupled between two switches of a high voltage bridge circuit (Q1 and Q2), wherein the inductor is connected between the switching node (130) and an output node (132, e.g., output to the second bridge of Q3 and Q4). Vinciarelli fails to disclose the details of the switches Q1-Q4 of the bridge circuit. Furthermore, Vinciarelli fails to disclose the circuit as recited in claim 1. However, McCallum discloses the circuit as recited in claim 1 (see above rejection). Furthermore, the circuit of McCallum is designed to withstand high voltages and have a low noise/ripple (see Col. 2 lines 46-48 and Col. 5 lines 34-51). It would have been obvious to replace the generic switches of Vinciarelli with the specific switch of Fig. 1 of McCallum for the purpose of, among other things, having switch circuits that are capable of withstanding high voltage and have low noise/ripple associated with the operation of the switches. With respect to claim 9, Vinciarelli discloses, a power driver circuit (Q1 with Q2 and Q3 with Q4) that is included in a voltage regulator (Fig. 1). Vinciarelli fails to disclose how Q1-Q4 are constructed and fails to disclose the power driver of claim 1. However, McCallum discloses the circuit as recited in claim 1 (see above rejection). Furthermore, the circuit of McCallum is designed to withstand high voltages and have a low noise/ripple (see Col. 2 lines 46-48 and Col. 5 lines 34-51). It would have been obvious to replace the generic switches/power drivers of Vinciarelli with the specific switch of Fig. 1 of McCallum for the purpose of, among other things, having switch circuits that are capable of withstanding high voltage and have low noise/ripple associated with the operation of the switches. With respect to claim 10, the power driver circuit of claim 9, wherein the voltage regulator circuit is a buck voltage regulator circuit (when operating in the buck mode, i.e., reducing the voltage levels, of Vinciarelli the circuit operates as a buck regulator) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 2-7 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 07-43-01 AIA Claim s 13-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action. Claim 13 is indicated allowable according to Examiner’s assumption that the recitation of “a supply voltage terminal” on line 16 refers to the same supply voltage terminal as the recitation of “a supply voltage terminal” on line 3. If Examiner’s assumption is incorrect further search and/or consideration will be required to determine patentability. With respect to claims 13-20, no cited art discloses the a voltage regulator comprising a “a gate drive circuit having a supply input terminal and a gate drive output, wherein the supply input terminal is couple to a voltage supply terminal”, a first transistor, an input voltage terminal, a first control terminal, an intermediate terminal, a second transistor, a switching terminal, a second control terminal, a first diode, a resistor, a first voltage clamp circuit, a second voltage clamp circuit, wherein all of the above elements are connected and operative as recited in claim 13 and further including “a second diode coupled between the first control terminal and” [the] “voltage supply terminal”. No cited art discloses all of the above elements connected and operative as claimed and wherein both the supplying input terminal of the gate drive is connected to the supply voltage terminal and the second diode is coupled between the first control terminal and the supply voltage terminal. For instance, McCallum, fails to disclose the gate driver having a supply input terminal connected to the “voltage supply terminal” that is also connected to the second diode that is connected and operative as claimed and further having a gate drive output that is different than the “voltage supply terminal”. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836 Application/Control Number: 19/275,153 Page 2 Art Unit: 2836
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