DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the application filed 01 July 2025.
Claims 1-20 are pending and have been presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation “2tCK interval” without defining the variable “t” or defining the acronym “CK”.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 9, 10, 14 and 17 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 and 5-7 of U.S. Patent No. 12,367,132. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are anticipated by the claims of the ‘132 patent as shown below.
12,367,132
19/275,389
1. A memory device comprising:
(A) memory comprised of a bank area and a channel area; and
(B) control circuitry configured to: receive a command to access the memory; and responsive to receiving the command to access the memory:
(C) provide a bank control path and a channel control path; provide a bank strobe signal over the bank control path for accessing the memory in the bank area; and provide at least two channel strobe signals over the channel control path for accessing the memory in the channel area;
(E) wherein the bank control path comprises disable circuitry configured to selectively disable one or more bank strobe signals.
2. The memory device of claim 1,
(D) wherein a channel strobe signal of the at least two channel strobe signals processes a smaller amount of data than that processed by the bank strobe signal.
5. The memory device of claim 1,
(E) wherein the disable circuitry is configured to disable one bank strobe signal for every other channel strobe signal provided.
9. A memory system comprising:
(A) a memory device including bank and channel areas;
(B C) bank control circuitry configured to generate bank strobe signals,
(D) wherein the memory device is configured to transfer a first number of bits of data in coordination with each bank strobe signal;
(B C) channel control circuitry configured to generate channel strobe signals,
(D) wherein the memory device is configured to transfer a second number of bits of data in coordination with each channel strobe signal; and
(E) coordination logic circuitry configured to disable alternate ones of the bank strobe signals to maintain a specified timing ratio between active bank strobe signals and channel strobe signals.
Claims 3/6&7
Claims 10/14
1. A memory device comprising: memory comprised of a bank area and a channel area; and
(A) control circuitry configured to: receive a command to access the memory; and responsive to receiving the command to access the memory:
(B) provide a bank control path and a channel control path; provide a bank strobe signal over the bank control path for accessing the memory in the bank area; and provide at least two channel strobe signals over the channel control path for accessing the memory in the channel area;
(D) wherein the bank control path comprises disable circuitry configured to selectively disable one or more bank strobe signals.
2. The memory device of claim 1,
(C) wherein a channel strobe signal of the at least two channel strobe signals processes a smaller amount of data than that processed by the bank strobe signal.
5. The memory device of claim 1,
(D) wherein the disable circuitry is configured to disable one bank strobe signal for every other channel strobe signal provided.
17. An apparatus comprising:
(A B) bank control circuitry configured to generate bank strobe signals for memory banks of a memory device,
(C) wherein the memory device is configured to control transfer of a first number of bits of data in coordination with the bank strobe signals;
(A B) channel control circuitry configured to generate channel strobe signals for channels of the memory device,
(C) wherein the memory device is configured to control transfer of a second number of bits of data in coordination with the channel strobe signals; and
(D) coordination logic circuitry configured to selectively disable alternate ones of the bank strobe signals to maintain a specified timing ratio between the bank strobe signals and channel strobe signals.
Allowable Subject Matter
Claims 1-8 are allowed.
Claims 11-13, 15, 16 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1: the limitations of claim 1 are distinct from the claims of the 12,367,132 patent. The ‘132 patent claims do not anticipate, or render obvious, the limitation of “… coordinating timing between the maintained first bank strobe signal and the first and second channel strobe signals to synchronize data output from the memory device.” Claims 9 and 14 are rejected on the grounds of nonstatutory double patenting because those claims refer to the timing between the disabled bank strobe signals. This limitation is anticipated by the ‘132 patent as shown above.
Claims 1, 9 and 14 are allowable over the prior art of record for the same reasons as the parent case was allowable. The art of record fails to disclose the combination of multiple bank signals, multiple channels signals, a difference in the amount of data transferred by the bank and channels signals, and disabling certain bank signals as claimed.
The closest art of record is WOO [2024/0211420]. WOO discloses a memory with a bank and channel area, control circuitry to access the memory using the bank and channel paths and providing a bank and channel strobe. [0012]-[0029] WOO fails to disclose disabling bank strobe signals as claimed or maintaining a specified timing between disabled/maintained bank strobe signals and channel strobe signals.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD J DUDEK JR whose telephone number is (571)270-1030. The examiner can normally be reached Monday - Friday, 8:00A-4:00P.
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/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2132