Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
As per the instant application having Application No. 19/275,605, the amendment filed on 6/24/2026 is herein acknowledged. Claims 1, 11-16 and 19-24 have been amended.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(C), the applicant’s submission of the Information Disclosure Statement(s) dated 6/24/2026 is/are acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy (copies) of the PTOL-1449(s) initialed and dated by the examiner is/are attached to the instant office action.
REJECTIONS BASED ON PRIOR ART
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Note that (MPEP 804.0 (I.B.1)) states: A complete response to a nonstatutory double patenting (NDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional.
As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. Therefore, an application must not be allowed unless the required compliant terminal disclaimer(s) is/are filed and/or the withdrawal of the nonstatutory double patenting rejection(s) is made of record by the examiner. See MPEP § 804.02, subsection VI, for filing terminal disclaimers required to overcome nonstatutory double patenting rejections in applications filed on or after June 8, 1995.
Claims 1-12 and 15-24 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-20 of US 12393355 (corresponding to US Application No. 18/223249) in view of Kim et al. (US 2023/0205428). Although the conflicting claims are not identical, they are not patentably distinct from each other because the claims in the patent in view of Kim disclose/obviate the subject matter of the claims in the instant application.
Claims of the instant application are compared to claims of the patent in the following table:
Instant Application
US 12393355 (corresponding to US Application No. 18/223249)
1. An apparatus, comprising: a plurality of memories; and
a single integrated circuit (IC) that is configured to (a) buffer signals received from the host device for the plurality of memories and (b) be coupled to a host device by a host bus and that is coupled to the plurality of memories by a memory bus, wherein the IC comprises:
a logic buffer module that is configured to monitor a status of the plurality of memories, and
a power management integrated circuit (PMIC) module that is configured to convert a supply voltage to one or more output voltages for use by the plurality of memories, wherein the PMIC module is coupled to the logic buffer module and is further configured, based at least in part on the monitored status of the plurality of memories, to enable a dynamic supply voltage scaling for the plurality of memories.
2. The apparatus of claim 1, wherein the logic buffer module is further configured to buffer data signals between the host device and the plurality of memories.
3. The apparatus of claim 1, wherein the logic buffer module is further configured to buffer command signals and/or address signals between the host device and the plurality of memories.
4. The apparatus of claim 1, wherein the logic
buffer module is further configured to buffer clock signals between the host device and the plurality of memories.
5. The apparatus of claim 1, wherein the plurality of memories comprises double data rate synchronous dynamic random-access memories.
6. The apparatus of claim 1, wherein the PMIC module is further configured to enable threshold voltage protection, programmable power on sequence, and/or power management to the plurality of memories.
7. The apparatus of claim 1, wherein the PMIC module is further configured to regulate voltage and/or monitor current provided to the plurality of memories.
8. The apparatus of claim 1, wherein the single IC further comprises a serial presence detect (SPD) hub that is configured to control plane communication between components of the IC and the host device, and to decouple load from the host device to the plurality of memories.
9. The apparatus of claim 1, wherein the single IC further comprises a temperature control module and/or a security logic module.
10. The apparatus of claim 1, wherein the single IC is configured to support multi-level signaling between the host device and the plurality of memories.
11. The apparatus of claim 1, wherein the single IC is configured to support various buffering operations including First-In-First-Out (FIFO), Last-In-First-Out (LIFO), and/or out-of- order execution.
12. The apparatus of claim 1, wherein the logic buffer module of the single IC permits configurability of memory bus width and clock speed.
15. A memory system, comprising: a host device; and a memory module configured to be coupled to the host device via a host bus, the memory module including:
a first plurality of memory devices, and a first single integrated circuit (IC) coupled to the first plurality of memory devices by a first memory bus, wherein the first single IC comprises:
a first logic buffer module that is configured to (a) buffer signals received from the host device for the plurality of memories and (b) monitor a status of the first plurality of memory devices, and
a first power management integrated circuit (PMIC) module that is configured to convert a supply voltage to one or more output voltages for use by the plurality of memories, wherein the PMIC module is configured, based at least in part on the monitored status of the first plurality of memory devices, to enable a first dynamic supply voltage for the first plurality of memory devices.
16. The memory system of claim 15, wherein the memory module further comprises: a second plurality of memory devices, and a second single IC coupled to the second plurality of memory devices by a second memory bus, wherein the second single IC comprises: a second logic buffer module that is configured to monitor a status of the second plurality of memory devices, and a second PMIC module configured, based at least in part on the monitored status of the second plurality of memory devices, to enable a second dynamic supply voltage scaling for the second plurality of memory devices.
17. The memory system of claim 16, wherein each of the first and second single ICs further comprises a temperature control module and/or a security logic module.
18. The memory system of claim 16, wherein each of the first and second single ICs further comprises a serial presence detect (SPD) hub that is configured to control plane communication between components of the IC and the host device, and to decouple load from the host device to the memory module.
19. The memory system of claim 16, wherein each of the first and second PMIC modules is configured to enable threshold voltage protection, programmable power on sequence, and/or power management to the first and second plurality of memory devices, respectively.
20. An integrated circuit (IC), comprising: a logic buffer module that is configured to (a) buffer signals received from a host device for one or more corresponding memory channels coupled to a plurality of memory devices in a memory module and (b) monitor a status of the plurality of memory devices in the memory module; and
a power management integrated circuit (PMIC) module that is configured to convert a supply voltage to one or more output voltages for use by the plurality of memory devices, wherein the PMIC module is further configured to selectively enable a dynamic supply voltage scaling for the memory module, wherein the IC is configured to be disposed in the memory module.
21. The integrated circuit of claim 20, wherein the PMIC is configured to selectively enable the dynamic supply voltage scaling for the memory module based at least in part on the monitored status of the memory module.
22. The integrated circuit of claim 20, wherein the PMIC is further configured to regulate voltage and monitor current provided to the one or more memory channels.
23. The integrated circuit of claim 20, wherein the signals between the host device and the one or more corresponding memory channels of the memory module include data signals, command signals, address signals, and/or clock signals.
24. The integrated circuit of claim 20, further comprises a serial presence detect (SPD) hub that is configured to control plane communication between components of the IC and the host device, and to decouple load from the host device to the corresponding one or more memory channels of the memory module.
1. An apparatus, comprising: a plurality of memories; and
a single integrated circuit (IC) that is configured to be coupled to a host device by a host bus and that is coupled to the plurality of memories by a memory bus, wherein the IC comprises:
a logic buffer module that is configured to buffer data signals, command signals, address signals, and clock signals between the host device and the plurality of memories and to monitor a status of the plurality of memories, and
a power management integrated circuit (PMIC) module that is coupled with the logic buffer module, wherein the PMIC is configured, based on the monitored status of the plurality of memories, to enable a dynamic supply voltage scaling for the plurality of memories.
See obviousness rationale below
See claim 1
See claim 1
See claim 1
2. The apparatus of claim 1, wherein the plurality of memories comprises double data rate synchronous dynamic random-access memories.
3. The apparatus of claim 1, wherein the PMIC module is further configured to enable threshold voltage protection, programmable power on sequence, or power management to the plurality of memories.
4. The apparatus of claim 1, wherein the PMIC module is further configured to regulate voltage and monitor current provided to the plurality of memories.
5. The apparatus of claim 1, wherein the single IC further comprises a serial presence detect (SPD) hub that is configured to control plane communication between components of the IC and the host device, and to decouple load from the host device to the plurality of memories.
6. The apparatus of claim 1, wherein the single IC further comprises a temperature control module.
7. The apparatus of claim 1, wherein the single IC further comprises a security logic module.
8. The apparatus of claim 1, wherein the single IC is configured to support multi-level signaling between the host device and the plurality of memories.
9. The apparatus of claim 1, wherein the single IC is configured to support various buffering operations including Fist-In-First-Out (FIFO), Last-In-First-Out (LIFO), or out-of-order execution.
10. The apparatus of claim 1, wherein the logic buffer of the single IC permits configurability of memory bus width and clock speed.
11. A memory system, comprising: a host device; a memory module including:
a first plurality of memory devices, and a first single integrated circuit (IC) coupled to the first plurality of memory devices by a first memory bus, wherein the first single IC comprises:
a first logic buffer module that is configured to buffer data signals, command signals, address signals, and clock signals between the host device and the first plurality of memory devices and to monitor a status of the first plurality of memories, and
a first power management integrated circuit (PMIC) module that is coupled with the first logic buffer module, wherein the first PMIC is configured, based on the monitored status of the first plurality of memory devices, to enable a first dynamic supply voltage scaling for the first plurality of memory devices; and a host bus that is configured to couple the host device and the memory module.
See obviousness rationale below
12. The memory system of claim 11, wherein the memory module further comprises: a second plurality of memory devices, and a second single IC coupled to the second plurality of memory devices by a second memory bus, wherein the second single IC comprises: a second logic buffer module that is configured to buffer data signals, command signals, address signals, and clock signals between the host device and the second plurality of memory devices and to monitor a status of the second plurality of memories, and a second PMIC module that is coupled with the second logic buffer module, wherein the second PMIC is configured, based on the monitored status of the second plurality of memory devices, to enable a second dynamic supply voltage scaling for the second plurality of memory devices.
13. The memory system of claim 12, wherein each of the first and second single ICs further comprises a temperature control module.
14. The memory system of claim 12, wherein each of the first and second single ICs further comprises a serial presence detect (SPD) hub that is configured to control plane communication between components of the IC and the host device, and to decouple load from the host device to the memory module.
15. The memory system of claim 12, wherein each of the first and second single ICs further comprises a security logic module.
16. The memory system of claim 12, wherein the PMIC module of each of the first and second single ICs is configured to enable threshold voltage protection, programmable power on sequence, or power management to the first and second plurality of memory devices, respectively.
17. The memory system of claim 11, wherein the memory module comprises double data rate synchronous dynamic random-access memories.
18. An integrated circuit (IC), comprising: a logic buffer module that is configured to buffer data signals, command signals, address signals, and clock signals between a host device and one or more corresponding memory channels of a memory module and to monitor a status of the memory module;
a power management integrated circuit (PMIC) module that is coupled with the logic buffer module, wherein the PMIC is configured, based on the monitored status of the memory module, to enable a dynamic supply voltage scaling for the memory module; memory bus terminals that are configured to be coupled to the one or more memory channels; and host bus terminals that are configured to be coupled to the host device.
See claim 18
See claim 4
See claim 18
19. The integrated circuit of claim 18, further comprises a serial presence detect (SPD) hub that is configured to control plane communication between components of the IC and the host device, and to decouple load from the host device to the corresponding one or more memory channels of the memory module.
20. The integrated circuit of claim 18, further comprising a temperature control module and a security logic module.
The patent does not expressly disclose configured to convert a supply voltage to one or more output voltages for use by the plurality of memories,… wherein the IC is configured to be disposed in the memory module; however, regarding these limitations, Kim teaches [“[0076] The PMIC chip 170 may generate a power supply voltage based on an input voltage and provide the generated power supply voltage to the memory chips 110 to 117, 210 to 217, 131, 132 141, 142, 151 and 152. The memory chips 110 to 117, 210 to 217, 131, 132, 141, 142, 151, and 152 may operate based on a power supply voltage.” Where the SPD, PMIC and RCD of Kim are configured to be disposed in the memory modules as show in in fig. 5 and related text].
It would have been obvious to a person of ordinary skill in the art to modify the patent to have the PMIC configured to convert a supply voltage to one or more output voltages for use by the plurality of memories wherein the IC is configured to be disposed in the memory module as taught by Kim since doing so would provide the benefits of facilitating power management as well as flexibility of design, thus providing efficient accesses to the memory devices.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
Yun et al. (US 20210318705) teaches “A power management integrated circuit (PMIC) includes a voltage regulator, a monitoring circuit, and a count register. The voltage regulator is configured to generate an output voltage. The monitoring circuit is configured to receive a feedback voltage of the output voltage, and to determine at each of periodic intervals whether the feedback voltage is outside a threshold voltage range. The count register is configured to store a count value indicative of a number of times the feedback voltage is determined by the monitoring circuit to be outside the threshold voltage range.” (Abstract).
ACKNOWLEDGEMENT OF ISSUES RAISED BY APPLICANT
Response to Amendment
Applicant’s arguments filed on 6/24/2026 with respect to the double patenting rejections of claims 1-12 and 15-24 have been fully considered; however, these arguments are moot in view of new grounds of rejection over obviousness type double patenting (see above).
In view of the amendments presented on 6/24/2026, the double patenting rejection of claims 13-14 have been withdrawn.
In view of the amendments presented on 6/24/2026 and Applicant’s arguments (which are deemed persuasive), the 35 USC 103 rejections of claims 1-24 are herein withdrawn.
CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
a. STATUS OF CLAIMS IN THE APPLICATION
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-12 and 15-24 have received an action on the merits and are subject to a final rejection.
a(2) ALLOWABLE SUBJECT MATTER
Claims 13 and 14 are objected as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
Note that claims 1-12 and 15-24 would be allowable if the double patenting rejections above are overcome.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAIMA RIGOL whose telephone number is (571)272-1232. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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September 8, 2026
/YAIMA RIGOL/
Primary Examiner, Art Unit 2135
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