Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending.
Information Disclosure Statement
The references cited in the information disclosure statement (IDS) submitted on 10/24/25, 12/19/25, 3/26/26,4/26/26, and 7/2/26 have been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The title is meant to have an “informative value in indexing, classifying, searching”. See MPEP606.01.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No.12386737. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the instant claims are found within the claims of the issued patent.
Instant Application
US Patent 12386737
1. A memory system, including: a memory device; and a memory controller
comprising a second interface communicated with a host,
coupled with the memory device and configured to: receive, through the second interface, an identifier indicating a peak power capability supported by the host, and control, an operating power of the memory system to match the peak power capability according to the identifier,
wherein the peak power capability is greater than the operating power of the memory device, and the identifier comprises at least one of: a first identifier representing a first current magnitude that the host is capable of providing to the memory device, or a second identifier representing a second current magnitude that the host is capable of providing to the memory controller.
1. A memory system, including: a memory device coupled with a host; a memory controller comprising a second interface communicated with a first interface of the host, coupled with the memory device and configured to: receive, through the second interface from the first interface of the host, an identifier indicating a peak power capability supported by of the host, and determine a peak power management policy matches the peak power capability according to the identifier; wherein the peak power capability is greater than an operating power of the memory device, and the identifier comprises at least one of: a first identifier representing a first current magnitude that a power management unit of the host is capable of providing to the memory device at a first voltage, and a second identifier representing a second current magnitude that the power management unit of the host is capable of providing to the memory controller at a second voltage.
8. An electronic device, including: a host comprising: a first interface configured to send an identifier indicating a peak power capability; and a memory system couple with the host, comprising: a memory device; and a memory controller comprising a second interface configured to receive the identifier from the first interface of the host, and configured to a control an operating power of the memory system to match the peak power capability according to the identifier, wherein the peak power capability is greater than the operating power of the memory device, and the identifier comprises at least one of: a first identifier representing a first current magnitude that the host is capable of providing to the memory device, or a second identifier representing a second current magnitude that the host is capable of providing to the memory controller.
11. An electronic device, including: a host comprising: a power management unit, and a first interface configured to send an identifier indicating a peak power capability supported by the power management unit; and a memory system comprising: a memory device, and a memory controller comprising a second interface communicated with a first interface of the host, coupled between the memory device and the host, and configured to determine a peak power management policy matches the peak power capability according to the identifier; wherein the peak power capability is greater than an operating power of the memory device, and the identifier comprises at least one of: a first identifier representing a first current magnitude that a power management unit of the host is capable of providing to the memory device at a first voltage, and a second identifier representing a second current magnitude that the power management unit of the host is capable of providing to the memory controller at a second voltage.
15. A power controlling method, comprising: receiving, an identifier indicating a peak power capability supported by a host; and controlling, an operating power of a memory system to match the peak power capability according to the identifier, wherein the peak power capability is greater than the operating power of a memory device in the memory system; and the identifier comprises at least one of:
a first identifier representing a first current magnitude that the host is capable of providing to the memory device, or a second identifier representing a second current magnitude that the host is capable of providing to the memory controller.
16. A power controlling method, comprising: sending, through a first interface of a host, an identifier indicating a peak power capability supported by the host; receiving, by a second interface in a memory controller of a memory system communicated with the first interface, the identifier; determining, by the memory controller, a peak power management policy matches the peak power capability according to the identifier; and applying, by the memory controller, the peak power management policy to control the memory system; wherein the peak power capability is greater than an operating power of a memory device in the memory system, and the identifier comprises at least one of: a first identifier representing a first current magnitude that a power management unit of the host is capable of providing to the memory device at a first voltage, and a second identifier representing a second current magnitude that the power management unit of the host is capable of providing to the memory controller at a second voltage.
Conclusion
The prior art made of record , listed on form PTO-892, and not relied upon, if any, is considered pertinent to applicant's disclosure.
Chung et. Al. US20230058022 teaches storing peak power information.
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TASNIMA . MATIN
Primary Examiner
Art Unit 2135
/TASNIMA MATIN/Primary Examiner, Art Unit 2135
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