DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in reply to an application filed on July 22, 2023 regarding Application No. 19/277,001. Claims 1-16 are pending.
Priority
Acknowledgment is made of Applicants’ claim for foreign priority under 35 U.S.C. 119(a)-(d). A certified copy of the KR 10-2024-0096568 application filed in Korea on July 22, 2024 has been filed.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 22, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Office. Please note that the Office has included the application number and art unit number on the IDS.
Claim Objections
Claims 1-16 are objected to for the reasons discussed below.
Claim 1: “a driving current” (2nd to the last line) should be changed to “[[a]]the driving current” since the term was previously recited.
Claim 9: “the OBS signal line” (3rd to the last line) should be changed to “[[the]]an on-bias stress (OBS) signal line” since the term was not previously recited.
Also, “an on-bias stress (OBS) voltage line” (2nd to the last line) should be changed to “an [[on-bias stress (OBS)]]OBS voltage line” since “OBS” was previously recited.
Claim 11: “the second capacitor” (l. 1) should be changed to “[[the]]a second capacitor” since the term was not previously recited. Alternatively, the claim dependency may need to be changed to depend from claim 10. For purposes of examination, the claim language is interpreted as discussed in the rejections.
Also, “the initialization power supply” (l. 2) should be changed to “[[the]]an initialization power supply” since the term was not previously recited. Alternatively, the claim dependency may need to be changed to depend from claim 10. For purposes of examination, the claim language is interpreted as discussed in the rejections.
Claim 14: “the emission period” (last line) should be changed to “[[the]]an emission period” since the term was not previously recited.
Claim 15: “applying the initialization voltage to the gate node of the driving transistor and a drain node of the driving transistor” (ll. 8-9) may need to be changed to “applying the initialization voltage to [[the gate node of the driving transistor and ]]a drain node of the driving transistor” since “applying… to the gate node of the driving transistor” was previously recited.
Also, “applying an OBS voltage to the source node of the driving transistor” (l. 11) should be deleted since the claim language was previously recited.
Claims 2-14 and 16: each of these claims depends from an objected to claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicants are advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in US 2023/0162664 A1 (hereinafter Kim) in view of Zhang et al. in US 2017/0018229 A1 (hereinafter Zhang).
Regarding claim 1, Kim teaches:
A display device (1000 in FIG. 1) comprising (Kim: FIG. 1 and “[0062] Referring to FIG. 1, the display device 1000 may include a pixel portion 100, a scan driver 200, [and] an emission driver 300….”):
a display panel (100) comprising a pixel (PX) configured to display an image (Kim: FIG. 1, “[0062] Referring to FIG. 1, the display device 1000 may include a pixel portion 100….”, and “[0063] The display device 1000 may display an image at various frame frequencies…. The frame frequency is a frequency at which a data voltage is substantially written to a driving transistor of a pixel PX for one second….”, see also FIG. 3, [0066], and [0085]); and
a driver (200 and 300) configured to drive the display panel (Kim: FIG. 1, “[0066] The pixel portion 100 may include scan lines S11 to S1n, S21 to S2n, S31 to S3n, and S41 to S4n,… and include pixels PX connected to the scan lines S11 to S1n, S21 to S2n, S31 to S3n, and S41 to S4n….”, “[0069] The scan driver 200 may receive the first control signal SCS from the timing controller 500, and supply a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal respectively to first scan lines S11 to S1n, second scan lines S21 to S2n, third scan lines S31 to S3n, and fourth scan lines S41 to S4n, based on the first control signal SCS.”, and “[0073] The emission driver 300 may supply an emission control signal to the emission control lines E1 to En, based on the second control signal ECS….”, see also “[0075] For convenience of description, a case where each of the scan driver 200 and the emission driver 300 is a single component has been illustrated in FIG. 1, but embodiments of the present disclosure are not limited thereto…. [A]t least a portion of the scan driver 200 and the emission driver 300 may be integrated as one driving circuit, one module, etc.”),
wherein the pixel comprises:
a light emitting element (LD in FIG. 3) (Kim: FIG. 3, “[0085] FIG. 3 is a circuit diagram illustrating an example of the pixel included in the display device shown in FIG. 1”, and “[0087] Referring to FIGS. 1 and 3, the pixel 10 may include a light emitting element LD….”);
a driving transistor (M1) configured to generate a driving current to be supplied to the light emitting element (Kim: FIG. 3, “[0088]… The light emitting element LD may generate light with a predetermined luminance corresponding to an amount of current supplied from the first transistor M1.”, and “[0090]… [T]he first transistor M1 (or driving transistor)….”);
a first capacitor (Cst) having a first electrode (Cst lower electrode) connected to a gate node of the driving transistor and a second electrode (Cst upper electrode) connected to a high-potential voltage line (PL1(VDD) line) (Kim: FIG. 3, “[0090]… A gate electrode of the first transistor M1 may be connected to a third node N3….”, “[0091]… [T]he first driving power source VDD may be set to a voltage higher than that of the second driving power source VSS.”, and “[0109] The storage capacitor Cst may be connected between the first power line PL1 and the third node N3. The storage capacitor Cst may store a voltage applied to the third node N3.”, see also [0097]).
However, it is noted that Kim does not teach:
the pixel is a subpixel,
but which would have been obvious to include, such that Kim as modified teaches: a display panel comprising a subpixel configured to display an image, wherein the subpixel comprises:, since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to provide image display.
However, it is noted that Kim as modified does not teach:
a stabilization unit configured to maintain a constant voltage between the gate node and a source node of the driving transistor when the driving transistor generates a driving current according to a voltage of the first capacitor.
Zhang teaches:
a stabilization unit (C2 and TFT3 in Fig. 3) configured to maintain a constant voltage between a gate node and a source node (DTFT upper node) of a driving transistor (DTFT) when the driving transistor generates a driving current according to a voltage of a first capacitor (C1) (Zhang: Figs. 3-4, “[0059]…. In the embodiments of the present invention,… the source is called a first electrode….”, “[0075] As shown in FIG. 3,… the voltage stabilizing unit comprises a third transistor TFT3 and a second storage capacitor C2…. [T]he first electrode of the driving transistor DTFT is connected with the second electrode of the second transistor TFT2, the second electrode of the driving transistor DTFT is connected with the light-emitting unit, and a control electrode of the driving transistor DTFT is connected with the first node A.”, “[0080] In the light emission for display stage,… the light emission control signal is inputted into the first control signal line [S1],… because the data signal in the previous stage and the threshold voltage stored in the first capacitor C1 in the previous stage are written to the control electrode of the driving transistor DTFT, the voltage of the control electrode of the driving transistor DTFT is higher than the threshold voltage of the driving transistor DTFT, so that the driving transistor DTFT is turned on, and a high level signal is inputted into the first voltage terminal ELVdd, so that the organic light-emitting diode OLED is driven to emit light, thereby achieving display. At this moment, a current IOLED flowing through the organic light-emitting diode OLED satisfies IOLED=k(VA−VB−Vth)2=kα(VDATA−V0)2, where, VDATA is the data voltage written to the data signal line DATA, α is a constant related to the first storage capacitor C1, k is a constant related to characteristics of the driving transistor DTFT, and V0 is the reference voltage provided by the data signal line DATA in the reset stage and the threshold acquisition stage.”, and [0081] (including: “In the voltage stabilization stage, the voltage stabilization control signal is inputted into the second control signal line [S2], so that the third transistor TFT3 is turned on, a high level is applied to the first voltage terminal ELVdd, and the potential at the first node A is stabilized through the second storage capacitor C2….”), see also Fig. 2).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Zhang, such that Kim as modified teaches: a stabilization unit configured to maintain a constant voltage between the gate node and a source node of the driving transistor when the driving transistor generates a driving current according to a voltage of the first capacitor (gate node and source node (M1 upper node; FIG. 3, “[0090] A first electrode of the first transistor M1 (or driving transistor) may be connected to a first node N1….”, and “[0096]… [T]he first electrode (e.g., a source electrode) of the first transistor M1….”), driving transistor, and first capacitor of Kim combined with the stabilization unit configured as taught by Zhang), to avoid flicker. (Zhang: “[0081]… As a result [of stabilizing the potential at the first node A], flicker due to difference between brightness of the organic light-emitting diode OLED which happens when a gate voltage of the driving transistor DTFT is changed because of electric leakage of the first transistor TFT1 and a change of the data signal can be avoided.”).
Regarding claim 7, Kim as modified by Zhang teaches:
The display device according to claim 1, wherein the subpixel further comprises:
a first switching transistor (M3 in FIG. 3 of Kim) having a gate electrode connected to a first scan line (S2i), a first electrode (M3 right/N2 electrode) connected to a drain node (M1 lower/N2 node) of the driving transistor, and a second electrode (M3 left/N3 electrode) connected to the gate node of the driving transistor (Kim: FIG. 3, “[0090]… [A] second electrode of the first transistor M1 may be connected to a second node N2. A gate electrode of the first transistor M1 may be connected to a third node N3….”, and “[0093] The third transistor M3 may be connected between the second electrode of the first transistor M1 (e.g., the second node N2) and the third node N3. A gate electrode of the third transistor M3 may be connected to an ith second scan line S2i…. [T]he second electrode (e.g., a drain electrode) of the first transistor M1….”); and
a second switching transistor (M2) having a gate electrode connected to a second scan line (S4i), a first electrode (M2 left electrode) connected to a data line (Dj), and a second electrode (M2 right/N1 electrode) connected to the source node (M1 upper/N1 node) of the driving transistor (Kim: FIG. 3, “[0090] A first electrode of the first transistor M1 (or driving transistor) may be connected to a first node N1…”, “[0092] The second transistor M2 may be connected between the jth data line Dj… and the first node N1. A gate electrode of the second transistor M2 may be connected to an ith fourth scan line S4i….”, and “[0096]… [T]he first electrode (e.g., a source electrode) of the first transistor M1….”).
Regarding claim 8, Kim as modified by Zhang teaches:
The display device according to claim 7, wherein the subpixel further comprises:
a third switching transistor (M5 in FIG. 3 of Kim) having a gate electrode connected to a light emitting signal line (Ei), a first electrode (M5 upper electrode) connected to the high-potential voltage line, and a second electrode (M5 lower/N1 electrode) connected to the source node of the driving transistor (Kim: FIG. 3 and “[0097] The fifth transistor M5 may be connected between a first power line PL1 through which the first driving power source VDD is provided and the first node N1. A gate electrode of the fifth transistor M5 may be connected to an ith emission control line Ei….”, see also [0090] and [0096]); and
a fourth switching transistor (M6) having a gate electrode connected to the light emitting signal line, a first electrode (M6 upper/N2 electrode) connected to the drain node of the driving transistor, and a second electrode (M6 lower/N4 electrode) connected to an anode (LD upper/N4) of the light emitting element (Kim: FIG. 3, “[0088] A first electrode (anode electrode…) of the light emitting element LD may be connected to the sixth transistor M6….”, and “[0098] The sixth transistor M6 may be connected between the second electrode of the first transistor M1 (e.g., the second node N2) and the first electrode of the light emitting element LD (e.g., a fourth node N4). A gate electrode of the sixth transistor M6 may be connected to the emission control line Ei….”, see also [0090] and [0093]).
Regarding claim 9, Kim as modified by Zhang teaches:
The display device according to claim 8, wherein the subpixel further comprises:
a fifth switching transistor (M7 in FIG. 3 of Kim) having a gate electrode connected to a fourth scan signal line (S3i), a first electrode (M7 lower electrode) connected to a first initialization voltage line (PL3), and a second electrode (M7 upper/N3 electrode) connected to the first capacitor (Kim: FIG. 3 and “[0099] The seventh transistor M7 may be connected between the third node N3 and a third power line PL3 through which the second power source Vint1 (hereinafter, referred to as a first initialization power source) is provided. A gate electrode of the seventh transistor M7 may be connected to an ith third scan line S3i….”, see also [0109]);
a sixth switching transistor (M8) having a gate electrode connected to a third scan line (S1i), a first electrode (M8 left electrode) connected to an input line (PL4) of an anode reset voltage (Vint2), and a second electrode (M8 right/N4 electrode) connected to the anode of the light emitting element (Kim: FIG. 3, “[0102] The eighth transistor M8 may be connected between the first electrode of the light emitting element LD (e.g., the fourth node N4) and a fourth power line PL4 through which the third power source Vint2 (hereinafter, referred to as a second initialization power source) is provided. In an embodiment, a gate electrode of the eighth transistor M8 may be connected to the first scan line S1i.”, “[0103] The eighth transistor M8 may be turned on when the first scan signal is supplied to the first scan line S1i, to supply the voltage of the second initialization power source Vint2 to the first electrode of the light emitting element LD.”, and “[0104] When the voltage of the second initialization power source Vint2 is supplied to the first electrode of the light emitting element LD, a parasitic capacitor of the light emitting element LD may be discharged. Since a residual voltage charged in the parasitic capacitor is discharged (eliminated), unintended fine emission can be prevented or reduced….”, see also [0088]); and
a seventh switching transistor (M4) having a gate electrode connected to the OBS signal line (S1i), a first electrode (M4 lower electrode) connected to an on-bias stress (OBS) voltage line (PL2), and a second electrode (M4 upper/N1 electrode) connected to the source node of the driving transistor (Kim: FIG. 3, “[0094] The fourth transistor M4 may be connected between the first node N1 and a second power line PL2 through which the voltage of the first power source Vbs is provided. The fourth transistor M4 may be turned on in response to the first scan signal supplied to an ith first scan line S1i….”, “[0117]… The bias scan period BSP may include… a second emission period EP2….”, and “[0130] As shown in FIG. 5, the first scan signal may be supplied to the first scan line S1i in the second non-emission period NEP2 as a non-emission period of the bias scan period BSP. Therefore, the voltage of the first power source Vbs may be supplied to the source electrode of the first transistor M1 in the second non-emission period NEP2. That is, on-bias stress may be… applied to the first transistor M1….”, see also FIG. 5, [0090], and [0096]).
Claims 2, 11-12, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Zhang, in further view of Ouyang et al. in CN 110751927 A (hereinafter Ouyang; an original copy and full machine translation thereof is/was provided with the first Office action mailed in response to the filing of the instant application).
Regarding claim 2, Kim as modified by Zhang teaches:
The display device according to claim 1, wherein:
the driver outputs a scan signal (S1i, S2i, S3i, S4i, or Ei in FIGs. 4-5 of Kim) for controlling driving of the subpixel in an initialization period (P3), a data writing period (P4), and an emission period (EP), outputs an on-bias stress (OBS) signal (Vbs in FIG. 3 of Kim) for controlling an OBS period (NEP2 in FIG. 5 of Kim) of the subpixel, and outputs a control signal (S2 signal in Fig. 3 of Zhang) for controlling an operation of the stabilization unit (Kim: FIGs. 3-5, “[0117]… The bias scan period BSP may include… a second emission period EP2….”, “[0130] As shown in FIG. 5, the first scan signal may be supplied to the first scan line S1i in the second non-emission period NEP2 as a non-emission period of the bias scan period BSP. Therefore, the voltage of the first power source Vbs may be supplied to the source electrode of the first transistor M1 in the second non-emission period NEP2. That is, on-bias stress may be… applied to the first transistor M1….”, “[0148]… [F]from the sixth time t6 to the seventh time t7 of the third period P3 [in FIG. 4], the third scan signal and the second scan signal may overlap each other, and the third transistor M3 and the seventh transistor M7 may simultaneously have the turn-on state. Therefore, the voltage of the first initialization power source Vint1 may be supplied to the second node N2, and a drain voltage of the first transistor M1 may be initialized to the voltage of the first initialization power source Vint1.”, “[0150] In the fourth period P4, the second transistor M2… may be turned on… in response to the fourth scan signal…. Therefore, the data signal supplied to the data line Dj is supplied to the first node N1… so that data writing… can be performed….”, and “[0157]… [T]he emission driver 300 may… supply… the emission control signal to the emission control line Ei in the emission period EP. Accordingly, the fifth and sixth transistors M5 and M6 may be turned on, and a driving current based on the data signal may be supplied to the light emitting element LD through the first transistor M1….”; Zhang: Fig. 3, “[0068]… [A] pixel driving circuit…”, and “[0081] In the voltage stabilization stage, the voltage stabilization control signal is inputted into the second control signal line [S2], so that the third transistor TFT3 is turned on, a high level is applied to the first voltage terminal ELVdd, and the potential at the first node A is stabilized through the second storage capacitor C2….”, see also Figs. 2 and 4; claim 1 above (subpixel)), and
the stabilization unit maintains a constant voltage between the gate node and the source node of the driving transistor during the emission period of the subpixel (Zhang: Figs. 3-4, “[0080] In the light emission for display stage,… the light emission control signal is inputted into the first control signal line S1, the second transistor TFT2 and the driving transistor DTFT are turned on, and a high level is applied to the first voltage terminal ELVdd, so that the organic light-emitting diode OLED is driven to emit light, thereby achieving display….”, and “[0081]… [T]he voltage stabilization control signal is inputted into the second control signal line [S2], that is, the second control signal has a high level, so that the third transistor TFT3 is turned on, the first terminal of the second storage capacitor C2 is connected with the first voltage terminal ELVdd into which a high level signal is inputted, and the potential at the first node A can be stabilized through the second storage capacitor C2…. As a result, flicker due to difference between brightness of the organic light-emitting diode OLED which happens when a gate voltage of the driving transistor DTFT is changed because of electric leakage of the first transistor TFT1 and a change of the data signal can be avoided.”; claim 1 above (subpixel)).
However, it is noted that Kim as modified by Zhang does not teach:
the stabilization unit is initialized in the OBS period of the subpixel according to the control signal of the driver.
Ouyang teaches:
a stabilization unit (40 and Cst in FIG. 1) is initialized in a period of a pixel according to a control signal (Sn-1 signal in FIG. 2) (Ouyang: FIGs. 1-2, p. 5, ¶ 3 (“FIG. 1 is a schematic structural diagram of a pixel driving circuit…”) and last ¶ (“… [I]n the initialization phase, the initialization unit 10 and the voltage stabilization unit 40 are turned on. The initialization unit 10 provides the initialization signal of the initialization signal terminal Vref to the first node N1, and the voltage stabilization unit 40 provides the initialization signal of the first node N1 to the first node N1. The two node N2 is capable of initializing the signal stored in the storage capacitor Cst….”), and p. 6, ¶ 4 (“… As shown in FIG. 2, the control terminal of the initialization unit 10 is electrically connected to the first scanning signal terminal Sn-1…. A scan signal is used to control the initialization unit 10… to be turned on during the initialization phase….”), see also FIGs. 3-8 and p. 5, ¶ 4 (“… [T]he voltage stabilizing unit 40 is electrically connected between the first node N1 and the second node N2; The unit 40 is configured to provide the potential of the first node N1 to the second node N2 during the initialization phase….”)).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Ouyang, such that Kim as modified teaches: the stabilization unit is initialized in the OBS period of the subpixel according to the control signal of the driver, and maintains a constant voltage between the gate node and the source node of the driving transistor during the emission period of the subpixel (stabilization unit, OBS period, subpixel, control signal, driver, and maintains as claimed of Kim as modified combined with the stabilization unit, period, pixel, and control signal of Ouyang; i.e., initialized of Ouyang during the OBS period of Kim as modified, and maintains as taught by Kim as modified), to provide initialization for image display.
Regarding claim 11, Kim as modified by Zhang teaches:
The display device according to claim 9, wherein the second capacitor (C2 in Fig. 3 of Zhang) is connected between the gate node and the source node (DTFT upper node) of the driving transistor (DTFT) during an emission period (Zhang: Fig. 3-4, “[0059]…. In the embodiments of the present invention,… the source is called a first electrode….”, “[0075] As shown in FIG. 3,… the voltage stabilizing unit comprises a third transistor TFT3 and a second storage capacitor C2;... a first electrode of the second transistor TFT2 is connected with a first voltage terminal ELVdd, a second electrode of the second transistor TFT2 is connected with a first electrode of the driving transistor DTFT, and a control electrode of the second transistor TFT2 is connected with the first control signal line S1;… a first electrode of the third transistor TFT3 is connected with a second terminal of the second storage capacitor C2, a second electrode of the third transistor TFT3 is connected with the first node A, and a control electrode of the third transistor TFT3 is connected with the second control signal line; a first terminal of the second storage capacitor C2 is connected with the first voltage terminal ELVdd; and the first electrode of the driving transistor DTFT is connected with the second electrode of the second transistor TFT2, the second electrode of the driving transistor DTFT is connected with the light-emitting unit, and a control electrode of the driving transistor DTFT is connected with the first node A.”, “[0080] In the light emission for display stage,… the light emission control signal is inputted into the first control signal line S1, the second transistor TFT2 and the driving transistor DTFT are turned on, and a high level is applied to the first voltage terminal ELVdd, so that the organic light-emitting diode OLED is driven to emit light, thereby achieving display….”, and “[0081]… [T]he voltage stabilization control signal is inputted into the second control signal line [S2], that is, the second control signal has a high level, so that the third transistor TFT3 is turned on, the first terminal of the second storage capacitor C2 is connected with the first voltage terminal ELVdd into which a high level signal is inputted, and the potential at the first node A can be stabilized through the second storage capacitor C2…. As a result, flicker due to difference between brightness of the organic light-emitting diode OLED which happens when a gate voltage of the driving transistor DTFT is changed because of electric leakage of the first transistor TFT1 and a change of the data signal can be avoided.”).
However, it is noted that Kim as modified by Zhang does not teach:
wherein the second capacitor is initialized by the initialization power supply.
Ouyang teaches:
wherein a second capacitor (Cst in FIG. 1) is initialized by an initialization power supply (Vref power supply) (Ouyang: FIG. 1 and p. 5, last ¶ (“… [I]n the initialization phase, the initialization unit 10 and the voltage stabilization unit 40 are turned on. The initialization unit 10 provides the initialization signal of the initialization signal terminal Vref to the first node N1, and the voltage stabilization unit 40 provides the initialization signal of the first node N1 to the first node N1. The two node N2 is capable of initializing the signal stored in the storage capacitor Cst….”), see also FIGs. 3-8 and p. 5, ¶ 4 (“… [T]he voltage stabilizing unit 40 is electrically connected between the first node N1 and the second node N2; The unit 40 is configured to provide the potential of the first node N1 to the second node N2 during the initialization phase….”)).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Ouyang, such that Kim as modified teaches:
wherein the second capacitor is initialized by the initialization power supply and connected between the gate node and the source node of the driving transistor during an emission period (second capacitor, and connected, as taught by Kim as modified combined with the second capacitor and initialized as taught by Ouyang), to provide initialization for image display.
Regarding claim 12, Kim as modified by Zhang teaches:
The display device according to claim 1, wherein the stabilization unit comprises a second capacitor (C2 in Fig. 3 of Zhang) having a first electrode (C2 lower electrode) connected to the gate node of the driving transistor (Zhang: Fig. 3 and “[0075]… [A] first electrode of the third transistor TFT3 is connected with a second terminal of the second storage capacitor C2, a second electrode of the third transistor TFT3 is connected with the first node A…; and… a control electrode of the driving transistor DTFT is connected with the first node A.”),
wherein the second capacitor is connected between the gate node and the source node of the driving transistor during an emission period of the subpixel (Zhang: Fig. 4, “[0075] As shown in FIG. 3,… the voltage stabilizing unit comprises a third transistor TFT3 and a second storage capacitor C2;... a first electrode of the second transistor TFT2 is connected with a first voltage terminal ELVdd, a second electrode of the second transistor TFT2 is connected with a first electrode of the driving transistor DTFT, and a control electrode of the second transistor TFT2 is connected with the first control signal line S1;… a first electrode of the third transistor TFT3 is connected with a second terminal of the second storage capacitor C2, a second electrode of the third transistor TFT3 is connected with the first node A, and a control electrode of the third transistor TFT3 is connected with the second control signal line; a first terminal of the second storage capacitor C2 is connected with the first voltage terminal ELVdd; and the first electrode of the driving transistor DTFT is connected with the second electrode of the second transistor TFT2, the second electrode of the driving transistor DTFT is connected with the light-emitting unit, and a control electrode of the driving transistor DTFT is connected with the first node A.”, “[0080] In the light emission for display stage,… the light emission control signal is inputted into the first control signal line S1, the second transistor TFT2 and the driving transistor DTFT are turned on, and a high level is applied to the first voltage terminal ELVdd, so that the organic light-emitting diode OLED is driven to emit light, thereby achieving display….”, and “[0081]… [T]he voltage stabilization control signal is inputted into the second control signal line [S2], that is, the second control signal has a high level, so that the third transistor TFT3 is turned on, the first terminal of the second storage capacitor C2 is connected with the first voltage terminal ELVdd into which a high level signal is inputted, and the potential at the first node A can be stabilized through the second storage capacitor C2…. As a result, flicker due to difference between brightness of the organic light-emitting diode OLED which happens when a gate voltage of the driving transistor DTFT is changed because of electric leakage of the first transistor TFT1 and a change of the data signal can be avoided.”; claim 1 above (sub-pixel)).
However, it is noted that Kim as modified by Zhang does not teach:
wherein the second capacitor is initialized by an initialization power supply during an on- bias stress (OBS) period of the subpixel.
Ouyang teaches:
wherein a second capacitor (Cst in FIG. 1) is initialized by an initialization power supply (Vref power supply) during a period of a pixel (Ouyang: FIG. 1 and p. 5, ¶ 3 (“FIG. 1 is a schematic structural diagram of a pixel driving circuit…”) and last ¶ (“… [I]n the initialization phase, the initialization unit 10 and the voltage stabilization unit 40 are turned on. The initialization unit 10 provides the initialization signal of the initialization signal terminal Vref to the first node N1, and the voltage stabilization unit 40 provides the initialization signal of the first node N1 to the first node N1. The two node N2 is capable of initializing the signal stored in the storage capacitor Cst….”), see also FIGs. 3-8 and p. 5, ¶ 4 (“… [T]he voltage stabilizing unit 40 is electrically connected between the first node N1 and the second node N2; The unit 40 is configured to provide the potential of the first node N1 to the second node N2 during the initialization phase….”)).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Ouyang, such that Kim as modified teaches:
wherein the second capacitor is initialized by an initialization power supply during an on-bias stress (OBS) period of the subpixel, and is connected between the gate node and the source node of the driving transistor during an emission period of the subpixel (second capacitor, on-bias stress (OBS) period (NEP2 in FIG. 5; Kim: FIG. 5, “[0117]… The bias scan period BSP may include… a second emission period EP2….”, and “[0130]… [T]he voltage of the first power source Vbs may be supplied to the source electrode of the first transistor M1 in the second non-emission period NEP2. That is, on-bias stress may be… applied to the first transistor M1….”), subpixel, and connected, as taught by Kim as modified combined with the second capacitor and initialized, as taught by Ouyang; i.e., initialized of Ouyang during the on-bias stress period of Kim as modified, and connected as taught by Kim as modified), to provide initialization for image display.
Regarding claim 14, Kim as modified by Zhang is further modified in the same manner and for the same reason set forth in the discussion of claim 2 above. Thus, claim 14 is rejected under similar rationale as claim 2 above.
Regarding claim 15, Kim teaches:
A method of driving a display device (1000 in FIG. 1) comprising a light emitting element (LD in FIG. 3), a driving transistor (M1) configured to generate a driving current to be supplied to the light emitting element, and a first capacitor (Cst) having a first electrode (Cst lower/N3 electrode) connected to a gate node of the driving transistor and a second electrode (Cst upper electrode) connected to a high-potential voltage line (PL1(VDD) line), the method comprising (Kim: FIGs. 1 and 3, “[0002] Embodiments of the present disclosure relate… to… a method of driving the display device.”, “[0062] Referring to FIG. 1, the display device 1000 ….”, “[0085] FIG. 3 is a circuit diagram illustrating an example of the pixel included in the display device shown in FIG. 1”, “[0087] Referring to FIGS. 1 and 3, the pixel 10 may include a light emitting element LD, first transistor[] M1, and a storage capacitor Cst.”, “[0088]… The light emitting element LD may generate light with a predetermined luminance corresponding to an amount of current supplied from the first transistor M1.”, “[0090]… [T]he first transistor M1 (or driving transistor)…. A gate electrode of the first transistor M1 may be connected to a third node N3….”, “[0091]… [T]he first driving power source VDD may be set to a voltage higher than that of the second driving power source VSS.”, and “[0109] The storage capacitor Cst may be connected between the first power line PL1 and the third node N3. The storage capacitor Cst may store a voltage applied to the third node N3.”, see also FIG. 5, [0097], and “[0115]… FIG. 5 is a timing diagram illustrating an example of the signals supplied to the pixel shown in FIG. 3 during one frame period.”):
applying an initialization voltage (Vint1) to the gate node of the driving transistor, applying an on- bias stress (OBS) voltage to a source node (M1 upper/N1 node) of the driving transistor (Kim: FIGs. 3-5, “[0090] A first electrode of the first transistor M1 (or driving transistor) may be connected to a first node N1…. A gate electrode of the first transistor M1 may be connected to a third node N3….”, “[0094] The fourth transistor M4 may be connected between the first node N1 and a second power line PL2 through which the voltage of the first power source Vbs is provided. The fourth transistor M4 may be turned on in response to the first scan signal supplied to an ith first scan line S1i….”, “[0096]… [T]he first electrode (e.g., a source electrode) of the first transistor M1….”, “[0117]… The bias scan period BSP may include… a second emission period EP2….”, “[0130] As shown in FIG. 5, the first scan signal may be supplied to the first scan line S1i in the second non-emission period NEP2 as a non-emission period of the bias scan period BSP. Therefore, the voltage of the first power source Vbs may be supplied to the source electrode of the first transistor M1 in the second non-emission period NEP2. That is, on-bias stress may be… applied to the first transistor M1….”, “[0145] During the third period P3 [in FIG. 4], the seventh transistor M7 may be turned on in response to the third scan signal, and the voltage of the first initialization power source Vint1 may be supplied to the third node N3. Therefore, the gate voltage of the first transistor M1 may be initialized to the voltage of the first initialization power source Vint1….”);
applying the initialization voltage to the gate node of the driving transistor and a drain node (M1 lower/N2 node) of the driving transistor (Kim: FIGs. 3-4, “[0090]… [A] second electrode of the first transistor M1 may be connected to a second node N2. A gate electrode of the first transistor M1 may be connected to a third node N3….”, “[0093]… [T]he second electrode (e.g., a drain electrode) of the first transistor M1….”, “[0145] During the third period P3 [in FIG. 4], the seventh transistor M7 may be turned on in response to the third scan signal, and the voltage of the first initialization power source Vint1 may be supplied to the third node N3. Therefore, the gate voltage of the first transistor M1 may be initialized to the voltage of the first initialization power source Vint1….”, and “[0148]… [F]rom the sixth time t6 to the seventh time t7 of the third period P3, the third scan signal and the second scan signal may overlap each other, and the third transistor M3 and the seventh transistor M7 may simultaneously have the turn-on state. Therefore, the voltage of the first initialization power source Vint1 may be supplied to the second node N2, and a drain voltage of the first transistor M1 may be initialized to the voltage of the first initialization power source Vint1.”);
storing a data voltage (Dj voltage) in the first capacitor (Kim: FIGs. 3-4, “[0109]… The storage capacitor Cst may store a voltage applied to the third node N3.”, and “[0150] In the fourth period P4, the second transistor M2 and the third transistor M3 may be turned on respectively in response to the fourth scan signal and the second scan signal. Therefore, the data signal supplied to the data line Dj is supplied to the first node N1, and the first transistor M1 is diode-connected, so that data writing and compensation of the threshold voltage of the first transistor M1 can be performed. The supply of the second scan signal is maintained even after the supply of the fourth scan signal is suspended, and thus, the threshold voltage of the first transistor M1 can be compensated for a sufficient amount of time.”; also, it would have been obvious to one of ordinary skill in the art to include the claimed features since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to provide data for image display);
applying an OBS voltage (Vbs) to the source node of the driving transistor (Kim: FIG. 3, “[0090] A first electrode of the first transistor M1 (or driving transistor) may be connected to a first node N1….”, “[0094] The fourth transistor M4 may be connected between the first node N1 and a second power line PL2 through which the voltage of the first power source Vbs is provided. The fourth transistor M4 may be turned on in response to the first scan signal supplied to an ith first scan line S1i….”, “[0096]… [T]he first electrode (e.g., a source electrode) of the first transistor M1….”, “[0117]… The bias scan period BSP may include… a second emission period EP2….”, “[0130] As shown in FIG. 5, the first scan signal may be supplied to the first scan line S1i in the second non-emission period NEP2 as a non-emission period of the bias scan period BSP. Therefore, the voltage of the first power source Vbs may be supplied to the source electrode of the first transistor M1 in the second non-emission period NEP2. That is, on-bias stress may be… applied to the first transistor M1….”); and
configuring the light emitting element to emit light based on a driving current generated from the driving transistor according to the data voltage stored in the first capacitor (Kim: FIGs. 3-4, “[0088]… The light emitting element LD may generate light with a predetermined luminance corresponding to an amount of current supplied from the first transistor M1.”, and “[0090]… [T]he first transistor M1 (or driving transistor)….”, “[0109]… The storage capacitor Cst may store a voltage applied to the third node N3.”, “[0157]… [T]he emission driver 300 may… supply… the emission control signal to the emission control line Ei in the emission period EP. Accordingly, the fifth and sixth transistors M5 and M6 may be turned on, and a driving current based on the data signal may be supplied to the light emitting element LD through the first transistor M1. The light emitting element LD may emit light with a luminance corresponding to the driving current.”, and “[0150] In the fourth period P4 [in FIG. 4], the second transistor M2 and the third transistor M3 may be turned on respectively in response to the fourth scan signal and the second scan signal. Therefore, the data signal supplied to the data line Dj is supplied to the first node N1, and the first transistor M1 is diode-connected, so that data writing and compensation of the threshold voltage of the first transistor M1 can be performed. The supply of the second scan signal is maintained even after the supply of the fourth scan signal is suspended, and thus, the threshold voltage of the first transistor M1 can be compensated for a sufficient amount of time.”; also, it would have been obvious to one of ordinary skill in the art to include the claimed features since it would have been within the general skill of one of ordinary skill in the art to select features on the basis of their suitability for the intended use to display images).
However, it is noted that Kim does not teach:
configuring the light emitting element to emit light in a state in which the second capacitor is connected between the gate node and the source node of the driving transistor.
Zhang teaches:
configuring a light emitting element (OLED in Fig. 3) to emit light in a state in which a second capacitor (C2) is connected between a gate node and a source node (DTFT upper node) of a driving transistor (DTFT) (Zhang: Figs. 3-4, “[0059]…. In the embodiments of the present invention,… the source is called a first electrode….”, “[0075] As shown in FIG. 3,… the first electrode of the driving transistor DTFT is connected with the second electrode of the second transistor TFT2, the second electrode of the driving transistor DTFT is connected with the light-emitting unit, and a control electrode of the driving transistor DTFT is connected with the first node A.”, [0080] (including: “In the light emission for display stage,… the light emission control signal is inputted into the first control signal line S1, the second transistor TFT2 and the driving transistor DTFT are turned on, and a high level is applied to the first voltage terminal ELVdd, so that the organic light-emitting diode OLED is driven to emit light, thereby achieving display….”), and “[0081]… [T]he voltage stabilization control signal is inputted into the second control signal line [S2], that is, the second control signal has a high level, so that the third transistor TFT3 is turned on, the first terminal of the second storage capacitor C2 is connected with the first voltage terminal ELVdd into which a high level signal is inputted, and the potential at the first node A can be stabilized through the second storage capacitor C2…. As a result, flicker due to difference between brightness of the organic light-emitting diode OLED which happens when a gate voltage of the driving transistor DTFT is changed because of electric leakage of the first transistor TFT1 and a change of the data signal can be avoided.”).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Zhang, such that Kim as modified teaches: configuring the light emitting element to emit light based on a driving current generated from the driving transistor according to the data voltage stored in the first capacitor in a state in which the second capacitor is connected between the gate node and the source node of the driving transistor (configuring of Kim combined with configuring Zhang), to avoid flicker. (Zhang: “[0081]… As a result [of stabilizing the potential at the first node A], flicker due to difference between brightness of the organic light-emitting diode OLED which happens when a gate voltage of the driving transistor DTFT is changed because of electric leakage of the first transistor TFT1 and a change of the data signal can be avoided.”).
However, it is noted that Kim as modified by Zhang does not teach:
initializing a second capacitor connected to the gate node of the driving transistor by the initialization voltage.
Ouyang teaches:
initializing a second capacitor (Cst in FIG. 1) connected to a gate node of a driving transistor (T) by an initialization voltage (Vref voltage) (Ouyang: FIG. 1 and p. 5, last ¶ (“… [I]n the initialization phase, the initialization unit 10 and the voltage stabilization unit 40 are turned on. The initialization unit 10 provides the initialization signal of the initialization signal terminal Vref to the first node N1, and the voltage stabilization unit 40 provides the initialization signal of the first node N1 to the first node N1. The two node N2 is capable of initializing the signal stored in the storage capacitor Cst….”) and ¶ 4 (“… [T]he gate G of the driving transistor T and the first terminal a of the storage capacitor Cst are electrically connected to the second node N2….”), see also FIGs. 3-8 and p. 5, ¶ 4 (“… [T]he voltage stabilizing unit 40 is electrically connected between the first node N1 and the second node N2; The unit 40 is configured to provide the potential of the first node N1 to the second node N2 during the initialization phase….”)).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Ouyang, such that Kim as modified teaches:
initializing a second capacitor connected to the gate node of the driving transistor by the initialization voltage (second capacitor, gate node, driving transistor, and initialization voltage of Kim as modified combined with initializing of Zhang), to provide initialization for image display.
Allowable Subject Matter
Claims 3-6, 10, 13, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to K. Kiyabu whose telephone number is (571) 270-7836. The examiner can normally be reached Monday to Thursday 9:00 A.M. - 5:00 P.M. EST.
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/K. K./
Examiner, Art Unit 2626
/TEMESGHEN GHEBRETINSAE/Supervisory Patent Examiner, Art Unit 2626 4/6/2026