Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-13 are pending. Bolded claim language below regards newly amended subject matter with a corresponding new rejection citation. Newly amended subject matter that is not bolded does not comprise a new rejection citation (utilizes previous interpretation that is unchanged in view of the new language) or is a newly added claim.
Claim Objections
3. Claim 7 is objected to because of the following informalities: “the second drain electrode” and “the transistor” does not comprise proper antecedent basis. Appropriate correction is required.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 and 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US Patent Application Publication 2022/0223109), herein after referred to as Lai, in view of Kim (US Patent Application Publication 2021/0065631), and further in view of Son et al. (US Patent Application Publication 2021/0265437), herein after referred to as Son.
Regarding independent claim 1, Lai discloses a display device (paragraph [0044]) comprising:
a substrate including a display area and a non-display area outside the display area (Figure 15 depicts a substrate including a display region/area AA and area outside of AA comprising scanning driving circuit 1001.);
a gate driving unit (Figures 1-2 shift register circuit comprising a first inverter 210 and second inverter 220 as described in paragraph [0045]) on the non-display area (Figure 15 depicts a substrate including a display region/area AA and area outside of AA comprising scanning driving circuit 1001 (relating to the shift register of figure 2).); and
a first transistor (Px1) and a second transistor (Nx1) in the gate driving unit (Figure 2 depicts both inverters 210+220 to each respectively comprise a first transistor PX1 and a second transistor Nx1 as described in paragraph [0050].);
an insulating layer (207) on the first transistor (Px1) and the second transistor (Nx1) (Figure 3 depicts insulating layer 207 directly on active layer 206 of the N-type transistor (Nx1) and indirectly over the active layer 202 of the P-type transistor (PX1)); and
[ ],
wherein the first transistor (Px1) includes (Figure 3 and paragraph [0051] describes the depicted inverter can be utilized as either of the first or second inverter.) a first semiconductor layer (P-type active layer 202), a first gate electrode (204 [0052] describes to share the gate electrode), a first source electrode (208+2081 [0051] erroneously refers to first through fourth holes as 2091-2094, the figures reference numerals will be utilized for the rest of this rejection.), and a first drain electrode (209+2091), and the second transistor (Nx1) includes a second semiconductor layer (N-type active layer 206), the first gate electrode (204), a second source electrode (208+2082), a second drain electrode (209+2092), [ ],
wherein the first semiconductor layer (202) is made of a poly-crystalline material ([0053]), and the second semiconductor layer (206) is made of an oxide semiconductor material ([0059]), and
wherein the first transistor (Px1) is pMOS transistor and the second transistor (Nx1) is nMOS transistor ([0050]),
[ ], and
wherein the first source electrode (208 used with 2081), the first drain electrode (209 used with 2091), the second source electrode (208 used with 2082), and the second drain electrode (209 used with 2092) are disposed on the insulating layer (207).
Lai does not specifically disclose the second transistor with a second gate electrode, a gate line on the insulating layer, or wherein the gate line is connected to the second gate electrode through a contact hole in the insulating layer.
Kim discloses a second transistor with a second gate electrode (Figure 7 depicts pull-up transistor with a top gate electrode GE_T and bottom gate electrode GE_B (gate control electrode) disposed under the semiconductor layer ACT of the pull-up transistor as described in paragraph [0122].).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Lai’s second transistor with the known technique of a second gate electrode yielding the predictable results of reducing or preventing the leaking current and degradation of the transistor as disclosed by Kim (paragraph [0118]).
It is noted Kim discloses utilizing a contact hole may be utilized in an insulating layer (212) to directly coupled electrically the gate electrode (GE_B) to a wiring/film (LSu) (Figure 7 [0123]).
Son discloses a gate line (Figure 10 161) on the insulating layer (116), or wherein the gate line (161) is connected to an upper gate electrode (G1) through a contact hole (CNT4) in the insulating layer (116) ([0136] describes the contact hole connection between the upper gate electrode G1 and gate wiring 161. [0183] describes the use of a double gate.).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Lai-Kim’s second transistor with upper second gate electrode with the known technique of a gate line on the insulating layer, wherein the gate line is connected to the second gate electrode through a contact hole in the insulating layer yielding the predictable results of enabling a node connection to the gate electrode as disclosed by Son ([0061]).
Regarding claim 2, Kim discloses the display device of claim 1, wherein the second gate electrode is a gate control electrode for applying a gate controlling voltage to the second transistor (Paragraphs [0109], [0120], and [0122] describes applying a VGL signal to the bottom electrode.).
Regarding claim 3, Lai discloses the display device of claim 1, wherein the first transistor (Figure 2 PX1) and the second transistor (Nx1) share the first gate electrode ([0052]).
Regarding claim 4, Lai discloses the display device of claim 1, wherein the first semiconductor layer (Figure 3 202) and the second semiconductor layer (206) overlap each other with the first gate electrode (204) therebetween (Figure 3 depicts 202 and 206 overlapping.).
Regarding claim 5, Lai and Kim discloses the display device of claim 1, wherein the first gate electrode (Lai: figure 3 204; Kim: figure 7 GE_T) and the second gate electrode (Kim: figure 7 GE_B) overlap each other with the second semiconductor layer (Lai: figure 3 206) therebetween (Kim: Figure 7 depicts GE_T above ACT and overlapping GE_B).
Regarding claim 6, Lai discloses the display device of claim 1, wherein the first transistor (Figure 2 Px1) and the second transistor (Nx1) are directly formed on the substrate (Figure 3 reference switch electrodes formed directly on substrate 201.).
Regarding claim 7, Lai discloses the display device of claim 1, wherein the first source electrode (Figure 3 208+2081) of the first transistor (Figure 2 Px1) is connected (Figure 2 paragraph [0050]) to the (claim objection) second drain electrode (209+2092) of the second transistor (Nx1), the first drain electrode (209+2091) of [the] first transistor (Px1) is connected to a high potential voltage (Figure 2 Px1 directly connected with VGH), and the second source electrode (208+2082) of the second transistor (Nx1) is connected to a low potential voltage (Figure 2 Nx1 directly connected with VGL), so that a output voltage is output (Figure 2 output Q12 as described in paragraphs [0047]-[0048]).
Regarding claim 8, Lai discloses the display device of claim 7, wherein an input voltage (Figure 2 input node Q11 as described in paragraphs [0045]-[0046]) is applied to the first gate electrode (Figure 3 204, also depicted in figure 2 as shared gate of Px1 and Nx1) of the first transistor (Px1) and the second transistor (Nx1).
Regarding claim 9, Lai discloses the display device of claim 8, wherein one of the first transistor (Figure 2 Px1) and the second transistor (Nx1) is turned on and other is turned off when the input voltage is applied to the first gate electrode (Paragraph [0056] shared gate single input to inverter pair can only turn on one of Px1 and Nx1 at a time.).
Regarding claim 11, Lai discloses the display device of claim 1, wherein the first transistor (Figure 2 Px1) and the second transistor (Nx1) are overlapped with each other in the same region (Figure 3 depicts source, acts, drain, and gate all overlapping.).
Regarding claim 12, Lai discloses the display device of claim 1, wherein the gate driving unit (Figures 1-2 shift register circuit comprising a first inverter 210 and second inverter 220 as described in paragraph [0045]) includes an inverter (210), and the inverter (210) includes the first transistor (Px1) and the second transistor (Nx1).
Regarding claim 13, Lai discloses the display device of claim 1, wherein the first source electrode (Figure 3 208) is connected to a source region (2081) of the first semiconductor layer (202), the first drain electrode (209) is connected to a drain region (2091) of the first semiconductor layer (202), the second source electrode (208) is connected to a source region (2082) of the second semiconductor layer (206), and the second drain electrode (209) is connected to a drain region (2092) of the second semiconductor layer (206).
5. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai-Kim-Son in view of Goodnow et al. (US Patent Application Publication 2007/0252641), herein after referred to as Goodnow.
Regarding claim 10, Lai and Kim discloses the display device of claim 9.
None of Lai, Kim, or Son disclose wherein a bias voltage is applied to the first gate electrode during an on-state, and a gate controlling voltage having an opposite polarity to the bias voltage is applied to the second gate electrode during an off-state.
Goodnow discloses a bias voltage is applied to the first gate electrode (1502a) during an on-state, and a gate controlling voltage having an opposite polarity to the bias voltage is applied to the second gate electrode (1502b) during an off-state ([0041]-[0042] top gate and bottom gate are described as opposite polarity types which operate at an operating voltage equal to the band-gap voltage exampled as 1.1 volts (positive 1.1 and negative -1.1 operating voltage respectively).).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Lai-Kim-Son double gate with the known technique of a bias voltage is applied to the first gate electrode during an on-state, and a gate controlling voltage having an opposite polarity to the bias voltage is applied to the second gate electrode during an off-state yielding the predictable results of enabling a lower operating voltage as disclosed by Goodnow ([0042]).
Response to Arguments
6. Applicant's arguments filed 7/20/2026 have been fully considered but they are not persuasive. Applicant argues newly amended subject matter of the independent claim. Please refer to newly cited art Son, utilized to reject the newly amended subject matter, in the above office action as rebuttal. It is noted newly added claim 13 describes the electrical connections between the electrodes. It is suggested to further detail the direct electrical connection between each of the electrodes and additionally the first and second gates in view of applicant’s figure 4. This action is final necessitated by amendment. An interview will be granted at applicant’s request.
Conclusion
7. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER E LEIBY whose telephone number is (571)270-3142. The examiner can normally be reached 11-7.
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/CHRISTOPHER E LEIBY/Primary Examiner, Art Unit 2621
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