Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Application
This action is in response to Applicant's filing on 22 July 2026. Claims 1-24 are presently pending and under consideration.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 18 August 2025 and 7 April 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10-20, 23, and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Agarwal et al (US 2018/0189104 A1, hereinafter Agarwal).
Regarding claim 10, Agarwal discloses a host system comprising: a communication interface (See Agarwal, [0028], “on-chip interface module” and “on-chip interface 11 is to communicate with devices external to processor 100” and [0042], “supports a common command interface for work submission from all of its clients”); and
at least one controller configured to: write, via the communication interface and using a memory write (See Agarwal, [0028], “a memory controller, which is described in more detail below, has been included in a computing system external to processor” and [0068] “When the work specified by the command is completed, the device generates appropriate synchronization or notification transactions to inform the client about work completions. These could be through memory writes, interrupt writes, or other methods”), a command to an address of a shared work queue (SWQ) in a memory sub-system (See Agarwal [0046] disclosing “submit work (commands) to a device SWQ through a set of new CPU instructions” and [0051], [0052] ENQCMD/S enqueue 64-byte command as a non-posted write to destination SWQ address (MMIO address)” and [0060] The non-posted write transaction is address routed like any normal MMIO write to the target device); and
receive, from the memory sub-system, a reply to the memory write that reduces available credits (See Agarwal, [0093] The SWQ 254 can then send a success/retry message 312 back to the VSWQ 302 in the I/O bridge 204 to update the credit counter).
Regarding claim 11, Agarwal disclosed the host system of claim 10 as above. Agarwal further discloses wherein the memory write is a posted transaction (See Agarwal, [0060] “address routed like any normal MMIO write to the target device” and [0068] “When the work specified by the command is completed, the device generates appropriate synchronization or notification transactions to inform the client about work completions. These could be through memory writes, interrupt writes, or other method”).
Regarding claim 12, Agarwal disclosed the host system of claim 10 as above. Agarwal further discloses wherein the memory sub-system sends the reply in response to determining that a command queue of the memory sub-system is full (See Agarwal, [0089] the VSWQ 302 is implemented using a set of credit counters which tracks the availability of SWQ buffers at the target device and [0094] determine whether there are available credits for the SWQ (408). If there are no credits available, then the VSWQ can send a retry message to the requesting device (410)”).
Regarding claim 13, Agarwal disclosed the host system of claim 10 as above. Agarwal further discloses wherein the command and address are input parameters for a store instruction invoked by a thread (See Agarwal, [0051] and [0052] disclosing command ENQCMD/S which is an enqueue 64-byte command as a non-posted write to destination SWQ address (MMIO address), and [0061], ENQCMD instruction use the PASID associated with the current software thread (something the OS is expected to save/restore using XSAVES/XRSTORS instructions on thread context switches, or in other words, the ENQCMD commands are invoked by currently running threads)..
Regarding claim 14, Agarwal disclosed the host system of claim 10 as above. Agarwal further discloses wherein the memory write is performed according to a standard for peripheral component interconnect express (PCle) (See Agarwal, [0093] “A core 202 can transmit an ENQCMD/S message 304 with an MMIO address for a SWQ 254 associated with a device (here, PCIe EP 212)”).
Regarding claim 15, Agarwal disclosed the host system of claim 10 as above. Agarwal further discloses wherein the command is written by sending a transaction layer packet (TLP) including the command to the address (See Agarwal, [0108], “In one embodiment, transaction layer 705 is to provide an interface between a device's processing core and the interconnect architecture, such as data link layer 710 and physical layer 720. In this regard, a primary responsibility of the transaction layer 705 is the assembly and disassembly of packets (i.e., transaction layer packets, or TLPs). The translation layer 705 typically manages credit-base flow control for TLPs” and [0110] “In one embodiment, four transaction address spaces include a configuration address space, a memory address space, an input/output address space, and a message address space. Memory space transactions include one or more of read requests and write requests to transfer data to/from a memory-mapped location. In one embodiment, memory space transactions are capable of using two different address formats, e.g., a short address format, such as a 32-bit address, or a long address format, such as 64-bit address. Configuration space transactions are used to access configuration space of the PCIe devices. Transactions to the configuration space include read requests and write requests. Message space transactions (or, simply messages) are defined to support in-band communication between PCIe agents”).
Regarding claim 16, Agarwal disclosed the host system of claim 10 as above. Agarwal further discloses wherein the command is configured according to a standard for non-volatile memory express (NVMe) (See Agarwal [0036] disclosing “Examples of such multi-client accelerator/high-performance devices include…. NVM-Express storage controllers devices”, or in other words, commands configured/compatible with the NVMe standard).
Regarding claim 17, Agarwal disclosed the host system of claim 10 as above. Agarwal further discloses wherein the command includes a completion address, and the host system is configured to receive a completion record at the completion address (See Agarwal, [0060] These CPU instructions produce an atomic non-posted write transaction (a write transaction for which a completion response is returned back to the CPU). The non-posted write transaction is address routed like any normal MMIO write to the target device and [0068] When the work specified by the command is completed, the device generates appropriate synchronization or notification transactions to inform the client about work completions. These could be through memory writes, interrupt writes, or other methods and [0073] c. Execute ENQCMD/S with the memory virtual address of descriptor as source and the virtual address to which the SWQ_PREG is mapped as the destination).
Regarding claim 18, Agarwal discloses a host system comprising: memory to provide a local shared work queue (LSWQ) (See Agarwal, Fig. 3 disclosing VSWQ of the I/O bridge and [0086], “This disclosure describes reducing the round trip latency by maintaining a Virtual Shared Work Queue (VSWQ) in the root complex, close to the CPU submitting work to a device”); and
at least one controller configured to: add an entry to the local shared work queue (LSWQ), wherein the entry includes a command and an address for a shared work queue (SWQ) of a memory sub-system (See Agarwal, [0090] the VSWQ 302 will be indexed by the MMIO address issued by the ENQCMD/S instruction and [0093] A core 202 can transmit an ENQCMD/S message 304 with an MMIO address for a SWQ 254 associated with a device (here, PCIe EP 212). The ENQCMD/s message 304 is indexed to the VSWQ 302 within the I/O bridge 204); and
write the command to the address (See Agarwal, [0067] If the above checks result in the non-posted write command to be accepted to the SWQ, a completion is returned with completion status of “Successful Completion”. The command queued to the SWQ is processed/dispatched based on the device-specific scheduling model internal to the device and [0068] When the work specified by the command is completed, the device generates appropriate synchronization or notification transactions to inform the client about work completions. These could be through memory writes, interrupt writes, or other methods).
Regarding claim 19, Agarwal disclosed the host system of claim 18 as above. Agarwal further discloses wherein the entry is added in response to a processing device of the host system invoking a store instruction (See Agarwal, [0067] “If the above checks result in the non-posted write command to be accepted to the SWQ, a completion is returned with completion status of “Successful Completion”. The command queued to the SWQ is processed/dispatched based on the device-specific scheduling model internal to the device” and [0068] “When the work specified by the command is completed, the device generates appropriate synchronization or notification transactions to inform the client about work completions. These could be through memory writes, interrupt writes, or other method”, or in other words, a write/store command and [0093] “A core 202 can transmit an ENQCMD/S message 304 with an MMIO address for a SWQ 254 associated with a device (here, PCIe EP 212). The ENQCMD/s message 304 is indexed to the VSWQ 302 within the I/O bridge 204” or in other words, a host command, the host command being a write/store command).
Regarding claim 20, Agarwal disclosed the host system of claim 18 as above. Agarwal further discloses wherein the controller is further configured to: determine the LSWQ is full; and in response to determining the LSWQ is full, send a signal to a processing device to retry queuing the entry (See Agarwal, [0093] A core 202 can transmit an ENQCMD/S message 304 with an MMIO address for a SWQ 254 associated with a device (here, PCIe EP 212). The ENQCMD/s message 304 is indexed to the VSWQ 302 within the I/O bridge 204. The VSWQ can provide a success/retry message 306).
Regarding claim 23, Agarwal disclosed the host system of claim 18 as above. Agarwal further discloses wherein the command is written to the address using a memory write (See Agarwal, [0068] “When the work specified by the command is completed, the device generates appropriate synchronization or notification transactions to inform the client about work completions. These could be through memory writes, interrupt writes, or other method”) .
Regarding claim 24, Agarwal disclosed the host system of claim 23 as above. Agarwal further discloses wherein the controller is further configured to receive, from the memory sub-system, a reply to the memory write that reduces available credits for transactions (See Agarwal, [0092] “The QoS policies implemented by the SWQ 254 of a device may also be emulated by the VSWQ 302 by establishing credit thresholds for privileged vs non-privileged modes of work” and [0093], “The SWQ 254 can then send a success/retry message 312 back to the VSWQ 302 in the I/O bridge 204 to update the credit counter”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-9 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Agarwal et al (US 2018/0189104 A1, hereinafter Agarwal) in view of Sankaran et al (US 2021/0209037 A1, hereinafter Sankaran).
Regarding claim 1, Agarwal discloses a host system comprising: a communication interface (See Agarwal, [0028], “on-chip interface module” and “on-chip interface 11 is to communicate with devices external to processor 100” and [0042], “supports a common command interface for work submission from all of its clients”); and
at least one controller (See Agarwal, [0028], “a memory controller, which is described in more detail below, has been included in a computing system external to processor”) configured to: receive a command and an address of a shared work queue (SWQ) in a memory sub-system (See Agarwal, [0046] disclosing “submit work (commands) to a device SWQ through a set of new CPU instructions” and [0051], [0052] ENQCMD/S enqueue 64-byte command as a non-posted write to destination SWQ address (MMIO address)”); and
write, via the communication interface, the command to the address (See Agarwal, [0046] disclosing “submit work (commands) to a device SWQ through a set of new CPU instructions” and [0051], [0052] ENQCMD/S enqueue 64-byte command as a non-posted write to destination SWQ address (MMIO address)”).
Agarwal does not disclose using a deferred memory write.
However, Sankaran discloses using a deferred memory write (See Sankaran, [0143], “Deferred Memory Write Request (DMWr)”).
Agarwal and Sankaran are analogous art directed to command scheduling in heterogeneous systems. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the shared work queue system of Agarwal with the deferred writes of Sankaran as system flexibility can be increased as deferrable memory writes facilitate use cases that were previously not possible by accepting work items from multiple non-cooperating software agents in a non-blocking way (See Sankaran, [0154]).
Regarding claim 2, Agarwal in view of Sankaran disclosed the host system of claim 1 as above. Agarwal further discloses wherein the command and address are received from execution of a store instruction invoked by a thread (See Agarwal, [0051] and [0052] disclosing command ENQCMD/S which is an enqueue 64-byte command as a non-posted write to destination SWQ address (MMIO address), and [0061], ENQCMD instruction use the PASID associated with the current software thread (something the OS is expected to save/restore using XSAVES/XRSTORS instructions on thread context switches, or in other words, the ENQCMD commands are invoked by currently running threads).
Regarding claim 3, Agarwal in view of Sankaran disclosed the host system of claim 1 as above. Sankaran further discloses wherein the deferred memory write is performed according to a standard for peripheral component interconnect express (PCle) (See Sankaran, [0143] “This disclosure describes a PCIe packet type, referred to herein as an “Deferred Memory Write Request” (DMWr)”).
Regarding claim 4, Agarwal in view of Sankaran disclosed the host system of claim 1 as above. Agarwal further discloses wherein the command is written by sending a transaction layer packet (TLP) including the command to the address (See Agarwal, [0108], “In one embodiment, transaction layer 705 is to provide an interface between a device's processing core and the interconnect architecture, such as data link layer 710 and physical layer 720. In this regard, a primary responsibility of the transaction layer 705 is the assembly and disassembly of packets (i.e., transaction layer packets, or TLPs). The translation layer 705 typically manages credit-base flow control for TLPs” and [0110] “In one embodiment, four transaction address spaces include a configuration address space, a memory address space, an input/output address space, and a message address space. Memory space transactions include one or more of read requests and write requests to transfer data to/from a memory-mapped location. In one embodiment, memory space transactions are capable of using two different address formats, e.g., a short address format, such as a 32-bit address, or a long address format, such as 64-bit address. Configuration space transactions are used to access configuration space of the PCIe devices. Transactions to the configuration space include read requests and write requests. Message space transactions (or, simply messages) are defined to support in-band communication between PCIe agents”).
Regarding claim 5, Agarwal in view of Sankaran disclosed the host system of claim 1 as above. Agarwal further discloses wherein the command is configured according to a standard for non-volatile memory express (NVMe) (See Agarwal [0036] disclosing “Examples of such multi-client accelerator/high-performance devices include…. NVM-Express storage controllers devices”, or in other words, commands configured/compatible with the NVMe standard).
Regarding claim 6, Agarwal in view of Sankaran disclosed the host system of claim 1 as above. Sankaran further discloses wherein the controller is further configured to receive, in reply to the deferred memory write, a retry signal (See Sankaran, Fig. 7B and [0147] FIGS. 7A-D are schematic diagrams illustrating an example acknowledged memory write (DMWr) request and response message flow in accordance with embodiments of the present disclosure and [0150] “In FIG. 7B, the command queue 704 is full. 4) Entity B issues command to the command queue 704 while the command queue 704 is full. 5) The accelerator 702 declines the request, and 6) the accelerator 702 sends a Completion with Request Retry Status (RRS). 7) If entity B attempts to reissue the command while the queue is still fill, the accelerator 702 can continue to send associated Completions with RRS in the status field”).
Regarding claim 7, Agarwal in view of Sankaran disclosed the host system of claim 6 as above. Agarwal further discloses wherein the address is a first address, the command is a first command, the shared work queue is a first shared work queue (See Agarwal, [0046] disclosing “submit work (commands) to a device SWQ through a set of new CPU instructions” and [0051], [0052] ENQCMD/S enqueue 64-byte command as a non-posted write to destination SWQ address (MMIO address)” and the controller is further configured to, in response to receiving the retry signal, write a second command to a second address of a second shared work queue (See Agarwal, [0045], In some implementations, a device may implement more than one (but a small number) of SWQs. For example, the device may do so by implementing one SWQ for all supervisor (kernel-mode) client requests, while using a different SWQ for all user-mode client requests. Alternatively, it may support a SWQ for all (ring-0 and ring-3) host clients, and use separate SWQs for any peer device work submission for in-lining usages and [0074] d. Execute a condition jump (JZ) to check if the ENQCMD/S instruction returned success or retry. If retry status, either retry from step-C (with appropriate back-off and [0073] c. Execute ENQCMD/S with the memory virtual address of descriptor as source and the virtual address to which the SWQ_PREG is mapped as the destination).
Regarding claim 8, Agarwal in view of Sankaran disclosed the host system of claim 1 as above. Sankaran further discloses wherein the controller is further configured to receive, in response to the deferred memory write, an accepted signal (See Sankaran, [0149] In the example shown in FIG. 7A, accelerator command queue 704 is nearly full. 1) Entity A issues a command to the queue 704 via an DMWr Packet. 2) The accelerator can accept the command into the command queue. 3) The accelerator 702 can respond with a Successful Completion (SC)”).
Regarding claim 9, Agarwal in view of Sankaran disclosed the host system of claim 1 as above. Sankaran further discloses wherein the deferred memory write is a non-posted transaction (See Sankaran [0143] “This disclosure describes a PCIe packet type, referred to herein as an “Deferred Memory Write Request” (DMWr)” and [0144], “DMWr packets are Non-Posted transactions”).
Regarding claim 21, Agarwal disclosed the host system of claim 18 as above. Agarwal further discloses wherein the command is written to the address (See Agarwal [0067] If the above checks result in the non-posted write command to be accepted to the SWQ, a completion is returned with completion status of “Successful Completion”. The command queued to the SWQ is processed/dispatched based on the device-specific scheduling model internal to the device and [0068] When the work specified by the command is completed, the device generates appropriate synchronization or notification transactions to inform the client about work completions. These could be through memory writes, interrupt writes, or other methods). Agarwal does not disclose using a deferred memory write.
However, Sankaran discloses using a deferred memory write (See Sankaran, [0143], “Deferred Memory Write Request (DMWr)”).
Agarwal and Sankaran are analogous art directed to command scheduling in heterogeneous systems. It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to combine the shared work queue system of Agarwal with the deferred writes of Sankaran as system flexibility can be increased as deferrable memory writes facilitate use cases that were previously not possible by accepting work items from multiple non-cooperating software agents in a non-blocking way (See Sankaran, [0154]).
Regarding claim 22, Agarwal in view of Sankaran disclosed the host system of claim 21 as above. Sankaran further discloses wherein the controller is further configured to receive, in reply to the deferred memory write, a retry signal (See Sankaran, Fig. 7B and [0147] FIGS. 7A-D are schematic diagrams illustrating an example acknowledged memory write (DMWr) request and response message flow in accordance with embodiments of the present disclosure and [0150] “In FIG. 7B, the command queue 704 is full. 4) Entity B issues command to the command queue 704 while the command queue 704 is full. 5) The accelerator 702 declines the request, and 6) the accelerator 702 sends a Completion with Request Retry Status (RRS). 7) If entity B attempts to reissue the command while the queue is still fill, the accelerator 702 can continue to send associated Completions with RRS in the status field”).
EXAMINER’S NOTE
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicants. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicants in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Xue et al (US 20230004503 A1) discloses a system using a shared work queue and an instruction to atomically submit the descriptor to the shared work queue via a non-posted write/a deferred memory write.
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/E.H.K/Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
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