DETAILED ACTION
This action is responsive to 06/30/2026.
Claims 1-8 and 10-20 are pending.
Claim 9 is canceled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 16-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sun et al. (US Pub. 2021/0209986), hereinafter Sun, in view of Lee et al. (US Pub. 2017/0352311), hereinafter Lee.
Regarding claim 1, Sun discloses a display panel (see fig. 1), comprising an active area (display area 20-see fig. 1A-1B and [0056]) and an irregular-shaped area (notch-see figs. 1A-1B and [0057]), wherein the active area comprises a first active area disposed on a side of the irregular-shaped area (sub-display area (a1, a2)-see figs. 1A-1B) and a second active area connected to the first active area (i.e., display area below the trough and the sub-display (a1, a2)-see figs. 1A-1B), and the display panel comprising: one or more first signal lines disposed in the second active area (see fig. 2B-gate lines Gate-1, Gate-2 … in the display area below the notch and the sub-display); one or more second signal lines disposed in the first active area (gate lines Gate1, Gate2, … Gaten-see figs. 1B and 2B), an extending direction of the first signal line being same as an extending direction of the second signal line (see fig. 2B), and a length of the first signal line being greater than a length of the second signal line (i.e., the length of each gate line Gate-1, Gate-2 is comparatively greater than the length of Gate1 and Gate2-see figs. 1A-1B); and a compensation circuit comprising one or more compensation modules (compensation circuit 300 (310, 320, and 330)-see fig. 2A and [0080]), the one or more compensation modules comprising a plurality of compensation units arranged at intervals (each compensation sub-circuit (e.g., 310, 320, and 330) has a plurality of signal line compensation circuits (see, for example, fig. 5) arrange at intervals-see, for example, figs. 4 and 19-20), and at least one of the plurality of compensation units being connected to a respective one of the second signal lines (see figs. 2B, 3-4, and 19-20), wherein each of the one or more compensation modules further comprises one or more control signal lines (switching trigger lines S1-see, for example, fig. 3 and [0066]-[0067]), and each of the one or more control signal lines is configured to control connectivity between one of the plurality of compensation units and a respective one of the second signal lines (see, for example, fig. 3 with description in [0061], which discloses that total capacitance compensation for the gate lines is the sum of the capacitance values of each effective compensation capacitor formed between each control line D1, D2, …, Dn and each gate line Gate1, Gate2, …, Gaten. Therefore, when the total capacitance of the gate lines needs to be increased, a charging signal may be applied to more control lines, and when the total capacitance compensation of the gate lines needs to be reduced, the charging signal may be applied to fewer control lines).
Sun does not appear to expressly disclose wherein the display panel further comprises a border area around the active area, and the display panel further comprises a first gate driving circuit and a second gate driving circuit disposed in the border area; and wherein the first gate driving circuit is disposed on a side of the first active area away from the second active area, the second gate driving circuit is disposed on a side of the second active area close to the irregular-shaped area, and the first gate driving circuit and the second gate driving circuit are arranged in the extending direction of the first signal line and the second signal line.
Lee is relied upon to teach wherein the display panel further comprises a border area arranged around the active area (peripheral or non-display regions (NA1, NA2)-see [0034] and figs. 3-4), and the display panel further comprises a first gate driving circuit and a second gate driving circuit disposed in the border area (see, for example fig. 4-first scan driver 210 and second scan driver 213 disposed in a border area outside pixels areas (AA1 and AA2)), wherein the first gate driving circuit is disposed on a side of the first active area away from the second active area (see fig. 4-first scan driver 210 (herein equated to claimed first gate driving circuit)), the second gate driving circuit is disposed on a side of the second active area close to the irregular-shaped area (second scan driver 213-see fig. 4), and the first gate driving circuit and the second gate driving circuit are arranged in the extending direction of the first signal line and the second signal line (see fig. 4-first and second scan drivers (210, 213) are disposed in an extending direction same as data lines (e.g., Dm-1, Dm)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Lee with the invention of Sun, such that the display panel has two or more gate driver circuits disposed in appropriate non-display border portions of the display panel, as taught by Lee, which constitutes combining prior art elements according to known methods to yield predictable results.
Regarding claim 2, Sun discloses wherein each of the compensation modules comprises a plurality of compensation units arranged at intervals or a single compensation unit (each compensation sub-circuit (e.g., 310, 320, and 330) has a plurality of signal line compensation circuits (see, for example, fig. 5) arrange at intervals-see, for example, figs. 4 and 19-20).
Regarding claim 3, Sun discloses wherein the number of compensation units controlled by each control signal line is one or more (see, for example, figs. 3-4).
Regarding claim 4, Sun discloses wherein the compensation circuit is disposed on a side of the first active area close to the irregular-shaped area (see fig. 3-compensation circuit 300).
Regarding claim 5, Lee discloses a special-shaped screen with a notch in a display area, however, Lee does not appear to expressly wherein the first active area and the second active area form a polygonal shape having a missing corner, the missing corner corresponding to the irregular-shaped area.
Lee is relied upon to teach wherein the first active area and the second active area form a polygonal shape having a missing corner, the missing corner corresponding to the irregular-shaped area (see fig. 1).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Lee with the invention of Sun such that an irregular-shaped portion of a non-rectangular display is formed at one corner of a polygon-shaped display, as taught by Lee, which constitutes choosing from a finite number of identified, predictable solutions, for forming a notched area in a display panel, with a reasonable expectation of success.
Regarding claim 16, Sun discloses wherein each of the one or more compensation modules comprises a plurality of control signal lines (switching trigger lines S1-see, for example, fig. 3 and [0066]-[0067]), and each of the plurality of control signal lines is connected to at least one of the plurality of compensation units and is configured to control connectivity between one of the at least one compensation unit and a respective one of the second signal lines (see [0061]-total capacitance compensation of a gate line can be increased or reduced by applying a charging signal to more or fewer control lines).
Regarding claim 17, Sun discloses wherein each of the compensation modules further comprises a compensation line (control lines D1, D2, …, Dn-see fig. 3) and a second connecting line, a terminal of the second connecting line is connected to a corresponding one of the plurality of compensation units, and another terminal of the second connecting line intersects with the compensation line (each capacitor C is connected to a corresponding control line D-see fig. 3) and is disposed in different layers with the compensation line (see, for example, figs. 7-8A and [0096], wherein each capacitor is formed by overlapping portions disposed on different layers).
Regarding claim 18, Sun discloses wherein each of the plurality of compensation units comprises a capacitor, a terminal of the capacitor is connected to the second connecting line, and another terminal of the capacitor is connected to a power supply (see fig. 3-each capacitor C is connected between a signal source 40 and a corresponding gate line Gate1, Gate2, …, Gaten).
Regarding claim 20, Sun discloses wherein the compensation circuit comprises a plurality of compensation modules (compensation circuit 300 (310, 320, and 330)-see fig. 2A and [0080]), and each of the second signal lines is connected to a respective one of the plurality of compensation modules (see figs. 2B, 3-4, and 19-20).
Claims 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sun in view of Lee, and further in view of Yang et al. (US Pub. 2018/0166018), hereinafter Yang.
Regarding claim 6, Sun is silent about a controller or driving chip for the display, However, Lee is relied upon to teach wherein the display panel is configured with a driving chip (see figs. 4 and 12-13), the driving chip is connected to the one or more first signal lines and the one or more second signal lines (see, for example, fig. 4, wherein second scan driver 213 is connected to scan lines in display region AA2 (first region), and second scan driver 210 is connected to scan lines in display region AA1 (second region)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Lee with the inventions of Sun to include one or more driving chips for driving the different display areas, as taught by Lee, which constitutes combining prior art elements according to known methods to yield predictable results.
Sun in view of Lee does not appear to expressly teach and the compensation circuit is connected to the one or more second signal lines on a side of the one or more second signal lines away from the driving chip.
Yang is relied upon to teach and the compensation circuit is connected to the one or more second signal lines on a side of the one or more second signal lines away from the driving chip (see, for example, fig. 1, wherein compensation units 13 are connected to scan lines 13 on a side away from gate driving unit 11).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Yang with the inventions of Sun and Lee such that the compensation is connected to signal lines on a side of the second signal lines away from a driving chip, as taught by Yang, which constitutes combining prior art elements according to known methods to yield predictable results (i.e., improve uniformity of display brightness and optimize a display effect-see [0005]).
Regarding claim 7, Lee is further relied upon to teach wherein the display panel further comprises a border area arranged around the active area, and the driving chip is disposed in the border area, or wherein the driving chip is bent and connected to a backside of the display panel (see, for example, figs. 1 and 4, wherein the driver chip (210, 213) is disposed in a non-display area (NA1, NA2)).
Regarding claim 8, Sun discloses wherein both the one or more first signal lines and the one or more second signal lines are data lines (see [0110]-signal line capacitance compensation circuit is not limited to gate lines, but may also be used to compensate the consistency of parasitic capacitance generated by signal lines (such as data lines, etc.)).
Claim 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sun in view of Lee, and further in view of Kim et al. (US Patent 10,388,227), hereinafter Kim.
Regarding claim 10, Sun in view of Lee does not appear to expressly teach wherein the display panel further comprises a third gate driving circuit, the third gate driving circuit is disposed on a side of the second active area away from the first active area and the irregular-shaped area, and the third gate driving circuit is arranged in the extending direction of the first signal Line and the second signal line.
Kim is relied upon to teach wherein the display panel further comprises a third gate driving circuit, the third gate driving circuit is disposed on a side of the second active area away from the first active area and the irregular-shaped area, and the third gate driving circuit is arranged in the extending direction of the first signal Line and the second signal line (see, for example, fig. 10-display device 10’ has four scan driver circuits-210, 220, 230 and 240, scan driver circuits 210 and 240 are disposed on opposite sides of a first display area AA1 (corresponding to claimed second active area), and scan drivers 220 and 220 are disposed on sides of display areas AA2 and AA3 (corresponding to claimed first active area)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Kim with the inventions of Sun and Lee by having three or more scan driver circuits at appropriate locations along a border area of a non-quadrangular display, as taught by Kim, which constitutes combining prior art elements according to known methods to yield predictable results.
Claims 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sun in view of Lee, and further in view of Shin et al. (US Patent 11,127,354), hereinafter Shin.
Regarding claim 11, Sun discloses wherein a plurality of compensation units comprises a switching transistor and a compensation element (see, for example, fig. 4).
However, Sun in view of Lee does not appear to expressly disclose wherein each of the plurality of compensation units comprises a switching transistor and a compensation element, a control terminal of the switching transistor is connected to a respective one of the control signal lines, a first terminal of the switching transistor is connected to the respective one of the second signal lines, and a second terminal of the switching transistor is connected to the compensation element.
Shin is relied upon to teach wherein each of the plurality of compensation units comprises a switching transistor and a compensation element (see, for example, fig. 7 with description in [col. 22, ll. 60-col. 23, ll. 4]-compensation circuit includes, for example, first switching element M1 and a capacitor Cj (compensation element)), a control terminal of the switching transistor is connected to a respective one of the control signal lines (gate of M1 is connected to control line SL1-see fig. 7), a first terminal of the switching transistor is connected to the respective one of the second signal lines (fist electrode of M1 is connected to a kth scan line Sk-see fig. 7 and description in [col. 22, ll. 60-64]), and a second terminal of the switching transistor is connected to the compensation element (see fig. 7 and description in [col. 22, ll. 60-64]-second electrode of M1 is connected to capacitor Cj).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the compensation circuit of Shin with the inventions of Sun and Lee as a simple substitution of one known element for another to yield predictable results (i.e., performing load compensation of scan lines in order to provide uniform brightness).
Regarding claim 12, Shin is further relied upon to teach wherein the compensation element comprises a capacitor (capacitor Cj-see fig. 7), the second terminal of the switching transistor is connected to a terminal of the capacitor (see fig. 7), and another terminal of the capacitor is connected to a power supply (see fig. 7-another terminal of capacitor Cj is coupled to VSS (second power supply)).
Claims 13 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sun.
Regarding 13, Sun discloses wherein each of the one or more compensation modules comprises a respective one of the one or more control signal lines (S1-see, for example, figs. 3-5 and [0066]-[0067]), wherein each of the plurality of compensation units comprises a switching transistor (see, for example, fig. 3-control switches K1 to Kn, or T2, T3,…in fig. 4), a control terminal of the switching transistor intersects with the control signal line (see, for example, fig. 3, wherein control terminals (K13, K23) respectively of switches K1 and K2, intersect control line S1), the control terminal of the switching transistor is connected to a first connecting line, and the first connecting line intersects with the control signal line (K13 and K23 are connected to S1 by a connecting line as shown in fig. 3).
Sun does not appear to expressly disclose a control terminal of the switching transistor intersects with the control signal line and is disposed in different layers with the control signal line, the control terminal of the switching transistor is connected to a first connecting line, and the first connecting line intersects with the control signal line and is disposed in different layers with the control signal line.
However, having a control terminal of a switching transistor and control signal line disposed in different layers can be gleaned in, for example, figs. 7-18 with description in, for example, [0096].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to dispose the control signal line on a different layer from a layer on which a gate electrode of the switching transistor is formed, as gleaned from the combined teachings of Sun, which constitutes combining prior art elements according to known methods to yield predictable results (i.e., providing more space for a structural design of the panel-see [0096]).
Regarding claim 15, Sun discloses wherein the compensation circuit comprises a plurality of compensation modules intervals (each compensation sub-circuit (e.g., 310, 320, and 330) has a plurality of signal line compensation circuits (see, for example, fig. 5)), and wherein the plurality of compensation modules is configured to share a same control signal line or each of the plurality of compensation modules is configured with a respective one of the control signal lines (see, for example, fig. 3).
Claims 14 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sun in view of Lee, and further in view of Park et al. (US Pub. 2005/0012873), hereinafter Park.
Regarding claim 14, Sun in view of Lee does not appear to expressly disclose wherein a laser mark is provided on the control signal line, and the laser mark is disposed at an intersection of the control signal line and the control terminal of the switching transistor, or wherein a laser mark is disposed at an intersection of the control signal line and the first connecting line.
Park, in for example, [0032] and [0073] teaches performing electrical connection between first and second wirings disposed on different layers by irradiating with a laser beam, wherein, for example, protrusions P1 and P2 are used to determine overlap positions of first power voltage wiring VSS1 and first connection wiring VSS2 for irradiating with a laser beam to electrically connect the wirings.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Park with the inventions of Sun and Lee by connecting electrical wirings on different layers by laser irradiation, wherein, markings are provided to determine irradiation location, as taught by Park, which constitutes combining prior art elements according to known methods to yield predictable results.
Regarding claim 19, Park is further relied upon to each wherein a connection mark is provided at an intersection of the compensation line and the second connecting line (see, for example, figs. 6-7C and [0077]-[0078] and claim 2-protrusions P1 and P2 are used to determine overlap positions of first power voltage wiring VSS1 and first connection wiring VSS2 for irradiating with a laser beam to electrically connect the wirings).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Park with the inventions of Sun and Lee by connecting electrical wirings on different layers by laser irradiation, wherein, markings are provided to determine irradiation location, as taught by Park, which constitutes combining prior art elements according to known methods to yield predictable results.
Response to Arguments
Applicant's arguments filed 06/30/2026 have been fully considered but they are not persuasive. Applicant argued (see remarks, pg. 2-3) that applied references, specifically Lee et al. (US Pub. 2017/0352311) fails to teach or suggest the limitations “wherein the display panel further comprises a border area arranged around the active area, and the display panel further comprises a first gate driving circuit and a second gate driving circuit disposed in the border area; and wherein the first gate driving circuit is disposed on a side of the first active area away from the second active area, the second gate driving circuit is disposed on a side of the second active area close to the irregular-shaped area, and the first gate driving circuit and the second gate driving circuit are arranged in the extending direction of the first signal line and the second signal line.” To buttress his arguments, applicant further argued that:
“First, in response to the discussion on pages 6-7 of the Office Action, Lee does not expressly state that scan drivers 210 and 213 are located in regions NA1 and NA2. To the contrary, as can be directly and unambiguously determined from, for example, FIG. 4 of Lee, scan drivers 210 and 213, which are components for driving display 200, are located outside regions NA1 and NA2, not within regions NA1 and NA2.”
The examiner strongly disagrees with applicant for at least the following reasons: As clearly illustrated in fig. 4 of Lee, first and second scan drivers (210, 213) are clearly disposed outside the pixel areas (AA1 and AA2), i.e., the first and second scan drivers are disposed respectively in the first periphery region (NA1-see fig. 3) and the second periphery region (NA2-see fig. 3).
“Second, amended claim 1 expressly requires specific circuit locations for the first gate driving circuit and the second gate driving circuit, namely, that “the first gate driving circuit is disposed on a side of the first active area away from the second active area, the second gate driving circuit is disposed on a side of the second active area close to the irregular-shaped area, and the first gate driving circuit and the second gate driving circuit are arranged in the extending direction of the first signal line and the second signal line.” These recited positional relationships are not disclosed by FIG. 4 of Lee.”
Again the examiner disagrees with applicant for at least the following reasons: The claim language reciting “the first gate driving circuit is disposed on a side of the first active area away from the second active area, the second gate driving circuit is disposed on a side of the second active area close to the irregular-shaped area, and the first gate driving circuit and the second gate driving circuit are arranged in the extending direction of the first signal line and the second signal line” can be broadly interpreted in many ways, for example, what constitutes “a side away”? Is it a side that is opposite or a side that is adjacent in a column direction? For example, the second scan driver 213 of Lee can be deemed to be closer to the irregular-shaped area than the first scan driver 210. The examiner therefore contends that the claim language is ambiguous and further contends that the current rejection in view of Lee is proper. Furthermore, arrangements of gate drivers along sides of non-quadrangular displays, as in the instant application, are readily available as may be illustrated in the non-applied reference listed below.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (US Patent 10,062,317 B2)-see fig. 6.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARDIS F AZONGHA whose telephone number is (571)270-7706. The examiner can normally be reached 10AM-7:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at (571)272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SARDIS F AZONGHA/Primary Examiner, Art Unit 2627
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