DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koenenkamp (US 2005/0147194).
Regarding claim 1, Koenenkamp teaches an LSK demodulator (figures 11 and 14) comprising:
a clock generation unit (310, 320, 360) configured to generate a first clock signal (RI; clk_0) and a second clock signal (RQ; clk_90) having the same frequency and having a phase difference of 90° (quadrature relationship) therebetween by using a reference clock signal (master clock 305) applied from an outside, an up signal (UP), and a down signal (DN);
a data recovery unit (331-332) configured to generate data recovery signals (outputs of 331-332) by processing an input signal (data input/line) according to the first clock signal (RI; clk_0) and the second clock signal (RQ; clk_90); and
a phase correction unit (335-336) configured to correct a phase (of RQ; clk_90) so that a portion of the second clock signal (RQ; clk_90) to be activated is located at a center of a data period (center point C is the ideal sampling point; para. [0043] and [0072]) by using the first clock signal (RI; clk_0) and the data recovery signals (outputs of 331-332).
As for claim 5, Koenenkamp teaches wherein the clock generation unit (310, 320, 360) comprises:
a quadrature phase clock generator (310) configured to receive the reference clock signal (master clock 305) to generate a first reference clock signal (I) and a second reference clock signal (Q) having a phase difference of 90° therebetween (quadrature signals),
wherein the first reference clock signal (I) and the second reference clock signal (Q) are used to generate the first clock signal (RI; clk_0) and the second clock signal (RQ; clk_90) together with the up signal (UP) and the down signal (DN).
Regarding 6, Koenenkamp teaches wherein the clock generation unit (310, 320, 360) further comprises:
a phase interpolator (320 is a phase interpolator; para. [0058]) configured to generate a signal that reflects a phase error of the first reference clock signal (I) and the second reference clock signal (Q) based on a cumulative difference between the up signal and the down signal (from phase position accumulator 360),
wherein phases of the first clock signal (RI; clk_0) and the second clock signal (RQ; clk_90) are dynamically corrected by using an output of the phase interpolator (320).
Allowable Subject Matter
Claims 2-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The best prior art reference of record, Koenenkamp, fails to teach:
“wherein the data recovery unit comprises: a first signal processing means including a first integrator configured to integrate the input signal according to the first clock signal and a first comparator configured to generate a first data recovery signal being one of the data recovery signals based on an output polarity of the first integrator; and a second signal processing means including a second integrator configured to integrate the input signal according to the second clock signal and a second comparator configured to generate a second data recovery signal being another one of the data recovery signals based on an output polarity of the second integrator.”, as set forth in claim 2.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang et al. (US 2009/0268801) teaches a demodulator (figure 4), comprising: a quadrature clock generator (30, 72, 74), a reference clock (10.8 MHz), recovery circuits (86, 92), and a phase corrector (94).
Van Funderburk (US 2015/0077050) teaches a wireless power transfer device (figure 13), comprising: an LSK demodulator (96) recovering digital data (para. [0014]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEVI GANNON whose telephone number is (571)272-7971. The examiner can normally be reached 7:00AM-4:30PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LEVI GANNON/Primary Examiner, Art Unit 2836 August 29, 2026
Prosecution Insights